bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	target/openrisc: Reorg tlb lookup	Richard Henderson	2018-07-03	1	-8/+0
*	target/openrisc: Increase the TLB size	Richard Henderson	2018-07-02	1	-1/+1
*	target/openrisc: Use identical sizes for ITLB and DTLB	Richard Henderson	2018-07-02	1	-6/+4
*	target/openrisc: Fix cpu_mmu_index	Richard Henderson	2018-07-02	1	-8/+15
*	target/openrisc: Reduce tlb to a single dimension	Richard Henderson	2018-07-02	1	-4/+2
*	target/openrisc: Remove indirect function calls for mmu	Richard Henderson	2018-07-02	1	-11/+0
*	target/openrisc: Merge tlb allocation into CPUOpenRISCState	Richard Henderson	2018-07-02	1	-2/+4
*	target/openrisc: Add print_insn_or1k	Richard Henderson	2018-07-02	1	-0/+1
*	cpu: get rid of unused cpu_init() defines	Igor Mammedov	2018-03-19	1	-2/+0
*	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov	2018-03-19	1	-0/+1
*	target/*/cpu.h: remove softfloat.h	Alex Bennée	2018-02-21	1	-1/+0
*	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	2018-01-25	1	-1/+1
*	openrisc: cleanup cpu type name composition	Igor Mammedov	2017-10-27	1	-0/+3
*	openrisc/cputimer: Perparation for Multicore	Stafford Horne	2017-10-20	1	-1/+3
*	openrisc: replace cpu_openrisc_init() with cpu_generic_init()	Igor Mammedov	2017-09-01	1	-3/+1
*	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	2017-05-04	1	-0/+10
*	target/openrisc: Remove duplicate features property	Stafford Horne	2017-05-04	1	-14/+2
*	target/openrisc: implement shadow registers	Stafford Horne	2017-05-04	1	-2/+13
*	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell	2017-04-21	1	-0/+7
*	target/openrisc: Optimize for r0 being zero	Richard Henderson	2017-02-13	1	-1/+4
*	target/openrisc: Tidy handling of delayed branches	Richard Henderson	2017-02-13	1	-7/+5
*	target/openrisc: Tidy ppc/npc implementation	Richard Henderson	2017-02-13	1	-1/+1
*	target/openrisc: Fix madd	Richard Henderson	2017-02-13	1	-3/+0
*	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson	2017-02-13	1	-2/+1
*	target/openrisc: Keep SR_CY and SR_OV in a separate variables	Richard Henderson	2017-02-13	1	-3/+10
*	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	2017-02-13	1	-2/+13
*	target/openrisc: Put SR[OVE] in TB flags	Richard Henderson	2017-02-13	1	-2/+2
*	target/openrisc: Implement lwa, swa	Richard Henderson	2017-02-13	1	-0/+3
*	target/openrisc: Rename the cpu from or32 to or1k	Richard Henderson	2017-02-13	1	-1/+1
*	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée	2017-01-13	1	-0/+3
*	Move target-* CPU file into a target/ folder	Thomas Huth	2016-12-20	1	-0/+411