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* target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson2017-02-131-3/+10
* target/openrisc: Keep SR_F in a separate variableRichard Henderson2017-02-131-2/+13
* target/openrisc: Put SR[OVE] in TB flagsRichard Henderson2017-02-131-2/+2
* target/openrisc: Implement lwa, swaRichard Henderson2017-02-131-0/+3
* target/openrisc: Rename the cpu from or32 to or1kRichard Henderson2017-02-131-1/+1
* qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2017-01-131-0/+3
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+411