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* target/openrisc: Tidy ppc/npc implementationRichard Henderson2017-02-131-18/+11Star
| | | | | | | | | | | | The NPC SPR is really only supposed to be used for FPGA debugging. It contains the same contents as PC, unless one plays games. Follow the or1ksim implementation in flushing delayed branch state when it is changed. The PPC SPR need not be updated every instruction, merely when we exit the TB or attempt to read its contents. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Optimize l.jal to nextRichard Henderson2017-02-131-1/+5
| | | | | | | | This allows the tcg optimizer to see, and fold, all of the constants involved in a GOT base register load sequence. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Fix maddRichard Henderson2017-02-131-9/+4Star
| | | | | | | | | | Note that the specification for lf.madd.s is confused. It's the only mention of supposed FPMADDHI/FPMADDLO special registers. On the other hand, or1ksim implements a somewhat normal non-fused multiply and add. Mirror that. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Implement muld, muldu, macu, msbuRichard Henderson2017-02-131-0/+108
| | | | | Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson2017-02-131-57/+63
| | | | | | | Significantly simplifies the implementation of the use of MAC. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Implement msyncRichard Henderson2017-02-131-0/+1
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Enable trap, csync, msync, psync for user modeRichard Henderson2017-02-131-32/+0Star
| | | | | | | | Not documented as disabled for user mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Use movcond where appropriateRichard Henderson2017-02-131-14/+14
| | | | | Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson2017-02-131-79/+40Star
| | | | | | This significantly streamlines carry and overflow production. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Keep SR_F in a separate variableRichard Henderson2017-02-131-64/+40Star
| | | | | | | This avoids having to keep merging and extracting the flag from SR. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Invert the decoding in dec_calcRichard Henderson2017-02-131-207/+95Star
| | | | | | | | Decoding the opcodes in the right order reduces by 100+ lines. Also, it happens to put the opcodes in the same order as Chapter 17. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Put SR[OVE] in TB flagsRichard Henderson2017-02-131-9/+15
| | | | | | Removes a call at execution time for overflow exceptions. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Streamline arithmetic and OVERichard Henderson2017-02-131-249/+177Star
| | | | | | | | | Fix incorrect overflow calculation. Move overflow exception check to a helper function, to eliminate inline branches. Remove some incorrect special casing of R0. Implement multiply inline. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Rationalize immediate extractionRichard Henderson2017-02-131-58/+40Star
| | | | | | | | The architecture manual is consistent in using "I" for signed fields and "K" for unsigned fields. Mirror that. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Tidy insn dumpingRichard Henderson2017-02-131-24/+12Star
| | | | | | | | Avoids warnings from unused variables etc. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Implement lwa, swaRichard Henderson2017-02-131-0/+58
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-openrisc: Use clz and ctz opcodesRichard Henderson2017-01-101-2/+4
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+1783
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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