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* exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé2022-02-212-0/+2
* Remove unnecessary minimum_version_id_old fieldsPeter Maydell2022-01-281-1/+0Star
* target/openrisc: Make openrisc_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-024-14/+6Star
* target/openrisc: Drop checks for singlestep_enabledRichard Henderson2021-10-161-15/+3Star
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-2/+0Star
* target/openrisc: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-144-7/+8
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-1/+1
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-17/+0Star
* target/openrisc: Use dc->zero in gen_add, gen_addcRichard Henderson2021-07-131-5/+5
* target/openrisc: Cache constant 0 in DisasContextRichard Henderson2021-07-131-6/+6
* target/openrisc: Use tcg_constant_tl for dc->R0Richard Henderson2021-07-131-8/+2Star
* target/openrisc: Use tcg_constant_*Richard Henderson2021-07-131-33/+9Star
* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell2021-07-121-8/+8
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| * target/openrisc: Use translator_use_goto_tbRichard Henderson2021-07-091-7/+8
| * tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé2021-07-091-1/+0Star
* | meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé2021-07-091-0/+2
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* hw/core: Constify TCGCPUOpsRichard Henderson2021-05-271-1/+1
* cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-271-0/+8
* Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth2021-05-021-1/+0Star
* target/openrisc: fix icount handling for timer instructionsPavel Dovgalyuk2021-04-011-0/+15
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-4/+13
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* migration: Replace migration's JSON writer by the general oneMarkus Armbruster2020-12-191-1/+1
* target/openrisc: Move pic_cpu code into CPU object properPeter Maydell2020-12-152-1/+32
* target/openrisc: Remove dead code attempting to check "is timer disabled"Peter Maydell2020-11-171-3/+0Star
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-4/+7
* meson: targetPaolo Bonzini2020-08-214-17/+25
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-213-5/+5
* softfloat: Name compare relation enumRichard Henderson2020-05-191-2/+2
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-03-192-5/+5
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| * cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-182-5/+5
* | gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-172-2/+2
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* cpu: Use cpu_class_set_parent_reset()Greg Kurz2020-01-241-2/+1Star
* Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into stagingPeter Maydell2020-01-171-1/+1
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| * target/openrisc: Fix FPCSR mask to allow setting DZFStafford Horne2020-01-171-1/+1
* | tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
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* target/openrisc: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
* target/openrisc: Update cpu "any" to v1.3Richard Henderson2019-09-041-1/+1
* target/openrisc: Implement l.adrpRichard Henderson2019-09-043-0/+16
* target/openrisc: Implement move to/from FPCSRRichard Henderson2019-09-045-5/+38
* target/openrisc: Implement unordered fp comparisonsRichard Henderson2019-09-045-0/+145
* target/openrisc: Add support for ORFPX64A32Richard Henderson2019-09-046-3/+332
* target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson2019-09-042-50/+36Star
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