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* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-2/+2
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-102-11/+20
* tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson2019-05-101-6/+0Star
* target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson2019-05-103-36/+39
* target/openrisc: Fix LGPL information in the file headersThomas Huth2019-05-088-8/+8
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster2019-04-181-1/+1
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-182-8/+6Star
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-182-11/+6Star
* target/openrisc: Fix LGPL version numberThomas Huth2019-01-307-7/+7
* vmstate: constify VMStateFieldMarc-André Lureau2018-11-271-2/+3
* decodetree: Remove "insn" argument from trans_* expandersRichard Henderson2018-10-312-112/+111Star
* target/openrisc: Fix writes to interrupt mask registerStafford Horne2018-07-031-1/+1
* target/openrisc: Fix delay slot exception flag to match specStafford Horne2018-07-031-7/+12
* linux-user: Implement signals for openriscRichard Henderson2018-07-031-0/+1
* target/openrisc: Reorg tlb lookupRichard Henderson2018-07-032-170/+88Star
* target/openrisc: Increase the TLB sizeRichard Henderson2018-07-023-6/+7
* target/openrisc: Stub out handle_mmu_fault for softmmuRichard Henderson2018-07-021-30/+5Star
* target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson2018-07-024-18/+16Star
* target/openrisc: Fix cpu_mmu_indexRichard Henderson2018-07-026-32/+49
* target/openrisc: Fix tlb flushing in mtsprRichard Henderson2018-07-021-6/+15
* target/openrisc: Reduce tlb to a single dimensionRichard Henderson2018-07-024-32/+30Star
* target/openrisc: Merge mmu_helper.c into mmu.cRichard Henderson2018-07-023-41/+12Star
* target/openrisc: Remove indirect function calls for mmuRichard Henderson2018-07-027-119/+32Star
* target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson2018-07-026-49/+46Star
* target/openrisc: Form the spr index from tcgRichard Henderson2018-07-023-15/+14Star
* target/openrisc: Exit the TB after l.mtsprRichard Henderson2018-07-021-1/+16
* target/openrisc: Split out is_userRichard Henderson2018-07-021-15/+12Star
* target/openrisc: Link more translation blocksRichard Henderson2018-07-021-41/+55
* target/openrisc: Fix singlestep_enabledRichard Henderson2018-07-021-18/+17Star
* target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson2018-07-022-5/+4Star
* target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson2018-07-021-4/+0Star
* target/openrisc: Log interruptsRichard Henderson2018-07-021-5/+25
* target/openrisc: Add print_insn_or1kRichard Henderson2018-07-025-115/+179
* target/openrisc: Fix mtspr shadow gprsRichard Henderson2018-07-021-0/+1
* Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into st...Peter Maydell2018-06-041-3/+3
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| * tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-3/+3
* | target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé2018-06-011-1/+0Star
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* target/openrisc: Merge disas_openrisc_insnRichard Henderson2018-05-141-9/+4Star
* target/openrisc: Convert dec_floatRichard Henderson2018-05-142-230/+149Star
* target/openrisc: Convert dec_compiRichard Henderson2018-05-142-58/+70
* target/openrisc: Convert dec_compRichard Henderson2018-05-142-62/+73
* target/openrisc: Convert dec_MRichard Henderson2018-05-142-28/+16Star
* target/openrisc: Convert dec_logicRichard Henderson2018-05-142-36/+32Star
* target/openrisc: Convert dec_macRichard Henderson2018-05-142-33/+27Star
* target/openrisc: Convert dec_calcRichard Henderson2018-05-142-169/+229
* target/openrisc: Convert remainder of dec_misc insnsRichard Henderson2018-05-142-153/+141Star
* target/openrisc: Convert memory insnsRichard Henderson2018-05-142-139/+160
* target/openrisc: Convert branch insnsRichard Henderson2018-05-142-78/+84
* target/openrisc: Start conversion to decodetree.pyRichard Henderson2018-05-143-43/+78
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