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* target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in int_helper.cMark Cave-Ayland2019-02-041-110/+45Star
| | | | | | | | | | | | Following on from the previous work, there are numerous endian-related hacks in int_helper.c that can now be replaced with Vsr* macros. There are also a few places where the VECTOR_FOR_INORDER_I macro can be replaced with a normal iterator since the processing order is irrelevant. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: remove ROTRu32 and ROTRu64 macros from int_helper.cMark Cave-Ayland2019-02-041-28/+20Star
| | | | | | | | | | Richard points out that these macros suffer from a -fsanitize=shift bug in that they improperly handle n == 0 turning it into a shift by 32/64 respectively. Replace them with QEMU's existing ror32() and ror64() functions instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: simplify VEXT_SIGNED macro in int_helper.cMark Cave-Ayland2019-02-041-7/+7
| | | | | | | | | | As pointed out by Richard: it does not need the mask argument, nor does it need the recast argument. The masking is implied by the cast argument, and the recast is implied by the assignment. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: eliminate use of EL_IDX macros from int_helper.cMark Cave-Ayland2019-02-041-39/+27Star
| | | | | | | | | These macros can be eliminated by instead using the relavant Vsr* macros in the few locations where they appear. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: eliminate use of HI_IDX and LO_IDX macros from int_helper.cMark Cave-Ayland2019-02-041-95/+85Star
| | | | | | | | | | | | The original purpose of these macros was to correctly reference the high and low parts of the VSRs regardless of the host endianness. Replace these direct references to high and low parts with the relevant VsrD macro instead, and completely remove the now-unused HI_IDX and LO_IDX macros. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: rework vmul{e,o}{s,u}{b,h,w} instructions to use Vsr* macrosMark Cave-Ayland2019-02-041-21/+27
| | | | | | | | | | | | The current implementations make use of the endian-specific macros HI_IDX and LO_IDX directly to calculate array offsets. Rework the implementation to use the Vsr* macros so that these per-endian references can be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: rework vmrg{l,h}{b,h,w} instructions to use Vsr* macrosMark Cave-Ayland2019-02-041-35/+19Star
| | | | | | | | | | | The current implementations make use of the endian-specific macros MRGLO/MRGHI and also reference HI_IDX and LO_IDX directly to calculate array offsets. Rework the implementation to use the Vsr* macros so that these per-endian references can be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc: remove the interrupt presenters from under PowerPCCPUCédric Le Goater2019-02-041-5/+0Star
| | | | | | | | | These fields have now been replaced by equivalents under the machine data. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: implement complete set of Vsr* macrosMark Cave-Ayland2019-02-041-1/+8
| | | | | | | | | This prepares us for eliminating the use of direct array access within the VMX instruction implementations. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc/kvm: Drop useless include directiveGreg Kurz2019-02-041-1/+0Star
| | | | | | | | | It has been there since the enablement of PR KVM for PAPR, ie, commit f61b4bedaf35 in 2011. Not sure why at that time, but it is definitely not needed with the current code. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc: e6500 registers SPR 604 twiceJon Diekema2019-01-241-8/+0Star
| | | | | | | | | | | | | | | | | | | | When using the e6500 CPU, QEMU generates a fatal error after complaining about registering SPR 604 twice. Building and testing with commit 9b2e891ec5ccdb4a7d583b77988848282606fdea shows the issue: qemu-system-ppc64 --version QEMU emulator version 3.1.50 (v3.1.0-456-g9b2e891ec5-dirty) Copyright (c) 2003-2018 Fabrice Bellard and the QEMU Project developers qemu-system-ppc64 -M none -cpu e6500 Error: Trying to register SPR 604 (25c) twice ! Signed-off-by: Jon Diekema <jon.diekema@ge.com> Message-Id: <CALvuzg43uSodseEHjNaRcPFBKKPTY2mcppUbYgiLL=QO9RxX_Q@mail.gmail.com> [removed duplicated mail header in the commit message] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 modeThomas Huth2019-01-221-4/+5
| | | | | | | | | | | | | | | | | | | | When compiling the ppc code with clang and -std=gnu99, there are a couple of warnings/errors like this one: CC ppc64-softmmu/hw/intc/xics.o In file included from hw/intc/xics.c:35: include/hw/ppc/xics.h:43:25: error: redefinition of typedef 'ICPState' is a C11 feature [-Werror,-Wtypedef-redefinition] typedef struct ICPState ICPState; ^ target/ppc/cpu.h:1181:25: note: previous definition is here typedef struct ICPState ICPState; ^ Work around the problems by including the proper headers in spapr.h and by using struct forward declarations in cpu.h. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the CPUCédric Le Goater2019-01-081-1/+2
| | | | | | | | Now that the 'intc' pointer is only used by the XICS interrupt mode, let's make things clear and use a XICS type and name. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xive: introduce a XiveTCTX pointer under PowerPCCPUCédric Le Goater2019-01-081-0/+2
| | | | | | | | which will be used by the machine only when the XIVE interrupt mode is in use. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: replace AVR* macros with Vsr* macrosMark Cave-Ayland2019-01-081-17/+13Star
| | | | | | | | | Now that the VMX and VSR register sets have been combined, the same macros can be used to access both AVR and VSR field members. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: move FP and VMX registers into aligned vsr register arrayMark Cave-Ayland2019-01-0812-70/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VSX register array is a block of 64 128-bit registers where the first 32 registers consist of the existing 64-bit FP registers extended to 128-bit using new VSR registers, and the last 32 registers are the VMX 128-bit registers as show below: 64-bit 64-bit +--------------------+--------------------+ | FP0 | | VSR0 +--------------------+--------------------+ | FP1 | | VSR1 +--------------------+--------------------+ | ... | ... | ... +--------------------+--------------------+ | FP30 | | VSR30 +--------------------+--------------------+ | FP31 | | VSR31 +--------------------+--------------------+ | VMX0 | VSR32 +-----------------------------------------+ | VMX1 | VSR33 +-----------------------------------------+ | ... | ... +-----------------------------------------+ | VMX30 | VSR62 +-----------------------------------------+ | VMX31 | VSR63 +-----------------------------------------+ In order to allow for future conversion of VSX instructions to use TCG vector operations, recreate the same layout using an aligned version of the existing vsr register array. Since the old fpr and avr register arrays are removed, the existing callers must also be updated to use the correct offset in the vsr register array. This also includes switching the relevant VMState fields over to using subarrays to make sure that migration is preserved. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: merge ppc_vsr_t and ppc_avr_t union typesMark Cave-Ayland2019-01-083-45/+39Star
| | | | | | | | | | | | | | | Since the VSX registers are actually a superset of the VMX registers then they can be represented by the same type. Merge ppc_avr_t into ppc_vsr_t and change ppc_avr_t to be a simple typedef alias. Note that due to a difference in the naming of the float32 member between ppc_avr_t and ppc_vsr_t, references to the ppc_avr_t f member must be replaced with f32 instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_envMark Cave-Ayland2019-01-082-45/+18Star
| | | | | | | | | | | Instead of accessing the FPR, VMX and VSX registers through static arrays of TCGv_i64 globals, remove them and change the helpers to load/store data directly within cpu_env. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for ↵Mark Cave-Ayland2019-01-081-224/+638
| | | | | | | | | | | | | | | VSR register access These helpers allow us to move VSR register values to/from the specified TCGv_i64 argument. To prevent VSX helpers accessing the cpu_vsr array directly, add extra TCG temporaries as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: introduce get_avr64() and set_avr64() helpers for VMX register ↵Mark Cave-Ayland2019-01-082-33/+124
| | | | | | | | | | | | | | | access These helpers allow us to move AVR register values to/from the specified TCGv_i64 argument. To prevent VMX helpers accessing the cpu_avr{l,h} arrays directly, add extra TCG temporaries as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: introduce get_fpr() and set_fpr() helpers for FP register accessMark Cave-Ayland2019-01-082-110/+386
| | | | | | | | | | | | | These helpers allow us to move FP register values to/from the specified TCGv_i64 argument in the VSR helpers to be introduced shortly. To prevent FP helpers accessing the cpu_fpr array directly, add extra TCG temporaries as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: switch EXTRACT_HELPER macros over to use sextract32/extract32Mark Cave-Ayland2019-01-081-4/+4
| | | | | | | | | These ensure that we consistently handle signed and unsigned extensions correctly when decoding immediates from instruction opcodes. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: fix typo in SIMM5 extraction helperMark Cave-Ayland2019-01-081-1/+1
| | | | | | | | As the macro name suggests, the argument should be signed and not unsigned. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* Changes requirement for "vsubsbs" instructionPaul A. Clarke2018-12-201-1/+1
| | | | | | | | | | Changes requirement for "vsubsbs" instruction, which has been supported since ISA 2.03. (Please see section 5.9.1.2 of ISA 2.03) Reported-by: Paul A. Clarke <pc@us.ibm.com> Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Signed-off-by: Leonardo Bras <leonardo@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)Greg Kurz2018-12-201-3/+3
| | | | | | | | Because it is a recommended coding practice (see HACKING). Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: tcg: Implement addex instructionSuraj Jitindar Singh2018-12-201-27/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the addex instruction introduced in ISA V3.00 in qemu tcg. The add extended using alternate carry bit (addex) instruction performs the same operation as the add extended (adde) instruction, but using the overflow (ov) field in the fixed point exception register (xer) as the carry in and out instead of the carry (ca) field. The instruction has a Z23-form, not an XO form, as follows: ------------------------------------------------------------------ | 31 | RT | RA | RB | CY | 170 | 0 | ------------------------------------------------------------------ 0 6 11 16 21 23 31 32 However since the only valid form of the instruction defined so far is CY = 0, we can treat this like an XO form instruction. There is no dot form (addex.) of the instruction and the summary overflow (so) bit in the xer is not modified by this instruction. For simplicity we reuse the gen_op_arith_add function and add a function argument to specify where the carry in input should come from and the carry out output be stored (note must be the same location). Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Remove silly GETFIELD/SETFIELD/MASK_TO_LSH macrosDavid Gibson2018-12-201-12/+0Star
| | | | | | | | | | | The (only) obvious use for these macros is constructing and parsing guest visible register fields. But the way they're constructed, they're only valid when used on a *host* long, whose size shouldn't be visible to the guest at all. They also have no current users, so just get rid of them. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: fix the PPC_BIT definitionsCédric Le Goater2018-12-201-3/+3
| | | | | | | | | | Change the PPC_BIT macro to use ULL instead of UL and the PPC_BIT32 and PPC_BIT8 not to use any suffix. This fixes a compile breakage on windows. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* vmstate: constify VMStateFieldMarc-André Lureau2018-11-271-6/+8
| | | | | | | | Because they are supposed to remain const. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20181114132931.22624-1-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* ppc/spapr_caps: Add SPAPR_CAP_NESTED_KVM_HVSuraj Jitindar Singh2018-11-082-0/+24
| | | | | | | | | | | | | | Add the spapr cap SPAPR_CAP_NESTED_KVM_HV to be used to control the availability of nested kvm-hv to the level 1 (L1) guest. Assuming a hypervisor with support enabled an L1 guest can be allowed to use the kvm-hv module (and thus run it's own kvm-hv guests) by setting: -machine pseries,cap-nested-hv=true or disabled with: -machine pseries,cap-nested-hv=false Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Add one reg id for ptcrSuraj Jitindar Singh2018-11-081-5/+5
| | | | | | | | | | | | | The ptcr (partition table control register) is used to store the address and size of the partition table. For nested kvm-hv we have a level 1 guest register the location of it's partition table with the hypervisor. Thus to support migration we need to be able to read this out of kvm and restore it post migration. Add the one reg id for the ptcr. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* This patch fixes processing of rfi instructions in icount mode.Maria Klimushenkova2018-11-081-0/+12
| | | | | | | | | | | In this mode writing to interrupt/peripheral state is controlled by can_do_io flag. This flag must be set explicitly before helper function invocation. Signed-off-by: Maria Klimushenkova <maria.klimushenkova@ispras.ru> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: fix mtmsr instruction for icountPavel Dovgalyuk2018-11-081-0/+12
| | | | | | | | | | | | This patch fixes processing of mtmsr instructions in icount mode. In this mode writing to interrupt/peripheral state is controlled by can_do_io flag. This flag must be set explicitly before helper function invocation. Signed-off-by: Maria Klimushenkova <maria.klimushenkova@ispras.ru> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Split out float_invalid_cvtRichard Henderson2018-11-081-39/+28Star
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Split out float_invalid_op_divRichard Henderson2018-11-081-28/+24Star
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Split out float_invalid_op_mulRichard Henderson2018-11-081-23/+20Star
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Split out float_invalid_op_addsubRichard Henderson2018-11-081-34/+26Star
| | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Introduce fp number classificationRichard Henderson2018-11-081-43/+51
| | | | | | | | Having a separate, logical classifiation of numbers will unify more error paths for different formats. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Remove float_check_statusRichard Henderson2018-11-081-42/+35Star
| | | | | | | | | Use do_float_check_status directly, so that we don't get confused about which return address we're using. And definitely don't use helper_float_check_status. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Split up float_invalid_op_excpRichard Henderson2018-11-081-163/+181
| | | | | | | | | | | The always_inline trick only works if the function is always called from the outer-most helper. But it isn't, so pass in the outer-most return address. There's no need for a switch statement whose argument is always a constant. Unravel the switch and goto via more helpers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: add external PID supportRoman Kapl2018-11-088-45/+387
| | | | | | | | | | | | | | | | | | | | | | | External PID is a mechanism present on BookE 2.06 that enables application to store/load data from different address spaces. There are special version of some instructions, which operate on alternate address space, which is specified in the EPLC/EPSC regiser. This implementation uses two additional MMU modes (mmu_idx) to provide the address space for the load and store instructions. The QEMU TLB fill code was modified to recognize these MMU modes and use the values in EPLC/EPSC to find the proper entry in he PPC TLB. These two QEMU TLBs are also flushed on each write to EPLC/EPSC. Following instructions are implemented: dcbfep dcbstep dcbtep dcbtstep dcbzep dcbzlep icbiep lbepx ldepx lfdepx lhepx lwepx stbepx stdepx stfdepx sthepx stwepx. Following vector instructions are not: evlddepx evstddepx lvepx lvepxl stvepx stvepxl. Signed-off-by: Roman Kapl <rka@sysgo.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' ↵Peter Maydell2018-10-231-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Error reporting patches for 2018-10-22 # gpg: Signature made Mon 22 Oct 2018 13:20:23 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2018-10-22: (40 commits) error: Drop bogus "use error_setg() instead" admonitions vpc: Fail open on bad header checksum block: Clean up bdrv_img_create()'s error reporting vl: Simplify call of parse_name() vl: Fix exit status for -drive format=help blockdev: Convert drive_new() to Error vl: Assert drive_new() does not fail in default_drive() fsdev: Clean up error reporting in qemu_fsdev_add() spice: Clean up error reporting in add_channel() tpm: Clean up error reporting in tpm_init_tpmdev() numa: Clean up error reporting in parse_numa() vnc: Clean up error reporting in vnc_init_func() ui: Convert vnc_display_init(), init_keyboard_layout() to Error ui/keymaps: Fix handling of erroneous include files vl: Clean up error reporting in device_init_func() vl: Clean up error reporting in parse_fw_cfg() vl: Clean up error reporting in mon_init_func() vl: Clean up error reporting in machine_set_property() vl: Clean up error reporting in chardev_init_func() qom: Clean up error reporting in user_creatable_add_opts_foreach() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * cpus hw target: Use warn_report() & friends to report warningsMarkus Armbruster2018-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calling error_report() in a function that takes an Error ** argument is suspicious. Convert a few that are actually warnings to warn_report(). While there, split a warning consisting of multiple sentences to conform to conventions spelled out in warn_report()'s contract. Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Fam Zheng <famz@redhat.com> Cc: Wei Huang <wei@redhat.com> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20181017082702.5581-5-armbru@redhat.com>
* | target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128Richard Henderson2018-10-193-62/+88
|/ | | | | Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/ppc/cpu-models: Re-group the 970 CPUs together againThomas Huth2018-09-251-21/+19Star
| | | | | | | | | | | The addition of the POWER9 CPUs divided the entries for the 970 CPUs, which is a little bit confusing when you look at the code. So let's re-group the 970 CPUs together again, and since these chips have been based on the POWER4 processor, move them also in front of the POWER5 chips now. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc/kvm: set vcpu as online/offlineNikunj A Dadhania2018-09-052-0/+16
| | | | | | | | | | | | Set the newly added register(KVM_REG_PPC_ONLINE) to indicate if the vcpu is online(1) or offline(0) KVM will use this information to set the RWMR register, which controls the PURR and SPURR accumulation. CC: paulus@samba.org Signed-off-by: Nikunj A Dadhania <nikunj@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc: Remove deprecated ppcemb targetThomas Huth2018-08-285-58/+5Star
| | | | | | | | | | | There is no known available OS for ppc around anymore that uses page sizes below 4k, so it does not make much sense that we keep wasting our time on building and testing the ppcemb-softmmu target. It has been deprecated since two releases, and nobody complained, so let's remove this now. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc: add DBCR based debuggingRoman Kapl2018-08-214-33/+107
| | | | | | | | | Add support for DBCR (debug control register) based debugging as used on BookE ppc. So far supports only branch and single-step events, but these are the important ones. GDB in Linux guest can now do single-stepping. Signed-off-by: Roman Kapl <rka@sysgo.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: simplify bcdadd/sub functionsYasmin Beatriz2018-08-211-31/+18Star
| | | | | | | | | | After solving a corner case in bcdsub, this patch simplifies the logic of both bcdadd/sub instructions by removing some unnecessary local flags. This commit also rearranges some if-else conditions in bcdadd to make it easier to read. Signed-off-by: Yasmin Beatriz <yasmins@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: bcdsub fix sign when result is zeroYasmin Beatriz2018-08-211-0/+3
| | | | | | | | | When the result of bcdsub is equal to zero, the result sign may be set to negative in some cases, and this does not follow the Power ISA specifications as to decimal integer arithmetic instructions. Signed-off-by: Yasmin Beatriz <yasmins@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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