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* target/ppc: fix msgsync insns flagsMatheus Ferst2022-10-281-1/+1
* target/ppc: fix msgclr/msgsnd insns flagsMatheus Ferst2022-10-281-2/+2
* target/ppc: Convert to tcg_ops restore_state_to_opcRichard Henderson2022-10-262-6/+10
* target/ppc: Fix xvcmp* clearing FI bitVíctor Colombo2022-10-171-1/+0Star
* target/ppc: restore powerpc_excp_booke doorbell interruptsNicholas Piggin2022-10-171-0/+6
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2022-10-131-0/+4
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| * kvm: allow target-specific accelerator propertiesPaolo Bonzini2022-10-101-0/+4
* | dump: Replace opaque DumpState pointer with a typed oneJanosch Frank2022-10-062-11/+11
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* hw/core: Add CPUClass.get_pcRichard Henderson2022-10-041-0/+8
* target/ppc: Clear fpstatus flags on helpers missing itVíctor Colombo2022-09-201-11/+26
* target/ppc: Zero second doubleword of VSR registers for FPR insnsVíctor Colombo2022-09-201-0/+8
* target/ppc: Set OV32 when OV is setVíctor Colombo2022-09-201-2/+2
* target/ppc: Zero second doubleword for VSX madd instructionsVíctor Colombo2022-09-201-1/+1
* target/ppc: Set result to QNaN for DENBCD when VXCVI occursVíctor Colombo2022-09-201-2/+24
* target/ppc: Zero second doubleword in DFP instructionsVíctor Colombo2022-09-201-1/+4
* target/ppc: Remove unused xer_* macrosVíctor Colombo2022-09-201-4/+0Star
* target/ppc: Remove extra space from s128 field in ppc_vsr_tVíctor Colombo2022-09-201-1/+1
* target/ppc: Merge fsqrt and fsqrts helpersVíctor Colombo2022-09-203-26/+17Star
* target/ppc: Move fsqrts to decodetreeVíctor Colombo2022-09-203-23/+2Star
* target/ppc: Move fsqrt to decodetreeVíctor Colombo2022-09-203-13/+24
* target/ppc: Implement hashstp and hashchkpVíctor Colombo2022-09-204-0/+8
* target/ppc: Implement hashst and hashchkVíctor Colombo2022-09-205-0/+128
* target/ppc: Add HASHKEYR and HASHPKEYR SPRsVíctor Colombo2022-09-202-0/+30
* accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson2022-09-061-2/+3
* target/ppc: Bugfix FP when OE/UE are setLucas Mateus Castro (alqotel)2022-08-312-2/+2
* target/ppc: Fix host PVR matching for KVMNicholas Piggin2022-08-303-23/+76
* ppc: Remove redundant macro MSR_BOOK3S_MASK.Yonggang Luo2022-08-041-1/+0Star
* target/ppc: Implement new wait variantsNicholas Piggin2022-07-282-8/+91
* target/ppc: Check page dir/table base alignmentLeandro Lupori2022-07-181-4/+24
* target/ppc: Improve Radix xlate level validationLeandro Lupori2022-07-181-11/+38
* ppc: Check partition and process table alignmentLeandro Lupori2022-07-182-4/+18
* target/ppc: check tb_env != 0 before printing TBU/TBL/DECRMatheus Ferst2022-07-182-10/+17
* target/ppc: Implement slbiagLucas Coutinho2022-07-184-0/+46
* target/ppc: Move slbsync to decodetreeLucas Coutinho2022-07-183-17/+16Star
* target/ppc: Move slbfee to decodetreeLucas Coutinho2022-07-185-28/+38
* target/ppc: Move slbmfee to decodetreeLucas Coutinho2022-07-185-15/+17
* target/ppc: Move slbmfev to decodetreeLucas Coutinho2022-07-185-14/+18
* target/ppc: Move slbmte to decodetreeLucas Coutinho2022-07-185-16/+18
* target/ppc: Move slbia to decodetreeLucas Coutinho2022-07-185-19/+21
* target/ppc: Move slbieg to decodetreeLucas Coutinho2022-07-185-15/+17
* target/ppc: Move slbie to decodetreeLucas Coutinho2022-07-185-15/+23
* target/ppc: add macros to check privilege levelMatheus Ferst2022-07-182-5/+23
* target/ppc: receive DisasContext explicitly in GEN_PRIVMatheus Ferst2022-07-182-149/+154
* target/ppc: Implement ISA 3.00 tlbie[l]Leandro Lupori2022-07-184-0/+188
* target/ppc: Move tlbie[l] to decode treeLeandro Lupori2022-07-184-64/+99
* target/ppc: fix exception error code in spr_write_excp_vectorMatheus Ferst2022-07-181-3/+3
* target/ppc: fix PMU Group A register read/write exceptionsMatheus Ferst2022-07-181-5/+5
* target/ppc: fix exception error code in helper_{load, store}_dcrMatheus Ferst2022-07-182-4/+4
* target/ppc: remove mfdcrux and mtdcruxMatheus Ferst2022-07-182-22/+2Star
* target/ppc: fix exception error value in slbfeeMatheus Ferst2022-07-181-2/+2
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-05 03:53:17 +0100