bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
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*	cpu: Use cpu_class_set_parent_reset()	Greg Kurz	2020-01-24	1	-2/+1
*	target/riscv: Remove atomic accesses to MIP CSR	Alistair Francis	2019-11-14	1	-3/+2
*	RISC-V: Implement cpu_do_transaction_failed	Palmer Dabbelt	2019-10-28	1	-1/+1
*	target/riscv: Use both register name and ABI name	Atish Patra	2019-09-17	1	-8/+11
*	target/riscv: rationalise softfloat includes	Alex Bennée	2019-08-19	1	-0/+1
*	RISC-V: Clear load reservations on context switch and SC	Joel Sing	2019-06-26	1	-0/+1
*	RISC-V: Add support for the Zicsr extension	Palmer Dabbelt	2019-06-26	1	-0/+1
*	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt	2019-06-26	1	-0/+1
*	target/riscv: Add support for disabling/enabling Counters	Alistair Francis	2019-06-25	1	-0/+1
*	target/riscv: Remove user version information	Alistair Francis	2019-06-25	1	-23/+9
*	target/riscv: Require either I or E base extension	Alistair Francis	2019-06-25	1	-0/+6
*	target/riscv: Set privledge spec 1.11.0 as default	Alistair Francis	2019-06-25	1	-3/+5
*	target/riscv: Restructure deprecatd CPUs	Alistair Francis	2019-06-24	1	-8/+10
*	target/riscv: Implement riscv_cpu_unassigned_access	Michael Clark	2019-06-24	1	-0/+1
*	target/riscv: Allow setting ISA extensions via CPU props	Alistair Francis	2019-06-24	1	-2/+68
*	qemu-common: Move qemu_isalnum() etc. to qemu/ctype.h	Markus Armbruster	2019-06-11	1	-0/+1
*	cpu: Introduce cpu_set_cpustate_pointers	Richard Henderson	2019-06-10	1	-2/+1
*	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis	2019-05-24	1	-0/+14
*	target/riscv: Create settable CPU properties	Alistair Francis	2019-05-24	1	-0/+49
*	target/riscv: Remove spaces from register names	Richard Henderson	2019-05-24	1	-8/+8
*	target/riscv: Convert to CPUClass::tlb_fill	Richard Henderson	2019-05-10	1	-3/+2
*	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	2019-04-18	1	-19/+18
*	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	2019-04-18	1	-13/+4
*	target/riscv: Remove unused struct	Alistair Francis	2019-03-19	1	-6/+0
*	RISC-V: Add hooks to use the gdb xml files.	Jim Wilson	2019-03-19	1	-1/+8
*	RISC-V: Add misa runtime write support	Michael Clark	2019-02-12	1	-1/+1
*	RISC-V: Implement existential predicates for CSRs	Michael Clark	2019-01-09	1	-0/+6
*	riscv/cpu: use device_class_set_parent_realize	Mao Zhongyi	2018-12-20	1	-2/+2
*	RISC-V: Update CSR and interrupt definitions	Michael Clark	2018-10-17	1	-2/+4
*	target/riscv: Honor CPU_DUMP_FPU	Richard Henderson	2018-05-18	1	-5/+7
*	RISC-V: Update E and I extension order	Michael Clark	2018-05-06	1	-1/+1
*	RISC-V: Convert cpu definition to future model	Michael Clark	2018-03-28	1	-54/+69
*	RISC-V: Fix riscv_isa_string memory size bug	Michael Clark	2018-03-20	1	-6/+6
*	RISC-V CPU Core Definition	Michael Clark	2018-03-06	1	-0/+432