summaryrefslogtreecommitdiffstats
path: root/target/riscv/cpu_bits.h
Commit message (Collapse)AuthorAgeFilesLines
* target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-271-0/+11
| | | | | | | | | Add a helper macro MSTATUS_MPV_ISSET() which will determine if the MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+3
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* target/riscv: Add virtual register swapping functionAlistair Francis2020-02-271-0/+7
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* target/riscv: Add the force HS exception modeAlistair Francis2020-02-271-0/+6
| | | | | | | | | | | Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit specifies if an exeption should be taken to HS mode no matter the current delegation status. This is used when an exeption must be taken to HS mode, such as when handling interrupts. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* target/riscv: Add the virtulisation modeAlistair Francis2020-02-271-0/+3
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* target/riscv: Rename the H irqs to VS irqsAlistair Francis2020-02-271-6/+6
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* target/riscv: Add support for the new execption numbersAlistair Francis2020-02-271-16/+19
| | | | | | | | | The v0.5 Hypervisor spec add new execption numbers, let's add support for those. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis2020-02-271-13/+21
| | | | | | | | | Add the Hypervisor CSRs to CPUState and at the same time (to avoid bisect issues) update the CSR macros for the v0.5 Hyp spec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
* target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis2019-09-171-17/+18
| | | | | | | | Update the Hypervisor CSR addresses to match the v0.4 spec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add the mcountinhibit CSRAlistair Francis2019-06-251-0/+1
| | | | | | | | | | | | | 1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1 but has different semantics. This patch enables the CSR for 1.11-based targets, which is trivial to implement because the counters in QEMU never tick (legal according to the spec). Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Fix counter access semantics, change commit message to indicate the behavior is fully emulated.] Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* Supply missing header guardsMarkus Armbruster2019-06-121-0/+5
| | | | | Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190604181618.19980-5-armbru@redhat.com>
* target/riscv: Add the HGATP register masksAlistair Francis2019-05-241-0/+11
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add the HSTATUS register masksAlistair Francis2019-05-241-0/+18
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviwed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add Hypervisor CSR macrosAlistair Francis2019-05-241-3/+6
| | | | | | | | Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis2019-05-241-3/+2Star
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* target/riscv: Mark privilege level 2 as reservedAlistair Francis2019-05-241-1/+1
| | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Fixes to CSR_* register macros.Jim Wilson2019-03-191-2/+33
| | | | | | | | | | This adds some missing CSR_* register macros, and documents some as being priv v1.9.1 specific. Signed-off-by: Jim Wilson <jimw@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190212230830.9160-1-jimw@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Add misa runtime write supportMichael Clark2019-02-121-0/+11
| | | | | | | | | | | | | | This patch adds support for writing misa. misa is validated based on rules in the ISA specification. 'E' is mutually exclusive with all other extensions. 'D' depends on 'F' so 'D' bit is dropped if 'F' is not present. A conservative approach to consistency is taken by flushing the translation cache on misa writes. misa_mask is added to the CPU struct to store the original set of extensions. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Update CSR and interrupt definitionsMichael Clark2018-10-171-318/+365
| | | | | | | | | | | | | | | | | * Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. * Remove erroneous until comments on machine mode interrupts. * Move together paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Improve page table walker spec complianceMichael Clark2018-09-041-2/+0Star
| | | | | | | | | | | | | | | | | | | - Inline PTE_TABLE check for better readability - Change access checks from ternary operator to if - Improve readibility of User page U mode and SUM test - Disallow non U mode from fetching from User pages - Add reserved PTE flag check: W or W|X - Add misaligned PPN check - Set READ protection for PTE X flag and mstatus.mxr - Use memory_region_is_ram in pte update Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V CPU Core DefinitionMichael Clark2018-03-061-0/+411
Add CPU state header, CPU definitions and initialization routines Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-03 23:35:47 +0100