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path:
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target
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riscv
/
insn32.decode
Commit message (
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Author
Age
Files
Lines
...
*
target/riscv: vector widening integer add and subtract
LIU Zhiwei
2020-07-02
1
-0
/
+16
*
target/riscv: vector single-width integer add and subtract
LIU Zhiwei
2020-07-02
1
-0
/
+10
*
target/riscv: add vector amo operations
LIU Zhiwei
2020-07-02
1
-0
/
+13
*
target/riscv: add fault-only-first unit stride load
LIU Zhiwei
2020-07-02
1
-0
/
+7
*
target/riscv: add vector index load and store instructions
LIU Zhiwei
2020-07-02
1
-0
/
+13
*
target/riscv: add vector stride load and store instructions
LIU Zhiwei
2020-07-02
1
-0
/
+32
*
target/riscv: add vector configure instruction
LIU Zhiwei
2020-07-02
1
-0
/
+5
*
target/riscv: Move the hfence instructions to the rvh decode
Alistair Francis
2020-06-19
1
-3
/
+5
*
target/riscv: Remove the hret instruction
Alistair Francis
2020-02-27
1
-1
/
+0
*
target/riscv: Add hfence instructions
Alistair Francis
2020-02-27
1
-9
/
+14
*
target/riscv: Name the argument sets for all of insn32 formats
Richard Henderson
2019-05-24
1
-3
/
+7
*
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
Bastian Koppelmann
2019-03-13
1
-1
/
+2
*
target/riscv: Move gen_arith_imm() decoding into trans_* functions
Bastian Koppelmann
2019-03-13
1
-1
/
+2
*
target/riscv: Convert RV priv insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+15
*
target/riscv: Convert RV32D insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+28
*
target/riscv: Convert RV32F insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+35
*
target/riscv: Convert RV32A insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+17
*
target/riscv: Convert RVXM insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+10
*
target/riscv: Convert RVXI csr insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+8
*
target/riscv: Convert RVXI fence insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+2
*
target/riscv: Convert RVXI arithmetic insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+25
*
target/riscv: Convert RV32I load/store insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+10
*
target/riscv: Convert RVXI branch insns to decodetree
Bastian Koppelmann
2019-03-13
1
-0
/
+19
*
target/riscv: Activate decodetree and implemnt LUI & AUIPC
Bastian Koppelmann
2019-03-13
1
-0
/
+30
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