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* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell2021-07-121-19/+1Star
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| * target/riscv: Use translator_use_goto_tbRichard Henderson2021-07-091-19/+1Star
* | meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé2021-07-091-0/+5
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* target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng2021-06-241-1/+1
* target/riscv: Use target_ulong for the DisasContext misaAlistair Francis2021-06-241-1/+1
* target/riscv: rvb: add b-ext version cpu optionFrank Chang2021-06-082-0/+26
* target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2021-06-082-0/+5
* target/riscv: rvb: add/shift with prefix zero-extendKito Cheng2021-06-083-0/+35
* target/riscv: rvb: address calculationKito Cheng2021-06-083-0/+62
* target/riscv: rvb: generalized or-combineFrank Chang2021-06-085-0/+64
* target/riscv: rvb: generalized reverseFrank Chang2021-06-086-0/+132
* target/riscv: rvb: rotate (left/right)Kito Cheng2021-06-083-0/+81
* target/riscv: rvb: shift onesKito Cheng2021-06-083-0/+74
* target/riscv: rvb: single-bit instructionsFrank Chang2021-06-083-0/+175
* target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2021-06-082-50/+43Star
* target/riscv: rvb: sign-extend instructionsKito Cheng2021-06-082-0/+15
* target/riscv: rvb: min/max instructionsKito Cheng2021-06-082-0/+28
* target/riscv: rvb: pack two words into one registerKito Cheng2021-06-083-0/+78
* target/riscv: rvb: logic-with-negateKito Cheng2021-06-082-0/+21
* target/riscv: rvb: count bits setFrank Chang2021-06-083-0/+21
* target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-084-1/+93
* target/riscv: reformat @sh format encoding for B-extensionKito Cheng2021-06-081-5/+5
* target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei2021-06-081-39/+50
* target/riscv/pmp: Add assert for ePMP operationsAlistair Francis2021-06-081-0/+4
* target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du2021-06-081-2/+5
* target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2021-06-082-4/+2Star
* target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé2021-06-081-0/+2
* target/riscv: fix wfi exception behaviorJose Martins2021-06-082-3/+9
* hw/core: Constify TCGCPUOpsRichard Henderson2021-05-271-1/+1
* cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-2/+2
* cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-271-0/+8
* cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé2021-05-271-2/+1Star
* target/riscv: Fix the RV64H decode commentAlistair Francis2021-05-111-1/+1
* target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis2021-05-115-72/+39Star
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-1114-150/+166
* target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis2021-05-111-6/+0Star
* target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis2021-05-111-6/+0Star
* target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis2021-05-114-28/+56
* target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis2021-05-113-14/+27
* target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2021-05-112-20/+15Star
* target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2021-05-112-7/+8
* target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2021-05-112-7/+5Star
* target/riscv: fix a typo with interrupt namesEmmanuel Blot2021-05-111-1/+1
* target/riscv: fix exception index on instruction access faultEmmanuel Blot2021-05-111-1/+3
* target/riscv: fix vrgather macro index variable type bugFrank Chang2021-05-111-2/+4
* target/riscv: Add ePMP support for the Ibex CPUAlistair Francis2021-05-111-0/+1
* target/riscv/pmp: Remove outdated commentAlistair Francis2021-05-111-4/+0Star
* target/riscv: Add a config option for ePMPHou Weiying2021-05-112-0/+11
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 00:58:03 +0100