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* target/s390x: vxeh2: Update for changes to vector shiftsDavid Miller2022-05-041-0/+3
| | | | | | | | | | Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-8-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/s390x: vxeh2: vector string searchDavid Miller2022-05-041-0/+6
| | | | | | | | | | Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-7-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/s390x: vxeh2: vector convert short/32bDavid Miller2022-05-041-0/+4
| | | | | | | | | | Signed-off-by: David Miller <dmiller423@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220428094708.84835-6-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the ↵David Miller2022-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | s390x implements: AND WITH COMPLEMENT (NCRK, NCGRK) NAND (NNRK, NNGRK) NOT EXCLUSIVE OR (NXRK, NXGRK) NOR (NORK, NOGRK) OR WITH COMPLEMENT (OCRK, OCGRK) SELECT (SELR, SELGR) SELECT HIGH (SELFHR) MOVE RIGHT TO LEFT (MVCRL) POPULATION COUNT (POPCNT) Resolves: https://gitlab.com/qemu-project/qemu/-/issues/737 Signed-off-by: David Miller <dmiller423@gmail.com> Message-Id: <20220223223117.66660-2-dmiller423@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* s390x/tcg: check for addressing exceptions for RRBE, SSKE and ISKEDavid Hildenbrand2021-09-061-3/+3
| | | | | | | | | | | | | | | Let's replace the ram_size check by a proper physical address space check (for example, to prepare for memory hotplug), trigger addressing exceptions and trace the return value of the storage key getter/setter. Provide an helper mmu_absolute_addr_valid() to be used in other context soon. Always test for "read" instead of "write" as we are not actually modifying the page itself. Signed-off-by: David Hildenbrand <david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210903155514.44772-5-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/s390x: Fix CC set by CONVERT TO FIXED/LOGICALUlrich Weigand2021-07-071-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | The FP-to-integer conversion instructions need to set CC 3 whenever a "special case" occurs; this is the case whenever the instruction also signals the IEEE invalid exception. (See e.g. figure 19-18 in the Principles of Operation.) However, qemu currently will set CC 3 only in the case where the input was a NaN. This is indeed one of the special cases, but there are others, most notably the case where the input is out of range of the target data type. This patch fixes the problem by switching these instructions to the "static" CC method and computing the correct result directly in the helper. (It cannot be re-computed later as the information about the invalid exception is no longer available.) This fixes a bug observed when running the wasmtime test suite under the s390x-linux-user target. Signed-off-by: Ulrich Weigand <ulrich.weigand@de.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210630105058.GA29130@oc3748833570.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)David Hildenbrand2021-06-211-0/+6
| | | | | | | | | | | | For IEEE functions, we can reuse the softfloat implementations. For the other functions, implement it generically for 32bit/64bit/128bit - carefully taking care of all weird special cases according to the tables defined in the PoP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-24-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand2021-06-211-0/+6
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-23-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand2021-06-211-0/+4
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-22-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand2021-06-211-0/+2
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-21-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDEDDavid Hildenbrand2021-06-211-0/+1
| | | | | | | | | 128 bit -> 64 bit, there is only a single element to process. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENEDDavid Hildenbrand2021-06-211-0/+1
| | | | | | | | | 64 bit -> 128 bit, there is only a single final element. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand2021-06-211-0/+4
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *David Hildenbrand2021-06-211-0/+12
| | | | | | | | | | In addition to 32/128bit variants, we also have to support the "Signal-on-QNaN (SQ)" bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT)David Hildenbrand2021-06-211-0/+4
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT)David Hildenbrand2021-06-211-0/+8
| | | | | | | | | | In case of 128bit, we always have a single element. Add new helpers for reading/writing 32/128 bit floats. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement VECTOR BIT PERMUTEDavid Hildenbrand2021-06-211-0/+1
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Simplify vflr64() handlingDavid Hildenbrand2021-06-211-1/+0Star
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Simplify vfll32() handlingDavid Hildenbrand2021-06-211-1/+0Star
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Simplify vfma64() handlingDavid Hildenbrand2021-06-211-2/+0Star
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Simplify vftci64() handlingDavid Hildenbrand2021-06-211-1/+0Star
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Simplify vfc64() handlingDavid Hildenbrand2021-06-211-6/+0Star
| | | | | | | | | | Pass the m5 field via simd_data() and don't provide specialized handlers for single-element variants. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Simplify vop64_2() handlingDavid Hildenbrand2021-06-211-6/+0Star
| | | | | | | | | | | | | | | | Let's rework our macros and simplify. We still need helper functions in most cases due to the different parameters types. Next, we'll only have 32/128bit variants for vfi and vfsq, so special case the others. Note that for vfsq, the XxC and erm passed in the simd_data() will never be set, resulting in the same behavior. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Simplify vop64_3() handlingDavid Hildenbrand2021-06-211-4/+0Star
| | | | | | | | | | | | Let's simplify, reworking our handler generation, passing the whole "m5" register content and not providing specialized handlers for "se", and reading/writing proper float64 values using new helpers. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Store r1/r2 for page-translation exceptions during MVPGDavid Hildenbrand2021-03-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The PoP states: When EDAT-1 does not apply, and a program interruption due to a page-translation exception is recognized by the MOVE PAGE instruction, the contents of the R1 field of the instruction are stored in bit positions 0-3 of location 162, and the contents of the R2 field are stored in bit positions 4-7. If [...] an ASCE-type, region-first-translation, region-second-translation, region-third-translation, or segment-translation exception was recognized, the contents of location 162 are unpredictable. So we have to write r1/r2 into the lowcore on page-translation exceptions. Simply handle all exceptions inside our mvpg helper now. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210315085449.34676-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MONITOR CALLDavid Hildenbrand2020-10-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Recent upstream Linux uses the MONITOR CALL instruction for things like BUG_ON() and WARN_ON(). We currently inject an operation exception when we hit a MONITOR CALL instruction - which is wrong, as the instruction is not glued to specific CPU features. Doing a simple WARN_ON_ONCE() currently results in a panic: [ 18.162801] illegal operation: 0001 ilc:2 [#1] SMP [ 18.162889] Modules linked in: [...] [ 18.165476] Kernel panic - not syncing: Fatal exception: panic_on_oops With a proper implementation, we now get: [ 18.242754] ------------[ cut here ]------------ [ 18.242855] WARNING: CPU: 7 PID: 1 at init/main.c:1534 [...] [ 18.242919] Modules linked in: [...] [ 18.246262] ---[ end trace a420477d71dc97b4 ]--- [ 18.259014] Freeing unused kernel memory: 4220K Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200918085122.26132-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Use tcg_gen_gvec_rotl{i,s,v}Richard Henderson2020-06-021-4/+0Star
| | | | | | | | Merge VERLL and VERLLV into op_vesv and op_ves, alongside all of the other vector shift operations. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/s390x: Implement LOAD/STORE TO REAL ADDRESS inlineRichard Henderson2019-12-181-4/+0Star
| | | | | | | | | | | | These are trivially done by performing a memory operation with the correct mmu_idx. The only tricky part is using get_address directly in order to get the address wrapped; we cannot use la2 because of the format. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191211203614.15611-3-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Split out helper_per_store_realRichard Henderson2019-12-181-0/+1
| | | | | | | | | | | Split the PER handling for store-to-real-address into its own helper function, conditionally called when PER is enabled, just as we do for per_branch and per_ifetch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191211203614.15611-2-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: MVST: Fix storing back the addresses to registersDavid Hildenbrand2019-09-231-1/+1
| | | | | | | | | | 24 and 31-bit address space handling is wrong when it comes to storing back the addresses to the register. While at it, read gprs 0 implicitly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand2019-06-071-0/+2
| | | | | | | We can reuse float64_dcmask(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP SUBTRACTDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Similar to VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP SQUARE ROOTDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | Simulate XxC=0 and ERM=0 (current mode), so we can use the existing helper function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand2019-06-071-0/+4
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP MULTIPLYDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Very similar to VECTOR FP DIVIDE. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR LOAD ROUNDEDDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | We can reuse some of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR LOAD LENGTHENEDDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Take care of reading/indicating the 32-bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR LOAD FP INTEGERDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | We can reuse most of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP DIVIDEDavid Hildenbrand2019-06-071-0/+2
| | | | | | | We can reuse most of the infrastructure added for VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | | | | | | | 1. We'll reuse op_vcdg() for similar instructions later, prepare for that. 2. We'll reuse vop64_2() later for other instructions. We have to mangle the erm (effective rounding mode) and the m4 into the simd_data(), and properly unmangle them again. Make sure to restore the erm before triggering an exception. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)David Hildenbrand2019-06-071-0/+12
| | | | | | | | Provide for all three instructions all four combinations of cc bit and s bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand2019-06-071-0/+2
| | | | | | | As far as I can see, there is only a tiny difference. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP ADDDavid Hildenbrand2019-06-071-0/+4
| | | | | | | | | | | | | | | | | | 1. We'll reuse op_vfa() for similar instructions later, prepare for that. 2. We'll reuse vop64_3() for other instructions later. 3. Take care of modifying the vector register only if no trap happened. - on traps, flags are not updated and no elements are modified - traps don't modify the fpc flags - without traps, all exceptions of all elements are merged 4. We'll reuse check_ieee_exc() later when we need the XxC flag. We have to check for exceptions after processing each element. Provide separate handlers for single/all element processing. We'll do the same for all applicable FP instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR STRING RANGE COMPAREDavid Hildenbrand2019-06-071-0/+12
| | | | | | | | | | | | Unfortunately, there is no easy way to avoid looping over all elements in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and all element types. Especially for different values of rt, the compiler might be able to optimize the code a lot. Add s390_vec_write_element(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR ISOLATE STRINGDavid Hildenbrand2019-06-071-0/+6
| | | | | | | Logic mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUALDavid Hildenbrand2019-06-071-0/+6
| | | | | | | | | Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H. Add s390_vec_read_element() that can deal with element sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FIND ELEMENT EQUALDavid Hildenbrand2019-06-071-0/+6
| | | | | | | Core logic courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>