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* target/s390x: Store r1/r2 for page-translation exceptions during MVPGDavid Hildenbrand2021-03-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The PoP states: When EDAT-1 does not apply, and a program interruption due to a page-translation exception is recognized by the MOVE PAGE instruction, the contents of the R1 field of the instruction are stored in bit positions 0-3 of location 162, and the contents of the R2 field are stored in bit positions 4-7. If [...] an ASCE-type, region-first-translation, region-second-translation, region-third-translation, or segment-translation exception was recognized, the contents of location 162 are unpredictable. So we have to write r1/r2 into the lowcore on page-translation exceptions. Simply handle all exceptions inside our mvpg helper now. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210315085449.34676-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MONITOR CALLDavid Hildenbrand2020-10-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Recent upstream Linux uses the MONITOR CALL instruction for things like BUG_ON() and WARN_ON(). We currently inject an operation exception when we hit a MONITOR CALL instruction - which is wrong, as the instruction is not glued to specific CPU features. Doing a simple WARN_ON_ONCE() currently results in a panic: [ 18.162801] illegal operation: 0001 ilc:2 [#1] SMP [ 18.162889] Modules linked in: [...] [ 18.165476] Kernel panic - not syncing: Fatal exception: panic_on_oops With a proper implementation, we now get: [ 18.242754] ------------[ cut here ]------------ [ 18.242855] WARNING: CPU: 7 PID: 1 at init/main.c:1534 [...] [ 18.242919] Modules linked in: [...] [ 18.246262] ---[ end trace a420477d71dc97b4 ]--- [ 18.259014] Freeing unused kernel memory: 4220K Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200918085122.26132-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Use tcg_gen_gvec_rotl{i,s,v}Richard Henderson2020-06-021-4/+0Star
| | | | | | | | Merge VERLL and VERLLV into op_vesv and op_ves, alongside all of the other vector shift operations. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/s390x: Implement LOAD/STORE TO REAL ADDRESS inlineRichard Henderson2019-12-181-4/+0Star
| | | | | | | | | | | | These are trivially done by performing a memory operation with the correct mmu_idx. The only tricky part is using get_address directly in order to get the address wrapped; we cannot use la2 because of the format. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191211203614.15611-3-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Split out helper_per_store_realRichard Henderson2019-12-181-0/+1
| | | | | | | | | | | Split the PER handling for store-to-real-address into its own helper function, conditionally called when PER is enabled, just as we do for per_branch and per_ifetch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191211203614.15611-2-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: MVST: Fix storing back the addresses to registersDavid Hildenbrand2019-09-231-1/+1
| | | | | | | | | | 24 and 31-bit address space handling is wrong when it comes to storing back the addresses to the register. While at it, read gprs 0 implicitly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand2019-06-071-0/+2
| | | | | | | We can reuse float64_dcmask(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP SUBTRACTDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Similar to VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP SQUARE ROOTDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | Simulate XxC=0 and ERM=0 (current mode), so we can use the existing helper function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand2019-06-071-0/+4
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP MULTIPLYDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Very similar to VECTOR FP DIVIDE. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR LOAD ROUNDEDDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | We can reuse some of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR LOAD LENGTHENEDDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Take care of reading/indicating the 32-bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR LOAD FP INTEGERDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | We can reuse most of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP DIVIDEDavid Hildenbrand2019-06-071-0/+2
| | | | | | | We can reuse most of the infrastructure added for VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | | | | | | | 1. We'll reuse op_vcdg() for similar instructions later, prepare for that. 2. We'll reuse vop64_2() later for other instructions. We have to mangle the erm (effective rounding mode) and the m4 into the simd_data(), and properly unmangle them again. Make sure to restore the erm before triggering an exception. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)David Hildenbrand2019-06-071-0/+12
| | | | | | | | Provide for all three instructions all four combinations of cc bit and s bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand2019-06-071-0/+2
| | | | | | | As far as I can see, there is only a tiny difference. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP ADDDavid Hildenbrand2019-06-071-0/+4
| | | | | | | | | | | | | | | | | | 1. We'll reuse op_vfa() for similar instructions later, prepare for that. 2. We'll reuse vop64_3() for other instructions later. 3. Take care of modifying the vector register only if no trap happened. - on traps, flags are not updated and no elements are modified - traps don't modify the fpc flags - without traps, all exceptions of all elements are merged 4. We'll reuse check_ieee_exc() later when we need the XxC flag. We have to check for exceptions after processing each element. Provide separate handlers for single/all element processing. We'll do the same for all applicable FP instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR STRING RANGE COMPAREDavid Hildenbrand2019-06-071-0/+12
| | | | | | | | | | | | Unfortunately, there is no easy way to avoid looping over all elements in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and all element types. Especially for different values of rt, the compiler might be able to optimize the code a lot. Add s390_vec_write_element(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR ISOLATE STRINGDavid Hildenbrand2019-06-071-0/+6
| | | | | | | Logic mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUALDavid Hildenbrand2019-06-071-0/+6
| | | | | | | | | Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H. Add s390_vec_read_element() that can deal with element sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FIND ELEMENT EQUALDavid Hildenbrand2019-06-071-0/+6
| | | | | | | Core logic courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUALDavid Hildenbrand2019-06-071-0/+8
| | | | | | | | | | Complicated stuff. Provide two different helpers for CC an !CC handling. We might want to add more helpers later. zero_search() and match_index() are courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR TEST UNDER MASKDavid Hildenbrand2019-05-171-0/+1
| | | | | | | | | | | | | Let's return the cc value directly via cpu_env. Unfortunately there isn't a simple way to calculate the value lazily - one would have to calculate and store e.g. the population count of the mask and the result so it can be evaluated in a cc helper. But as VTM only sets the cc, we can assume the value will be needed soon either way. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATIONDavid Hildenbrand2019-05-171-0/+2
| | | | | | | | Let's keep it simple for now and handle 8/16 bit elements via helpers. Especially for 8/16, we could come up with some bit tricks. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *David Hildenbrand2019-05-171-0/+1
| | | | | | | Similar to VECTOR SHIFT RIGHT ARITHMETICAL. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETICDavid Hildenbrand2019-05-171-0/+1
| | | | | | | | Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to s390_vec_shr(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE)David Hildenbrand2019-05-171-0/+1
| | | | | | | We can reuse the existing 128-bit shift utility function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASKDavid Hildenbrand2019-05-171-0/+2
| | | | | | | Use the new vector expansion for GVecGen3i. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICALDavid Hildenbrand2019-05-171-0/+4
| | | | | | | | | Take care of properly taking the modulo of the count. We might later want to come back and create a variant of VERLL where the base register is 0, resulting in an immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR POPULATION COUNTDavid Hildenbrand2019-05-171-0/+2
| | | | | | | Similar to VECTOR COUNT TRAILING ZEROES. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR MULTIPLY *David Hildenbrand2019-05-171-0/+16
| | | | | | | | Yet another set of variants. Implement it similar to VECTOR MULTIPLY AND ADD *. At least for one variant we have a gvec helper we can reuse. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR MULTIPLY AND ADD *David Hildenbrand2019-05-171-0/+18
| | | | | | | | | | Quite some variants to handle. At least handle some 32-bit element variants via gvec expansion (we could also handle 16/32-bit variants for ODD and EVEN easily via gvec expansion, but let's keep it simple for now). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE)David Hildenbrand2019-05-171-0/+8
| | | | | | | | | | | | A galois field multiplication in field 2 is like binary multiplication, however instead of doing ordinary binary additions, xor's are performed. So no carries are considered. Implement all variants via helpers. s390_vec_sar() and s390_vec_shr() will be reused later on. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR COUNT TRAILING ZEROSDavid Hildenbrand2019-05-171-0/+2
| | | | | | | Implement it similar to VECTOR COUNT LEADING ZEROS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR COUNT LEADING ZEROSDavid Hildenbrand2019-05-171-0/+2
| | | | | | | | For 8/16, use the 32 bit variant and properly subtract the added leading zero bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR AVERAGE LOGICALDavid Hildenbrand2019-05-171-0/+2
| | | | | | | Similar to VECTOR AVERAGE but without sign extension. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR AVERAGEDavid Hildenbrand2019-05-171-0/+4
| | | | | | | | Handle 32/64-bit elements via gvec expansion and the 8/16 bits via ool helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR STORE WITH LENGTHDavid Hildenbrand2019-03-111-0/+1
| | | | | | | | | | Very similar to VECTOR LOAD WITH LENGTH, just the opposite direction. Properly probe write access before modifying memory. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-32-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Provide probe_write_access helperDavid Hildenbrand2019-03-111-0/+1
| | | | | | | | | | | | | | | | | Instead of checking e.g. the first access on every touched page, we should check the actual access, otherwise we might get false positives when Low Address Protection (LAP) is active. As probe_write() can only deal with accesses to one page, we have to loop. Use i64 for the length, although not needed - easier to reuse TCG temps we already have in the translation functions where this will be used. Also allow it to be used from other helpers. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-28-david@redhat.com> [CH: add missing page_check_range()] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement VECTOR PERMUTEDavid Hildenbrand2019-03-111-0/+1
| | | | | | | | | Take care of overlying inputs and outputs by using a temporary vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-21-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement VECTOR PACK *David Hildenbrand2019-03-111-0/+15
| | | | | | | | | | | | | | This is a big one. Luckily we only have a limited set of such nasty instructions. We'll implement all variants with helpers, except when sources and the destination don't overlap for VECTOR PACK. Provide different helpers when the cc is to be modified. We'll return the cc then via env->cc_op. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-20-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARYDavid Hildenbrand2019-03-111-0/+3
| | | | | | | | | | | | | | | | | | | | Very similar to LOAD COUNT TO BLOCK BOUNDARY, but instead of only calculating, the actual vector is loaded. Use a temporary vector to not modify the real vector on exceptions. Initialize that one to zero, to not leak any data. Provide a fast path if we're loading a full vector. As we don't have gvec ool handlers for single vectors, just calculate the vector address manually. We can reuse the helper later on for VECTOR LOAD WITH LENGTH. In fact, we are going to name it "vll" right from the beginning, because that's a better match. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDEDDavid Hildenbrand2019-03-041-3/+3
| | | | | | | | | | | | With the floating-point extension facility, LOAD ROUNDED has a rounding mode specification and the inexact-exception control (XxC). Handle them just like e.g. LOAD FP INTEGER. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Check for exceptions in SET BFP ROUNDING MODEDavid Hildenbrand2019-03-041-0/+1
| | | | | | | | | | | Let's split handling of BFP/DFP rounding mode configuration. Also, let's not reuse the sfpc handler, use a separate handler so we can properly check for specification exceptions for SRNMB. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Handle SET FPC AND LOAD FPC 3-bit BFP rounding modesDavid Hildenbrand2019-03-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already forward the 3 bits correctly in the translation functions. We also have to handle them properly and check for specification exceptions. Setting an invalid rounding mode (BFP only, all DFP rounding modes) results in a specification exception. Setting unassigned bits in the fpc, results in a specification exception. This fixes LOAD FPC (AND SIGNAL), SET FPC (AND SIGNAL). Also for, SET BFP ROUNDING MODE, 3-bit rounding mode is now explicitly checked. Note: TCG_CALL_NO_WG is required for sfpc handler, as we now inject exceptions. We won't be modeling abscence of the "floating-point extension facility" for now, not necessary as most take the facility for granted without checking. z14 PoP, 9-23, "LOAD FPC" When the floating-point extension facility is installed, bits 29-31 of the second operand must specify a valid BFP rounding mode and bits 6-7, 14-15, 24, and 28 must be zero; otherwise, a specification exception is recognized. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-9-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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