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* s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)David Hildenbrand2020-10-021-0/+1
| | | | | | | | | | As with the other crypto functions, we only implement subcode 0 (query) and no actual encryption/decryption. We now implement S390_FEAT_MSA_EXT_8. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)David Hildenbrand2020-10-021-0/+4
| | | | | | | | | | | | | We need new CC handling, determining the CC based on the intermediate result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC). We want to store out2 ("low") after muls128 to r1, so add "wout_out2_r1". Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)David Hildenbrand2020-10-021-0/+2
| | | | | | | | | | | | Just like BRANCH ON CONDITION - however the address is read from memory (always 8 bytes are read), we have to wrap the address manually. The address is read using current CPU DAT/address-space controls, just like ordinary data. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MULTIPLY HALFWORD (MGH)David Hildenbrand2020-10-021-0/+1
| | | | | | | | | | Just like MULTIPLY HALFWORD IMMEDIATE (MGHI), only the second operand (signed 16 bit) comes from memory. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MULTIPLY (MG, MGRK)David Hildenbrand2020-10-021-0/+2
| | | | | | | | | | Multiply two signed 64bit values and store the 128bit result in r1 (0-63) and r1 + 1 (64-127). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement SUBTRACT HALFWORD (SGH)David Hildenbrand2020-10-021-0/+1
| | | | | | | | | | Easy to wire up. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement ADD HALFWORD (AGH)David Hildenbrand2020-10-021-0/+1
| | | | | | | | | | Easy, just like ADD HALFWORD IMMEDIATE (AGHI). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MONITOR CALLDavid Hildenbrand2020-10-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Recent upstream Linux uses the MONITOR CALL instruction for things like BUG_ON() and WARN_ON(). We currently inject an operation exception when we hit a MONITOR CALL instruction - which is wrong, as the instruction is not glued to specific CPU features. Doing a simple WARN_ON_ONCE() currently results in a panic: [ 18.162801] illegal operation: 0001 ilc:2 [#1] SMP [ 18.162889] Modules linked in: [...] [ 18.165476] Kernel panic - not syncing: Fatal exception: panic_on_oops With a proper implementation, we now get: [ 18.242754] ------------[ cut here ]------------ [ 18.242855] WARNING: CPU: 7 PID: 1 at init/main.c:1534 [...] [ 18.242919] Modules linked in: [...] [ 18.246262] ---[ end trace a420477d71dc97b4 ]--- [ 18.259014] Freeing unused kernel memory: 4220K Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200918085122.26132-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Fix SQXBRRichard Henderson2020-07-031-1/+1
| | | | | | | | | | The output is 128-bit, and thus requires a pair of 64-bit temps. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Buglink: https://bugs.launchpad.net/bugs/1883984 Message-Id: <20200620042140.42070-1-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Use tcg_gen_gvec_rotl{i,s,v}Richard Henderson2020-06-021-2/+2
| | | | | | | | Merge VERLL and VERLLV into op_vesv and op_ves, alongside all of the other vector shift operations. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/s390x: Implement LOAD/STORE TO REAL ADDRESS inlineRichard Henderson2019-12-181-4/+4
| | | | | | | | | | | | These are trivially done by performing a memory operation with the correct mmu_idx. The only tricky part is using get_address directly in order to get the address wrapped; we cannot use la2 because of the format. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191211203614.15611-3-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: MVST: Fix storing back the addresses to registersDavid Hildenbrand2019-09-231-1/+1
| | | | | | | | | | 24 and 31-bit address space handling is wrong when it comes to storing back the addresses to the register. While at it, read gprs 0 implicitly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand2019-06-071-0/+2
| | | | | | | We can reuse float64_dcmask(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP SUBTRACTDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Similar to VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP SQUARE ROOTDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | Simulate XxC=0 and ERM=0 (current mode), so we can use the existing helper function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand2019-06-071-0/+2
| | | | | | | The only FP instruction we can implement without an helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand2019-06-071-0/+4
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP MULTIPLYDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Very similar to VECTOR FP DIVIDE. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR LOAD ROUNDEDDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | We can reuse some of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR LOAD LENGTHENEDDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Take care of reading/indicating the 32-bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR LOAD FP INTEGERDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | We can reuse most of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP DIVIDEDavid Hildenbrand2019-06-071-0/+2
| | | | | | | We can reuse most of the infrastructure added for VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BITDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | | | | | | | 1. We'll reuse op_vcdg() for similar instructions later, prepare for that. 2. We'll reuse vop64_2() later for other instructions. We have to mangle the erm (effective rounding mode) and the m4 into the simd_data(), and properly unmangle them again. Make sure to restore the erm before triggering an exception. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)David Hildenbrand2019-06-071-0/+6
| | | | | | | | Provide for all three instructions all four combinations of cc bit and s bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand2019-06-071-0/+4
| | | | | | | As far as I can see, there is only a tiny difference. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FP ADDDavid Hildenbrand2019-06-071-0/+5
| | | | | | | | | | | | | | | | | | 1. We'll reuse op_vfa() for similar instructions later, prepare for that. 2. We'll reuse vop64_3() for other instructions later. 3. Take care of modifying the vector register only if no trap happened. - on traps, flags are not updated and no elements are modified - traps don't modify the fpc flags - without traps, all exceptions of all elements are merged 4. We'll reuse check_ieee_exc() later when we need the XxC flag. We have to check for exceptions after processing each element. Provide separate handlers for single/all element processing. We'll do the same for all applicable FP instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR STRING RANGE COMPAREDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | | | | | Unfortunately, there is no easy way to avoid looping over all elements in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and all element types. Especially for different values of rt, the compiler might be able to optimize the code a lot. Add s390_vec_write_element(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR ISOLATE STRINGDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Logic mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUALDavid Hildenbrand2019-06-071-0/+2
| | | | | | | | | Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H. Add s390_vec_read_element() that can deal with element sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FIND ELEMENT EQUALDavid Hildenbrand2019-06-071-0/+2
| | | | | | | Core logic courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUALDavid Hildenbrand2019-06-071-0/+5
| | | | | | | | | | Complicated stuff. Provide two different helpers for CC an !CC handling. We might want to add more helpers later. zero_search() and match_index() are courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR TEST UNDER MASKDavid Hildenbrand2019-05-171-0/+2
| | | | | | | | | | | | | Let's return the cc value directly via cpu_env. Unfortunately there isn't a simple way to calculate the value lazily - one would have to calculate and store e.g. the population count of the mask and the result so it can be evaluated in a cc helper. But as VTM only sets the cc, we can assume the value will be needed soon either way. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SUM ACROSS WORDDavid Hildenbrand2019-05-171-0/+2
| | | | | | | Similar to VECTOR SUM ACROSS DOUBLEWORD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SUM ACROSS QUADWORDDavid Hildenbrand2019-05-171-0/+2
| | | | | | | | Similar to VECTOR SUM ACROSS DOUBLEWORD, however without a loop and using 128-bit calculations. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORDDavid Hildenbrand2019-05-171-0/+2
| | | | | | | | Perform the calculations without a helper. Only 16 bit or 32 bit values have to be added. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATIONDavid Hildenbrand2019-05-171-0/+2
| | | | | | | Mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATIONDavid Hildenbrand2019-05-171-0/+2
| | | | | | | | Fairly easy as only 128-bit handling is required. Simply perform the subtraction and then subtract the borrow. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATIONDavid Hildenbrand2019-05-171-0/+2
| | | | | | | | Let's keep it simple for now and handle 8/16 bit elements via helpers. Especially for 8/16, we could come up with some bit tricks. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SUBTRACTDavid Hildenbrand2019-05-171-0/+2
| | | | | | | | We can use tcg_gen_sub2_i64() to do 128-bit subtraction and otherwise existing gvec helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *David Hildenbrand2019-05-171-0/+4
| | | | | | | Similar to VECTOR SHIFT RIGHT ARITHMETICAL. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETICDavid Hildenbrand2019-05-171-0/+4
| | | | | | | | Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to s390_vec_shr(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTEDavid Hildenbrand2019-05-171-0/+2
| | | | | | | Inline expansion courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE)David Hildenbrand2019-05-171-0/+4
| | | | | | | We can reuse the existing 128-bit shift utility function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR ELEMENT SHIFTDavid Hildenbrand2019-05-171-0/+9
| | | | | | | | | | We can use all the fancy new vector helpers implemented by Richard. One important thing to take care of is always to properly mask of unused bits from the shift count. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASKDavid Hildenbrand2019-05-171-0/+2
| | | | | | | Use the new vector expansion for GVecGen3i. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICALDavid Hildenbrand2019-05-171-0/+3
| | | | | | | | | Take care of properly taking the modulo of the count. We might later want to come back and create a variant of VERLL where the base register is 0, resulting in an immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR POPULATION COUNTDavid Hildenbrand2019-05-171-0/+2
| | | | | | | Similar to VECTOR COUNT TRAILING ZEROES. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
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