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* s390x/tcg: Implement CIPHER MESSAGE WITH AUTHENTICATION (KMA)David Hildenbrand2020-10-021-0/+7
| | | | | | | | | | As with the other crypto functions, we only implement subcode 0 (query) and no actual encryption/decryption. We now implement S390_FEAT_MSA_EXT_8. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MULTIPLY SINGLE (MSC, MSGC, MSGRKC, MSRKC)David Hildenbrand2020-10-021-0/+19
| | | | | | | | | | | | | We need new CC handling, determining the CC based on the intermediate result (64bit for MSC and MSRKC, 128bit for MSGC and MSGRKC). We want to store out2 ("low") after muls128 to r1, so add "wout_out2_r1". Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)David Hildenbrand2020-10-021-0/+8
| | | | | | | | | | | | Just like BRANCH ON CONDITION - however the address is read from memory (always 8 bytes are read), we have to wrap the address manually. The address is read using current CPU DAT/address-space controls, just like ordinary data. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MULTIPLY (MG, MGRK)David Hildenbrand2020-10-021-0/+13
| | | | | | | | | | Multiply two signed 64bit values and store the 128bit result in r1 (0-63) and r1 + 1 (64-127). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement ADD HALFWORD (AGH)David Hildenbrand2020-10-021-0/+1
| | | | | | | | | | Easy, just like ADD HALFWORD IMMEDIATE (AGHI). Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200928122717.30586-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement MONITOR CALLDavid Hildenbrand2020-10-021-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Recent upstream Linux uses the MONITOR CALL instruction for things like BUG_ON() and WARN_ON(). We currently inject an operation exception when we hit a MONITOR CALL instruction - which is wrong, as the instruction is not glued to specific CPU features. Doing a simple WARN_ON_ONCE() currently results in a panic: [ 18.162801] illegal operation: 0001 ilc:2 [#1] SMP [ 18.162889] Modules linked in: [...] [ 18.165476] Kernel panic - not syncing: Fatal exception: panic_on_oops With a proper implementation, we now get: [ 18.242754] ------------[ cut here ]------------ [ 18.242855] WARNING: CPU: 7 PID: 1 at init/main.c:1534 [...] [ 18.242919] Modules linked in: [...] [ 18.246262] ---[ end trace a420477d71dc97b4 ]--- [ 18.259014] Freeing unused kernel memory: 4220K Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200918085122.26132-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/s390x/translate: Fix RNSBG instructionThomas Huth2020-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | RNSBG is handled via the op_rosbg() helper function. But RNSBG has the opcode 0xEC54, i.e. 0x54 as second byte, while op_rosbg() currently checks for 0x55. This seems to be a typo, fix it to use 0x54 instead, so that op_rosbg() does not abort() anymore if a program uses RNSBG. I've checked with a simple test function that I now get the same results with KVM and with TCG: static void test_rnsbg(void) { uint64_t r1, r2; r2 = 0xffff000000000000UL; r1 = 0x123456789bdfaaaaUL; asm volatile (" rnsbg %0,%1,12,61,16 " : "+r"(r1) : "r"(r2)); printf("r1 afterwards: 0x%lx\n", r1); } Buglink: https://bugs.launchpad.net/qemu/+bug/1860920 Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200130133417.10531-1-thuth@redhat.com> Fixes: d6c6372e186e ("target-s390: Implement R[NOX]SBG") Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Remove DisasFields argument from extract_insnRichard Henderson2020-01-271-11/+8Star
| | | | | | | | | The separate pointer is now redundant. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200123232248.1800-6-richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Move DisasFields into DisasContextRichard Henderson2020-01-271-12/+10Star
| | | | | | | | | | | | | | | | | | I believe that the separate allocation of DisasFields from DisasContext was meant to limit the places from which we could access fields. But that plan did not go unchanged, and since DisasContext contains a pointer to fields, the substructure is accessible everywhere. By allocating the substructure with DisasContext, we improve the locality of the accesses by avoiding one level of pointer chasing. In addition, we avoid a dangling pointer to stack allocated memory, diagnosed by static checkers. Launchpad: https://bugs.launchpad.net/bugs/1661815 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200123232248.1800-5-richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Pass DisasContext to get_field and have_fieldRichard Henderson2020-01-271-269/+265Star
| | | | | | | | | All callers pass s->fields, so we might as well pass s directly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200123232248.1800-4-richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Remove DisasFields argument from callbacksRichard Henderson2020-01-271-207/+210
| | | | | | | | | | The DisasFields data is available from DisasContext. We do not need to pass a separate argument. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200123232248.1800-3-richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Move struct DisasFields definition earlierRichard Henderson2020-01-271-81/+83
| | | | | | | | | We will want to include the struct in DisasContext. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200123232248.1800-2-richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently search both the root and the tcg/ directories for tcg files: $ git grep '#include "tcg/' | wc -l 28 $ git grep '#include "tcg[^/]' | wc -l 94 To simplify the preprocessor search path, unify by expliciting the tcg/ directory. Patch created mechanically by running: $ for x in \ tcg.h tcg-mo.h tcg-op.h tcg-opc.h \ tcg-op-gvec.h tcg-gvec-desc.h; do \ sed -i "s,#include \"$x\",#include \"tcg/$x\"," \ $(git grep -l "#include \"$x\""); \ done Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc parts) Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200101112303.20724-2-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/s390x: Implement LOAD/STORE TO REAL ADDRESS inlineRichard Henderson2019-12-181-17/+4Star
| | | | | | | | | | | | These are trivially done by performing a memory operation with the correct mmu_idx. The only tricky part is using get_address directly in order to get the address wrapped; we cannot use la2 because of the format. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191211203614.15611-3-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Split out helper_per_store_realRichard Henderson2019-12-181-0/+8
| | | | | | | | | | | Split the PER handling for store-to-real-address into its own helper function, conditionally called when PER is enabled, just as we do for per_branch and per_ifetch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191211203614.15611-2-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Add ilen to unwind dataRichard Henderson2019-10-091-3/+17
| | | | | | | | | | Use ILEN_UNWIND to signal that we have in fact that cpu_restore_state will have been called by the time we arrive in do_program_interrupt. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20191001171614.8405-2-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Always use MMU_USER_IDX for CONFIG_USER_ONLYDavid Hildenbrand2019-09-231-0/+4
| | | | | | | | | Although we basically ignore the index all the time for CONFIG_USER_ONLY, let's simply skip all the checks and always return MMU_USER_IDX in cpu_mmu_index() and get_mem_index(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: MVST: Fix storing back the addresses to registersDavid Hildenbrand2019-09-231-2/+6
| | | | | | | | | | 24 and 31-bit address space handling is wrong when it comes to storing back the addresses to the register. While at it, read gprs 0 implicitly. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-3/+3
| | | | | | | | | | | | | | Preparation for collapsing the two byte swaps, adjust_endianness and handle_bswap, along the I/O path. Target dependant attributes are conditionalized upon NEED_CPU_H. Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <81d9cd7d7f5aaadfa772d6c48ecee834e9cf7882.1566466906.git.tony.nguyen@bt.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* s390x: Use uint64_t for vector registersDavid Hildenbrand2019-06-071-1/+1
| | | | | | | | | CPU_DoubleU is primarily used to reinterpret between integer and floats. We don't really need this functionality. So let's just keep it simple and use an uint64_t. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR NANDDavid Hildenbrand2019-05-171-0/+1
| | | | | | | Part of vector enhancements facility 1, but easy to implement. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* s390x/tcg: Implement VECTOR COMPARE *David Hildenbrand2019-05-171-0/+1
| | | | | | | | | | To carry out the comparison, we can reuse the existing gvec comparison function. In case the CC is to be computed, save the result vector and compute the CC lazily. The result is a vector consisting of all 1's for elements that matched and 0's for elements that didn't match. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
* target/s390x: Use tcg_gen_abs_i64Richard Henderson2019-05-141-7/+1Star
| | | | | Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
| | | | | | | | | | In order to handle TB's that translate to too much code, we need to place the control of the length of the translation in the hands of the code gen master loop. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* s390x/tcg: Implement VECTOR LOAD WITH LENGTHDavid Hildenbrand2019-03-111-0/+7
| | | | | | | | | | | We can reuse the helper introduced along with VECTOR LOAD TO BLOCK BOUNDARY. We just have to take care of converting the highest index into a length. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement VECTOR GENERATE BYTE MASKDavid Hildenbrand2019-03-111-0/+1
| | | | | | | | | | Let's optimize it for the common cases (setting a vector to zero or all ones) - courtesy of Richard. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement VECTOR GATHER ELEMENTDavid Hildenbrand2019-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | Let's start with a more involved one, but it is the first in the list of vector support instructions (introduced with the vector facility). Good thing is, we need a lot of basic infrastructure for this. Reading and writing vector elements as well as checking element validity. All vector instruction related translation functions will reside in translate_vx.inc.c, to be included in translate.c - similar to how other architectures handle it. While at it, directly add some documentation (which contains parts about things added in follow-up patches, but splitting this up does not make too much sense). Also add ES_* defines heavily used later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Check vector register instructions at central pointDavid Hildenbrand2019-03-111-0/+12
| | | | | | | | | | | | Check them at a central point. We'll use a new instruction flag to flag all vector instructions (IF_VEC) and handle it very similar to AFP, whereby we use another unused position in the PSW mask to store the state of vector register enablement per translation block. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Define vector instruction formatsDavid Hildenbrand2019-03-111-1/+38
| | | | | | | | | | | | | | | | | | | | These are the new instruction formats related to vector instructions as up to the z14 (a.k.a. latest PoP). As v2 appeares (like x2 in VRX) with d2/b2 in VRV, we have to assign it a higher field number to avoid collisions. Properly take care of the MSB (to be able to address 32 registers) for each vector register field stored in the RXB field (Bit 36 - 30 for all vector instructions). As we have 32 bit vector registers and the "v" fields are only 4 bit in size, the 5th bit is stored in the RXB. We use a new type to indicate that the MSB has to be fetched from the RXB. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDEDDavid Hildenbrand2019-03-041-3/+21
| | | | | | | | | | | | With the floating-point extension facility, LOAD ROUNDED has a rounding mode specification and the inexact-exception control (XxC). Handle them just like e.g. LOAD FP INTEGER. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement XxC and checks for most FP instructionsDavid Hildenbrand2019-03-041-63/+172
| | | | | | | | | | | | | | | | | | | | | | With the floating-point extension facility - CONVERT FROM LOGICAL - CONVERT TO LOGICAL - CONVERT TO FIXED - CONVERT FROM FIXED - LOAD FP INTEGER have both, a rounding mode specification and the inexact-exception control (XxC). Other instructions will be handled separatly. Check for valid rounding modes and forward also the XxC (via m4). To avoid a lot of boilerplate code and changes to the helpers, combine both, the m3 and m4 field in a combined 32 bit TCG variable. Perform checks at a central place, taking in account if the m3 or m4 field was ignore before the floating-point extension facility was introduced. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-13-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Check for exceptions in SET BFP ROUNDING MODEDavid Hildenbrand2019-03-041-32/+24Star
| | | | | | | | | | | Let's split handling of BFP/DFP rounding mode configuration. Also, let's not reuse the sfpc handler, use a separate handler so we can properly check for specification exceptions for SRNMB. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARYDavid Hildenbrand2019-03-041-0/+19
| | | | | | | | | | | | | | | Use a new CC helper to calculate the CC lazily if needed. While the PoP mentions that "A 32-bit unsigned binary integer" is placed into the first operand, there is no word telling that the other 32 bits (high part) are left untouched. Maybe the other 32-bit are unpredictable. So store 64 bit for now. Bit magic courtesy of Richard. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-8-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFPDavid Hildenbrand2019-03-041-0/+6
| | | | | | | | | | | Nice trick to load a 32 bit value into vector element 0 (32 bit element size) from memory, zeroing out element1. The short HFP to long HFP conversion really only is a shift. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address()David Hildenbrand2019-03-041-15/+26
| | | | | | | | | | Also properly wrap in 24bit mode. While at it, convert the comment (and drop the comment about fundamental TCG optimizations). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Factor out vec_full_reg_offset()David Hildenbrand2019-03-041-2/+7
| | | | | | | | | | | We'll use that a lot along with gvec helpers, to calculate the start address of a vector. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Clarify terminology in vec_reg_offset()David Hildenbrand2019-03-041-5/+6
| | | | | | | | | | | We will use s390x speak "Element Size" (es) for MO_8 == 0, MO_16 == 1 ... Simple rename of variables. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Simplify disassembler operands initializationDavid Hildenbrand2019-03-041-7/+1Star
| | | | | | | | | | Let's simplify initialization to 0. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Implement STCK et al for CONFIG_USER_ONLYRichard Henderson2019-02-181-0/+2
| | | | | | | | | | | | This is a non-privileged instruction that was only implemented for system mode. However, the stck instruction is used by glibc, so this was causing SIGILL for programs run under debian stretch. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190212053044.29015-3-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: Don't model FP registers as globalsDavid Hildenbrand2019-02-041-50/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: Fix LGPL version in the file header commentsThomas Huth2019-01-301-1/+1
| | | | | | | | | | | | It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <1548769067-20792-1-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translateRichard Henderson2018-10-191-7/+18
| | | | | Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/s390x: Skip wout, cout helpers if op helper does not returnRichard Henderson2018-10-191-5/+15
| | | | | | | | When op raises an exception, it may not have initialized the output temps that would be written back by wout or cout. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* s390x/tcg: refactor specification checkingDavid Hildenbrand2018-10-041-28/+6Star
| | | | | | | | | | We can fit this nicely into less LOC, without harming readability. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: fix FP register pair checksDavid Hildenbrand2018-10-041-10/+10
| | | | | | | | | | | | | Valid register pairs are 0/2, 1/3, 4/6, 5/7, 8/10, 9/11, 12/14, 13/15. R1/R2 always selects the lower number, so the current checks are not correct as e.g. 2/4 could be selected as a pair. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: handle privileged instructions via flagsDavid Hildenbrand2018-10-041-76/+7Star
| | | | | | | | | | Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: check for AFP-register, BFP and DFP data exceptionsDavid Hildenbrand2018-10-041-0/+33
| | | | | | | | | | | | | | | | | | With the annotated functions, we can now easily check this at a central place. DXC 1 is to be injected if an AFP register is used (for a HFP AND FPS instruction) when AFP is disabled. DXC 2 is to be injected if a BFP instruction is used when AFP is disabled. DXC 3 is to be injected if a DFP instruction is used when AFP is disabled. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: add instruction flags for floating point instructionsDavid Hildenbrand2018-10-041-0/+8
| | | | | | | | | | | | | | These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: support flags for instructionsDavid Hildenbrand2018-10-041-6/+16
| | | | | | | | | | | | | Storing flags for instructions allows us to efficiently verify certain properties at a central point. Examples might later be handling if AFP is disabled in CR0, we are not in problem state, or if vector instructions are disabled in CR0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>