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* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently search both the root and the tcg/ directories for tcg files: $ git grep '#include "tcg/' | wc -l 28 $ git grep '#include "tcg[^/]' | wc -l 94 To simplify the preprocessor search path, unify by expliciting the tcg/ directory. Patch created mechanically by running: $ for x in \ tcg.h tcg-mo.h tcg-op.h tcg-opc.h \ tcg-op-gvec.h tcg-gvec-desc.h; do \ sed -i "s,#include \"$x\",#include \"tcg/$x\"," \ $(git grep -l "#include \"$x\""); \ done Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc parts) Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200101112303.20724-2-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Switch to do_transaction_failed() hookPeter Maydell2019-09-171-4/+12
| | | | | | | | | | | | | | | | Switch the SPARC target from the old unassigned_access hook to the new do_transaction_failed hook. This will cause the "if transaction failed" code paths added in the previous commits to become active if the access is to an unassigned address. In particular we'll now handle bus errors during page table walks correctly (generating a translation error with the right kind of fault status). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20190801183012.17564-8-peter.maydell@linaro.org
* target/sparc: Check for transaction failures in MXCC stream ASI accessesPeter Maydell2019-09-171-20/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently the ld/st_asi helper functions make calls to the ld*_phys() and st*_phys() functions for those ASIs which imply direct accesses to physical addresses. These implicitly rely on the unassigned_access hook to cause them to generate an MMU fault if the access fails. Switch to using the address_space_* functions instead, which return a MemTxResult that we can check. This means that when we switch SPARC over to using the do_transaction_failed hook we'll still get the same MMU faults we did before. This commit converts the ASIs which do MXCC stream source and destination accesses. It's not clear to me whether raising an MMU fault like this is the correct behaviour if we encounter a bus error, but we retain the same behaviour that the old unassigned_access hook would implement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20190801183012.17564-4-peter.maydell@linaro.org
* target/sparc: Check for transaction failures in MMU passthrough ASIsPeter Maydell2019-09-171-16/+33
| | | | | | | | | | | | | | | | | | | | Currently the ld/st_asi helper functions make calls to the ld*_phys() and st*_phys() functions for those ASIs which imply direct accesses to physical addresses. These implicitly rely on the unassigned_access hook to cause them to generate an MMU fault if the access fails. Switch to using the address_space_* functions instead, which return a MemTxResult that we can check. This means that when we switch SPARC over to using the do_transaction_failed hook we'll still get the same MMU faults we did before. This commit converts the ASIs which do "MMU passthrough". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20190801183012.17564-3-peter.maydell@linaro.org
* target/sparc: Factor out the body of sparc_cpu_unassigned_access()Peter Maydell2019-09-171-95/+106
| | | | | | | | | | | | | | | | | | | | | | | | Currently the SPARC target uses the old-style do_unassigned_access hook. We want to switch it over to do_transaction_failed, but to do this we must first remove all the direct calls in ldst_helper.c to cpu_unassigned_access(). Factor out the body of the hook function's code into a new sparc_raise_mmu_fault() and call it from the hook and from the various places that used to call cpu_unassigned_access(). In passing, this fixes a bug where the code that raised the MMU exception was directly calling GETPC() from a function that was several levels deep in the callstack from the original helper function: the new sparc_raise_mmu_fault() instead takes the return address as an argument. Other than the use of retaddr rather than GETPC() and a comment format fixup, the body of the new function has no changes from that of the old hook function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20190801183012.17564-2-peter.maydell@linaro.org
* target/sparc: Use env_cpu, env_archcpuRichard Henderson2019-06-101-18/+15Star
| | | | | | | | | | | Cleanup in the boilerplate that each target must define. Replace sparc_env_get_cpu with env_archcpu. The combination CPU(sparc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson2019-05-101-6/+0Star
| | | | | | | | | | | | We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also isolates the asserts within. Remove the named tlb_fill function from all of the targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-10/+1Star
| | | | | | | Cc: Artyom Tarasenko <atar4qemu@gmail.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target: Clean up how the dump_mmu() printMarkus Armbruster2019-04-181-9/+9
| | | | | | | | | | | | | | | | | | | | | The various dump_mmu() take an fprintf()-like callback and a FILE * to pass to it, and so do their helper functions. Passing around callback and argument is rather tiresome. Most dump_mmu() are called only by the target's hmp_info_tlb(). These all pass monitor_printf() cast to fprintf_function and the current monitor cast to FILE *. SPARC's dump_mmu() gets also called from target/sparc/ldst_helper.c a few times #ifdef DEBUG_MMU. These calls pass fprintf() and stdout. The type-punning is technically undefined behaviour, but works in practice. Clean up: drop the callback, and call qemu_printf() instead. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-11-armbru@redhat.com>
* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The MC68040 MMU provides the size of the access that triggers the page fault. This size is set in the Special Status Word which is written in the stack frame of the access fault exception. So we need the size in m68k_cpu_unassigned_access() and m68k_cpu_handle_mmu_fault(). To be able to do that, this patch modifies the prototype of handle_mmu_fault handler, tlb_fill() and probe_write(). do_unassigned_access() already includes a size parameter. This patch also updates handle_mmu_fault handlers and tlb_fill() of all targets (only parameter, no code change). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
* sparc: embed sparc_def_t into CPUSPARCStateIgor Mammedov2017-09-011-7/+7
| | | | | | | | | | | | Make CPUSPARCState::def embedded so it would be allocated as part of cpu instance and we won't have to worry about cleaning def pointer up mannualy on cpu destruction. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1503592308-93913-4-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmapAlex Bennée2017-02-241-3/+5
| | | | | | | | | | | | | | | | | | | | | | While the vargs approach was flexible the original MTTCG ended up having munge the bits to a bitmap so the data could be used in deferred work helpers. Instead of hiding that in cputlb we push the change to the API to make it take a bitmap of MMU indexes instead. For ARM some the resulting flushes end up being quite long so to aid readability I've tended to move the index shifting to a new line so all the bits being or-ed together line up nicely, for example: tlb_flush_page_by_mmuidx(other_cs, pageaddr, (1 << ARMMMUIdx_S1SE1) | (1 << ARMMMUIdx_S1SE0)); Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [AT: SPARC parts only] Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [PM: ARM parts only] Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko2017-01-181-8/+44
| | | | | | | | | | According to chapter 13.3 of the UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005, only the sun4u format is available for data-access loads. Store UA2005 entries in the sun4u format to simplify processing. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko2017-01-181-0/+31
| | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko2017-01-181-0/+22
| | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko2017-01-181-36/+15Star
| | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-sparc: implement UA2005 TSB PointersArtyom Tarasenko2017-01-181-22/+102
| | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko2017-01-181-4/+4
| | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko2017-01-181-2/+4
| | | | | | | | | | | Implement the behavior described in the chapter 13.9.11 of UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005: "If a TLB Data-In replacement is attempted with all TLB entries locked and valid, the last TLB entry (entry 63) is replaced." Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko2017-01-181-0/+1
| | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko2017-01-181-14/+18
| | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko2017-01-181-0/+24
| | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko2017-01-181-3/+2Star
| | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-sparc: use explicit mmu register pointersArtyom Tarasenko2017-01-181-12/+54
| | | | | | | | Use explicit register pointers while accessing D/I-MMU registers. Call cpu_unassigned_access on access to missing registers. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-sparc: ignore MMU-faults if MMU is disabled in hypervisor modeArtyom Tarasenko2017-01-181-2/+13
| | | | | | | | while IMMU/DMMU is disabled - ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor - signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* cputlb: drop flush_global flag from tlb_flushAlex Bennée2017-01-131-6/+6
| | | | | | | | | | | We have never has the concept of global TLB entries which would avoid the flush so we never actually use this flag. Drop it and make clear that tlb_flush is the sledge-hammer it has always been. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> [DG: ppc portions] Acked-by: David Gibson <david@gibson.dropbear.id.au>
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+1709
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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