bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
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*	target/xtensa: implement PREFCTL SR	Max Filippov	2019-02-28	1	-0/+1
*	target/xtensa: prioritize load/store in FLIX bundles	Max Filippov	2019-02-28	1	-0/+4
*	target/xtensa: reorganize register handling in translators	Max Filippov	2019-02-28	1	-3/+12
*	target/xtensa: move WINDOW_BASE SR update to postprocessing	Max Filippov	2019-02-28	1	-0/+1
*	target/xtensa: add generic instruction post-processing	Max Filippov	2019-02-28	1	-0/+8
*	target/xtensa: sort FLIX instruction opcodes	Max Filippov	2019-02-28	1	-0/+2
*	target/xtensa: allow multiple names for single opcode	Max Filippov	2019-02-19	1	-1/+3
*	target/xtensa: don't require opcode table sorting	Max Filippov	2019-02-19	1	-2/+0
*	target/xtensa: move xtensa_finalize_config to xtensa_core_class_init	Max Filippov	2019-02-19	1	-1/+0
*	target/xtensa: don't specify windowed registers manually	Max Filippov	2019-02-11	1	-1/+1
*	target/xtensa: expose core runstall as an IRQ line	Max Filippov	2019-01-28	1	-0/+2
*	target/xtensa: rearrange access to external interrupts	Max Filippov	2019-01-28	1	-2/+3
*	target/xtensa: drop function xtensa_timer_irq	Max Filippov	2019-01-28	1	-1/+0
*	target/xtensa: rework zero overhead loops implementation	Max Filippov	2019-01-12	1	-0/+32
*	target/xtensa: extract test for cpdisabled exception	Max Filippov	2018-10-01	1	-0/+1
*	target/xtensa: extract test for window overflow exception	Max Filippov	2018-10-01	1	-0/+9
*	target/xtensa: extract test for an illegal instruction	Max Filippov	2018-10-01	1	-1/+26
*	target/xtensa: convert to do_transaction_failed	Max Filippov	2018-09-17	1	-3/+4
*	target/xtensa: clean up gdbstub register handling	Max Filippov	2018-08-20	1	-0/+2
*	target/xtensa: check zero overhead loop alignment	Max Filippov	2018-06-30	1	-0/+1
*	cpu: get rid of unused cpu_init() defines	Igor Mammedov	2018-03-19	1	-2/+0
*	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov	2018-03-19	1	-0/+1
*	target/xtensa: add linux-user support	Max Filippov	2018-03-16	1	-19/+37
*	target/xtensa: support MTTCG	Max Filippov	2018-03-13	1	-0/+3
*	target/xtensa: use correct number of registers in gdbstub	Max Filippov	2018-03-13	1	-0/+1
*	target/*/cpu.h: remove softfloat.h	Alex Bennée	2018-02-21	1	-1/+0
*	target/xtensa: allow different default CPU for MMU/noMMU	Max Filippov	2018-01-22	1	-1/+6
*	target/xtensa: implement GPIO32	Max Filippov	2018-01-09	1	-0/+1
*	target/xtensa: add internal/noop SRs and opcodes	Max Filippov	2018-01-09	1	-0/+2
*	target/xtensa: use libisa for instruction decoding	Max Filippov	2018-01-09	1	-0/+3
*	target/xtensa: extract FPU2000 opcode translators	Max Filippov	2017-12-19	1	-0/+1
*	target/xtensa: extract core opcode translators	Max Filippov	2017-12-19	1	-0/+24
*	xtensa: cleanup cpu type name composition	Igor Mammedov	2017-10-27	1	-0/+4
*	xtensa: replace cpu_xtensa_init() with cpu_generic_init()	Igor Mammedov	2017-09-01	1	-3/+1
*	target/xtensa: support output to chardev console	Max Filippov	2017-06-06	1	-0/+1
*	target/xtensa: sim: instantiate local memories	Max Filippov	2017-02-23	1	-0/+16
*	target-xtensa: implement RER/WER instructions	Max Filippov	2017-01-17	1	-0/+7
*	target/xtensa: implement MEMCTL SR	Max Filippov	2017-01-15	1	-0/+19
*	target/xtensa: support icount	Max Filippov	2017-01-15	1	-0/+5
*	target/xtensa: refactor CCOUNT/CCOMPARE	Max Filippov	2017-01-15	1	-5/+11
*	target/xtensa: implement RUNSTALL	Max Filippov	2017-01-15	1	-1/+2
*	target/xtensa: add static vectors selection	Max Filippov	2017-01-15	1	-1/+9
*	Move target-* CPU file into a target/ folder	Thomas Huth	2016-12-20	1	-0/+587