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* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-2/+2
* Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...Richard Henderson2021-11-031-1/+1
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| * monitor: Trim some trailing space from human-readable outputMarkus Armbruster2021-10-311-1/+1
* | target/xtensa: Make xtensa_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-023-23/+3Star
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* target/xtensa: Drop check for singlestep_enabledRichard Henderson2021-10-161-17/+8Star
* target/xtensa: list cores in a text filePaolo Bonzini2021-10-053-2/+14
* hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-221-2/+2
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-2/+0Star
* target/xtensa: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-8/+5Star
* target/xtensa: Restrict do_transaction_failed() to sysemuPhilippe Mathieu-Daudé2021-09-141-0/+2
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-2/+3
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-17/+0Star
* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell2021-07-121-6/+1Star
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| * target/xtensa: Use translator_use_goto_tbRichard Henderson2021-07-091-5/+1Star
| * tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé2021-07-091-1/+0Star
* | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-07-111-0/+2
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| * | meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé2021-07-091-0/+2
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* / target/xtensa/xtensa-semi: Fix compilation problem on HaikuThomas Huth2021-07-091-45/+39Star
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* hw/core: Constify TCGCPUOpsRichard Henderson2021-05-271-1/+1
* cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-271-0/+6
* cpu: Assert DeviceClass::vmsd is NULL on user emulationPhilippe Mathieu-Daudé2021-05-271-1/+3
* target/xtensa: clean up unaligned accessMax Filippov2021-05-202-66/+67
* target/xtensa: fix access ring in l32exMax Filippov2021-05-201-1/+1
* target/xtensa: don't generate extra EXCP_DEBUG on exceptionMax Filippov2021-05-204-19/+0Star
* target/xtensa: Make sure that tb->size != 0Ilya Leoshkevich2021-05-201-0/+3
* Do not include exec/address-spaces.h if it's not really necessaryThomas Huth2021-05-021-1/+0Star
* target/xtensa: make xtensa_modules static on importMax Filippov2021-04-031-0/+1
* target/xtensa: fix meson.build rule for xtensa coresMax Filippov2021-04-032-12/+4Star
* semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-102-2/+2
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-7/+16
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-052-3/+3
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: Move debug_excp_handler to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* xtensa tcg cpus: Fix Lesser GPL version numberChetan Pant2020-11-151-1/+1
* hmp: Pass monitor to mon_get_cpu_env()Kevin Wolf2020-11-131-1/+1
* target/xtensa: enable all coprocessors for linux-userMax Filippov2020-10-261-0/+1
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-232-3/+3
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-3/+5
* target/xtensa: import DSP3400 coreMax Filippov2020-08-216-0/+173129
* target/xtensa: import de233_fpu coreMax Filippov2020-08-216-0/+22538
* target/xtensa: implement FPU division and square rootMax Filippov2020-08-213-0/+132
* target/xtensa: add DFPU registers and opcodesMax Filippov2020-08-216-34/+1413