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Experimental fork of QEMU with video encoding patches
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Commit message (
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Author
Age
Files
Lines
*
target/s390x/translate: Fix RNSBG instruction
Thomas Huth
2020-02-26
1
-1
/
+1
*
Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEAD
Paolo Bonzini
2020-02-25
7
-19
/
+18
|
\
|
*
Avoid cpu_physical_memory_rw() with a constant is_write argument
Philippe Mathieu-Daudé
2020-02-20
1
-2
/
+2
|
*
Let cpu_[physical]_memory() calls pass a boolean 'is_write' argument
Philippe Mathieu-Daudé
2020-02-20
3
-6
/
+6
|
*
Avoid address_space_rw() with a constant is_write argument
Peter Maydell
2020-02-20
2
-10
/
+9
|
*
Let address_space_rw() calls pass a boolean 'is_write' argument
Philippe Mathieu-Daudé
2020-02-20
2
-5
/
+5
|
*
Remove unnecessary cast when using the cpu_[physical]_memory API
Philippe Mathieu-Daudé
2020-02-20
1
-3
/
+3
|
*
Remove unnecessary cast when using the address_space API
Philippe Mathieu-Daudé
2020-02-20
4
-4
/
+4
*
|
target/i386: check for empty register in FXAM
Paolo Bonzini
2020-02-25
1
-1
/
+5
*
|
target/arm: Set MVFR0.FPSP for ARMv5 cpus
Richard Henderson
2020-02-21
1
-4
/
+6
*
|
target/arm: Use isar_feature_aa32_simd_r32 more places
Richard Henderson
2020-02-21
3
-13
/
+11
*
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target/arm: Rename isar_feature_aa32_simd_r32
Richard Henderson
2020-02-21
2
-27
/
+28
*
|
target/arm: Convert PMULL.8 to gvec
Richard Henderson
2020-02-21
6
-55
/
+95
*
|
target/arm: Convert PMULL.64 to gvec
Richard Henderson
2020-02-21
5
-72
/
+39
*
|
target/arm: Convert PMUL.8 to gvec
Richard Henderson
2020-02-21
5
-37
/
+39
*
|
target/arm: Vectorize USHL and SSHL
Richard Henderson
2020-02-21
6
-66
/
+389
*
|
target/arm: Correctly implement ACTLR2, HACTLR2
Peter Maydell
2020-02-21
4
-9
/
+33
*
|
target/arm: Use FIELD_EX32 for testing 32-bit fields
Peter Maydell
2020-02-21
1
-9
/
+9
*
|
target/arm: Use isar_feature function for testing AA32HPD feature
Peter Maydell
2020-02-21
2
-2
/
+7
*
|
target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
Peter Maydell
2020-02-21
6
-79
/
+106
*
|
target/arm: Correct handling of PMCR_EL0.LC bit
Peter Maydell
2020-02-21
1
-4
/
+9
*
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target/arm: Correct definition of PMCRDP
Peter Maydell
2020-02-21
1
-1
/
+2
*
|
target/arm: Provide ARMv8.4-PMU in '-cpu max'
Peter Maydell
2020-02-21
1
-0
/
+8
*
|
target/arm: Implement ARMv8.4-PMU extension
Peter Maydell
2020-02-21
2
-1
/
+39
*
|
target/arm: Implement ARMv8.1-PMU extension
Peter Maydell
2020-02-21
1
-2
/
+30
*
|
target/arm: Read debug-related ID registers from KVM
Peter Maydell
2020-02-21
3
-0
/
+49
*
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target/arm: Move DBGDIDR into ARMISARegisters
Peter Maydell
2020-02-21
5
-12
/
+12
*
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target/arm: Stop assuming DBGDIDR always exists
Peter Maydell
2020-02-21
4
-19
/
+57
*
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target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
Peter Maydell
2020-02-21
4
-11
/
+25
*
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target/arm: Define an aa32_pmu_8_1 isar feature test function
Peter Maydell
2020-02-21
4
-21
/
+27
*
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target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
Peter Maydell
2020-02-21
1
-1
/
+1
*
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target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
Peter Maydell
2020-02-21
3
-4
/
+14
*
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target/arm: Factor out PMU register definitions
Peter Maydell
2020-02-21
1
-76
/
+82
*
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target/arm: Define and use any_predinv isar_feature test
Peter Maydell
2020-02-21
2
-8
/
+6
*
|
target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
Peter Maydell
2020-02-21
2
-2
/
+19
*
|
target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
Peter Maydell
2020-02-21
1
-1
/
+1
*
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target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers
Peter Maydell
2020-02-21
5
-10
/
+19
*
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target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
Richard Henderson
2020-02-21
2
-34
/
+37
*
|
target/arm: Remove ttbr1_valid check from get_phys_addr_lpae
Richard Henderson
2020-02-21
1
-5
/
+1
*
|
target/arm: Fix select for aa64_va_parameters_both
Richard Henderson
2020-02-21
1
-22
/
+24
*
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target/arm: Use bit 55 explicitly for pauth
Richard Henderson
2020-02-21
1
-1
/
+2
*
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target/arm: Flush high bits of sve register after AdvSIMD INS
Richard Henderson
2020-02-21
1
-0
/
+6
*
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target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
Richard Henderson
2020-02-21
1
-0
/
+1
*
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target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
Richard Henderson
2020-02-21
1
-0
/
+1
*
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target/arm: Flush high bits of sve register after AdvSIMD EXT
Richard Henderson
2020-02-21
1
-0
/
+1
*
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target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition
BALATON Zoltan
2020-02-20
1
-91
/
+54
*
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target/ppc/cpu.h: Move fpu related members closer in cpu env
BALATON Zoltan
2020-02-20
1
-5
/
+4
*
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target/ppc: Fix typo in comments
BALATON Zoltan
2020-02-20
2
-5
/
+5
*
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target/ppc/cpu.h: Remove duplicate includes
BALATON Zoltan
2020-02-20
1
-2
/
+0
*
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target/i386/whpx: Remove superfluous semicolon
Philippe Mathieu-Daudé
2020-02-18
1
-1
/
+1
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/
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