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* target/mips: Amend MXU ASE overview noteAleksandar Markovic2018-10-291-10/+74
* target/mips: Move MXU_EN check one level higherAleksandar Markovic2018-10-291-271/+238Star
* target/mips: Add emulation of MXU instructions S32LDD and S32LDDRCraig Janeczek2018-10-291-7/+47
* target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSUCraig Janeczek2018-10-291-7/+94
* target/mips: Add emulation of MXU instruction D16MACCraig Janeczek2018-10-291-3/+87
* target/mips: Add emulation of MXU instruction D16MULCraig Janeczek2018-10-291-3/+63
* target/mips: Add emulation of MXU instruction S8LDDCraig Janeczek2018-10-291-3/+87
* target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switchAleksandar Markovic2018-10-291-18/+23
* target/mips: Add emulation of MXU instructions S32I2M and S32M2ICraig Janeczek2018-10-291-6/+85
* target/mips: Add emulation of non-MXU MULL within MXU decoding engineCraig Janeczek2018-10-291-1/+18
* target/mips: Add bit encoding for MXU operand getting pattern 'optn3'Craig Janeczek2018-10-291-0/+10
* target/mips: Add bit encoding for MXU operand getting pattern 'optn2'Craig Janeczek2018-10-291-0/+6
* target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'Aleksandar Markovic2018-10-291-0/+6
* target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'Craig Janeczek2018-10-291-0/+6
* target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'Aleksandar Markovic2018-10-291-0/+6
* target/mips: Add MXU decoding engineAleksandar Markovic2018-10-291-2/+1141
* target/mips: Add and integrate MXU decoding engine placeholderAleksandar Markovic2018-10-291-0/+8
* target/mips: Amend MXU instruction opcodesAleksandar Markovic2018-10-291-91/+69Star
* target/mips: Define a bit for MXU in insn_flagsCraig Janeczek2018-10-291-0/+1
* target/mips: Introduce MXU registersCraig Janeczek2018-10-292-0/+30
* target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder casesAleksandar Markovic2018-10-291-0/+2
* target/mips: Add disassembler support for nanoMIPSAleksandar Markovic2018-10-251-2/+11
* target/mips: Implement emulation of nanoMIPS EVA instructionsDimitrije Nikolic2018-10-251-0/+128
* target/mips: Add nanoMIPS CRC32 instruction poolAleksandar Markovic2018-10-251-0/+10
* Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' in...Peter Maydell2018-10-256-362/+420
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| * RISC-V: Update CSR and interrupt definitionsMichael Clark2018-10-173-321/+370
| * RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark2018-10-173-36/+35Star
| * RISC-V: Allow setting and clearing multiple irqsMichael Clark2018-10-172-18/+28
* | Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part...Peter Maydell2018-10-243-19/+908
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| * | target/mips: Fix decoding of ALIGN and DALIGN instructionsAleksandar Markovic2018-10-241-8/+32
| * | target/mips: Fix the title of translate.cAleksandar Markovic2018-10-241-1/+1
| * | target/mips: Define the R5900 CPUFredrik Noring2018-10-241-0/+59
| * | target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user onlyFredrik Noring2018-10-241-1/+22
| * | target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IVFredrik Noring2018-10-241-2/+3
| * | target/mips: Support R5900 DIV1 and DIVU1 instructionsFredrik Noring2018-10-241-3/+9
| * | target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructionsFredrik Noring2018-10-241-6/+17
| * | target/mips: Support R5900 three-operand MULT1 and MULTU1 instructionsFredrik Noring2018-10-241-3/+14
| * | target/mips: Support R5900 three-operand MULT and MULTU instructionsFredrik Noring2018-10-241-0/+74
| * | target/mips: Add a placeholder for R5900 MMI3 instruction subclassFredrik Noring2018-10-241-1/+30
| * | target/mips: Add a placeholder for R5900 MMI2 instruction subclassFredrik Noring2018-10-241-1/+39
| * | target/mips: Add a placeholder for R5900 MMI1 instruction subclassFredrik Noring2018-10-241-1/+35
| * | target/mips: Add a placeholder for R5900 MMI0 instruction subclassFredrik Noring2018-10-241-1/+42
| * | target/mips: Add a placeholder for R5900 MMI instruction classFredrik Noring2018-10-241-1/+44
| * | target/mips: Add a placeholder for R5900 LQFredrik Noring2018-10-241-2/+11
| * | target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWRFredrik Noring2018-10-241-1/+52
| * | target/mips: Define R5900 MMI3 opcode constantsFredrik Noring2018-10-241-0/+39
| * | target/mips: Define R5900 MMI2 opcode constantsFredrik Noring2018-10-241-0/+48
| * | target/mips: Define R5900 MMI1 opcode constantsFredrik Noring2018-10-241-0/+44
| * | target/mips: Define R5900 MMI0 opcode constantsFredrik Noring2018-10-241-0/+51
| * | target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constantsFredrik Noring2018-10-241-0/+51
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