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* | | target/mips: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-145-26/+22Star
* | | target/microblaze: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-12/+5Star
* | | target/m68k: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-14/+6Star
* | | target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folderPhilippe Mathieu-Daudé2021-09-142-64/+62Star
* | | target/i386: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-9/+5Star
* | | target/hppa: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-8/+5Star
* | | target/cris: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-18/+5Star
* | | target/arm: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-7/+9
* | | target/alpha: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-5/+4Star
* | | accel/tcg: Rename user-mode do_interrupt hack as fake_user_interruptPhilippe Mathieu-Daudé2021-09-141-2/+4
* | | target/xtensa: Restrict do_transaction_failed() to sysemuPhilippe Mathieu-Daudé2021-09-141-0/+2
* | | target/i386: Simplify TARGET_X86_64 #ifdef'ryPhilippe Mathieu-Daudé2021-09-141-3/+1Star
* | | target/i386: Restrict sysemu-only fpu_helper helpersPhilippe Mathieu-Daudé2021-09-141-0/+3
* | | target/avr: Remove pointless use of CONFIG_USER_ONLY definitionPhilippe Mathieu-Daudé2021-09-141-3/+0Star
* | | tcg: Remove tcg_global_reg_new definesBin Meng2021-09-141-3/+0Star
* | | accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-1419-46/+53
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* | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210913-...Peter Maydell2021-09-139-108/+156
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| * target/arm: Merge disas_a64_insn into aarch64_tr_translate_insnRichard Henderson2021-09-131-115/+109Star
| * target/arm: Take an exception if PSTATE.IL is setPeter Maydell2021-09-137-0/+49
| * hw/arm/virt: add ITS support in virt GICShashi Mallela2021-09-131-2/+2
| * hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VMMarc Zyngier2021-09-131-1/+6
* | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-09-139-56/+169
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| * Fix nvmm_ram_block_added() function argumentsReinoud Zandijk2021-09-131-2/+3
| * target/i386: Added vVMLOAD and vVMSAVE featureLara Lazier2021-09-134-1/+34
| * target/i386: Added changed priority check for VIRQLara Lazier2021-09-133-15/+22
| * target/i386: Added ignore TPR check in ctl_has_irqLara Lazier2021-09-131-0/+5
| * target/i386: Added VGIF V_IRQ masking capabilityLara Lazier2021-09-133-2/+19
| * target/i386: Moved int_ctl into CPUX86State structureLara Lazier2021-09-136-38/+41
| * target/i386: Added VGIF featureLara Lazier2021-09-133-3/+37
| * target/i386: VMRUN and VMLOAD canonicalizationsLara Lazier2021-09-133-18/+30
| * target/i386: add missing bits to CR4_RESERVED_MASKDaniel P. Berrangé2021-09-131-0/+1
* | target/sparc: Drop use of gen_io_end()Peter Maydell2021-09-081-15/+10Star
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* s390x/cpumodel: Add more feature to gen16 default modelChristian Borntraeger2021-09-071-1/+7
* hw/s390x/s390-skeys: lazy storage key enablement under TCGDavid Hildenbrand2021-09-062-0/+17
* s390x/mmu_helper: avoid setting the storage key if nothing changedDavid Hildenbrand2021-09-061-4/+7
* s390x/mmu_helper: move address validation into mmu_translate*()David Hildenbrand2021-09-064-29/+24Star
* s390x/mmu_helper: fixup mmu_translate() documentationDavid Hildenbrand2021-09-061-1/+2
* s390x/mmu_helper: no need to pass access type to mmu_translate_asce()David Hildenbrand2021-09-061-2/+2
* s390x/tcg: check for addressing exceptions for RRBE, SSKE and ISKEDavid Hildenbrand2021-09-064-16/+35
* s390x/tcg: convert real to absolute address for RRBE, SSKE and ISKEDavid Hildenbrand2021-09-061-0/+3
* s390x/tcg: fix ignoring bit 63 when setting the storage key in SSKEDavid Hildenbrand2021-09-061-1/+1
* s390x/tcg: wrap address for RRBEDavid Hildenbrand2021-09-061-3/+4
* s390x/ioinst: Fix wrong MSCH alignment check on little endianDavid Hildenbrand2021-09-061-1/+1
* s390x/tcg: fix and optimize SPX (SET PREFIX)David Hildenbrand2021-09-061-1/+14
* target-arm: Add support for Fujitsu A64FXShuuichirou Ishii2021-09-011-0/+48
* target/arm: Enable MVE in Cortex-M55Peter Maydell2021-09-011-5/+2Star
* target/arm: Implement MVE VRINT insnsPeter Maydell2021-09-014-0/+93
* target/arm: Implement MVE VCVT between single and half precisionPeter Maydell2021-09-014-0/+108
* target/arm: Implement MVE VCVT with specified rounding modePeter Maydell2021-09-014-0/+105
* target/arm: Implement MVE VCVT between fp and integerPeter Maydell2021-09-012-0/+39
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