summaryrefslogtreecommitdiffstats
path: root/target
Commit message (Expand)AuthorAgeFilesLines
* target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta2021-12-201-4/+4
* target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang2021-12-202-6/+13
* target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang2021-12-204-8/+8
* target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang2021-12-204-0/+67
* target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang2021-12-201-18/+18
* target/riscv: rvv-1.0: add vsetivli instructionFrank Chang2021-12-202-0/+29
* target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang2021-12-204-0/+197
* target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang2021-12-204-0/+189
* target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang2021-12-203-0/+187
* target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang2021-12-201-0/+22
* target/riscv: rvv-1.0: implement vstart CSRFrank Chang2021-12-205-103/+199
* target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang2021-12-203-4/+4
* target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang2021-12-204-44/+97
* target/riscv: add "set round to odd" rounding mode helper functionFrank Chang2021-12-204-0/+14
* target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang2021-12-204-14/+63
* target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang2021-12-202-36/+59
* target/riscv: introduce floating-point rounding mode enumFrank Chang2021-12-203-15/+24
* target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang2021-12-201-12/+12
* target/riscv: rvv-1.0: remove integer extract instructionFrank Chang2021-12-202-24/+0Star
* target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang2021-12-204-17/+0Star
* target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang2021-12-204-243/+0Star
* target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: widening floating-point reduction instructionsFrank Chang2021-12-201-1/+8
* target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang2021-12-202-9/+15
* target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang2021-12-204-50/+50
* target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang2021-12-204-45/+121
* target/riscv: rvv-1.0: slide instructionsFrank Chang2021-12-201-7/+12
* target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang2021-12-202-5/+2Star
* target/riscv: rvv-1.0: floating-point compare instructionsFrank Chang2021-12-201-9/+0Star
* target/riscv: rvv-1.0: integer comparison instructionsFrank Chang2021-12-202-11/+2Star
* target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: widening integer multiply-add instructionsFrank Chang2021-12-201-3/+3
* target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang2021-12-204-51/+51
* target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang2021-12-203-26/+17Star
* target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang2021-12-201-3/+3
* target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang2021-12-204-6/+102
* target/riscv: rvv-1.0: integer extension instructionsFrank Chang2021-12-204-0/+133
* target/riscv: rvv-1.0: whole register move instructionsFrank Chang2021-12-202-0/+29
* target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang2021-12-203-26/+21Star
* target/riscv: rvv-1.0: floating-point move instructionFrank Chang2021-12-201-2/+14
* target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang2021-12-202-9/+37
* target/riscv: rvv-1.0: register gather instructionsFrank Chang2021-12-204-12/+43
* target/riscv: rvv-1.0: allow load element with sign-extendedFrank Chang2021-12-201-10/+22
* target/riscv: rvv-1.0: element index instructionFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: iota instructionFrank Chang2021-12-202-3/+9
* target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang2021-12-203-8/+7Star
* target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang2021-12-204-7/+7
* target/riscv: rvv-1.0: count population in mask instructionFrank Chang2021-12-204-8/+9
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 00:44:23 +0100