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| * target/arm: Don't NOCP fault for FPCXT_NS accessesPeter Maydell2021-06-215-528/+542
| * target/arm: Handle FPU being disabled in FPCXT_NS accessesPeter Maydell2021-06-211-2/+30
| * target/arm/translate-vfp.c: Whitespace fixesPeter Maydell2021-06-211-6/+5Star
| * target/arm: Use acpi_ghes_present() to see if we report ACPI memory errorsPeter Maydell2021-06-211-5/+1Star
* | Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210621' into...Peter Maydell2021-06-2218-565/+1496
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| * | target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstubRichard Henderson2021-06-211-13/+2Star
| * | target/s390x: Improve s390_cpu_dump_state vs cc_opRichard Henderson2021-06-211-5/+7
| * | target/s390x: Do not modify cpu state in s390_cpu_get_psw_maskRichard Henderson2021-06-211-4/+4
| * | target/s390x: Expose load_psw and get_psw_mask to cpu.hRichard Henderson2021-06-216-61/+69
| * | s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2David Hildenbrand2021-06-212-8/+11
| * | s390x/tcg: We support Vector enhancements facilityDavid Hildenbrand2021-06-211-0/+1
| * | s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)David Hildenbrand2021-06-215-0/+391
| * | s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand2021-06-214-2/+49
| * | s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand2021-06-213-8/+87
| * | s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand2021-06-213-2/+70
| * | s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand2021-06-211-33/+73
| * | s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDEDDavid Hildenbrand2021-06-213-1/+30
| * | s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENEDDavid Hildenbrand2021-06-213-3/+30
| * | s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand2021-06-213-9/+77
| * | s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *David Hildenbrand2021-06-213-12/+121
| * | s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT)David Hildenbrand2021-06-213-15/+109
| * | s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT)David Hildenbrand2021-06-213-14/+153
| * | s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICALDavid Hildenbrand2021-06-212-0/+52
| * | s390x/tcg: Implement VECTOR BIT PERMUTEDavid Hildenbrand2021-06-214-0/+33
| * | s390x/tcg: Simplify wfc64() handlingDavid Hildenbrand2021-06-211-11/+12
| * | s390x/tcg: Simplify vflr64() handlingDavid Hildenbrand2021-06-213-25/+8Star
| * | s390x/tcg: Simplify vfll32() handlingDavid Hildenbrand2021-06-213-22/+6Star
| * | s390x/tcg: Simplify vfma64() handlingDavid Hildenbrand2021-06-213-32/+20Star
| * | s390x/tcg: Simplify vftci64() handlingDavid Hildenbrand2021-06-213-24/+13Star
| * | s390x/tcg: Simplify vfc64() handlingDavid Hildenbrand2021-06-213-107/+38Star
| * | s390x/tcg: Simplify vop64_2() handlingDavid Hildenbrand2021-06-213-156/+58Star
| * | s390x/tcg: Simplify vop64_3() handlingDavid Hildenbrand2021-06-213-79/+30Star
| * | s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED)David Hildenbrand2021-06-211-2/+2
| * | s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handlingDavid Hildenbrand2021-06-212-6/+43
| * | s390x/kvm: remove unused gs handlingCornelia Huck2021-06-213-15/+1Star
* | | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210619-2' in...Peter Maydell2021-06-224-10/+0Star
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| * | tcg: Combine dh_is_64bit and dh_is_signed to dh_typecodeRichard Henderson2021-06-194-10/+0Star
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* | Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request'...Peter Maydell2021-06-211-0/+41
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| * i386: Add ratelimit for bus locks acquired in guestChenyi Qiang2021-06-171-0/+41
* | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-06-174-50/+94
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| * target/i386: Added Intercept CR0 writes checkLara Lazier2021-06-161-0/+9
| * target/i386: Added consistency checks for CR0Lara Lazier2021-06-163-3/+13
| * target/i386: Added consistency checks for VMRUN intercept and ASIDLara Lazier2021-06-161-0/+10
| * target/i386: Refactored intercept checks into cpu_svm_has_interceptLara Lazier2021-06-162-47/+62
* | bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operationsPeter Maydell2021-06-161-20/+0Star
* | target/arm: Move expand_pred_b() data to vec_helper.cPeter Maydell2021-06-163-99/+109
* | target/arm: Add framework for MVE decodePeter Maydell2021-06-165-0/+53
* | target/arm: Implement MVE LETP insnPeter Maydell2021-06-162-9/+97
* | target/arm: Implement MVE DLSTPPeter Maydell2021-06-162-5/+27
* | target/arm: Implement MVE WLSTP insnPeter Maydell2021-06-162-3/+42
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