bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
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* \|	target/riscv: vector integer min/max instructions	LIU Zhiwei	2020-07-02	4	-0/+122
* \|	target/riscv: vector integer comparison instructions	LIU Zhiwei	2020-07-02	4	-0/+246
* \|	target/riscv: vector narrowing integer right shift instructions	LIU Zhiwei	2020-07-02	4	-0/+123
* \|	target/riscv: vector single-width bit shift instructions	LIU Zhiwei	2020-07-02	4	-0/+165
* \|	target/riscv: vector bitwise logical instructions	LIU Zhiwei	2020-07-02	4	-0/+96
* \|	target/riscv: vector integer add-with-carry / subtract-with-borrow instructions	LIU Zhiwei	2020-07-02	4	-0/+294
* \|	target/riscv: vector widening integer add and subtract	LIU Zhiwei	2020-07-02	4	-0/+362
* \|	target/riscv: vector single-width integer add and subtract	LIU Zhiwei	2020-07-02	4	-0/+509
* \|	target/riscv: add vector amo operations	LIU Zhiwei	2020-07-02	6	-0/+339
* \|	target/riscv: add fault-only-first unit stride load	LIU Zhiwei	2020-07-02	4	-0/+212
* \|	target/riscv: add vector index load and store instructions	LIU Zhiwei	2020-07-02	4	-0/+293
* \|	target/riscv: add vector stride load and store instructions	LIU Zhiwei	2020-07-02	6	-0/+914
* \|	target/riscv: add an internals.h header	LIU Zhiwei	2020-07-02	1	-0/+24
* \|	target/riscv: add vector configure instruction	LIU Zhiwei	2020-07-02	7	-12/+210
* \|	target/riscv: support vector extension csr	LIU Zhiwei	2020-07-02	2	-1/+89
* \|	target/riscv: implementation-defined constant parameters	LIU Zhiwei	2020-07-02	2	-0/+12
* \|	target/riscv: add vector extension field in CPURISCVState	LIU Zhiwei	2020-07-02	2	-1/+14
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*	hw/mips: Implement the kvm_type() hook in MachineClass	Huacai Chen	2020-06-27	2	-0/+37
*	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626'...	Peter Maydell	2020-06-26	21	-857/+4141
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\| *	target/arm: Enable MTE	Richard Henderson	2020-06-26	1	-0/+5
\| *	target/arm: Add allocation tag storage for system mode	Richard Henderson	2020-06-26	1	-0/+131
\| *	target/arm: Create tagged ram when MTE is enabled	Richard Henderson	2020-06-26	2	-4/+54
\| *	target/arm: Cache the Tagged bit for a page in MemTxAttrs	Richard Henderson	2020-06-26	2	-3/+50
\| *	target/arm: Always pass cacheattr to get_phys_addr	Richard Henderson	2020-06-26	4	-36/+42
\| *	target/arm: Set PSTATE.TCO on exception entry	Richard Henderson	2020-06-26	1	-0/+3
\| *	target/arm: Implement data cache set allocation tags	Richard Henderson	2020-06-26	3	-1/+58
\| *	target/arm: Complete TBI clearing for user-only for SVE	Richard Henderson	2020-06-26	3	-2/+25
\| *	target/arm: Add mte helpers for sve scatter/gather memory ops	Richard Henderson	2020-06-26	3	-253/+877
\| *	target/arm: Handle TBI for sve scalar + int memory ops	Richard Henderson	2020-06-26	3	-3/+6
\| *	target/arm: Add mte helpers for sve scalar + int ff/nf loads	Richard Henderson	2020-06-26	3	-100/+357
\| *	target/arm: Add mte helpers for sve scalar + int stores	Richard Henderson	2020-06-26	3	-78/+226
\| *	target/arm: Add mte helpers for sve scalar + int loads	Richard Henderson	2020-06-26	5	-98/+385
\| *	target/arm: Add arm_tlb_bti_gp	Richard Henderson	2020-06-26	3	-2/+15
\| *	target/arm: Tidy trans_LD1R_zpri	Richard Henderson	2020-06-26	1	-5/+7
\| *	target/arm: Use mte_check1 for sve LD1R	Richard Henderson	2020-06-26	1	-2/+4
\| *	target/arm: Use mte_checkN for sve unpredicated stores	Richard Henderson	2020-06-26	1	-28/+33
\| *	target/arm: Use mte_checkN for sve unpredicated loads	Richard Henderson	2020-06-26	1	-28/+33
\| *	target/arm: Add helper_mte_check_zva	Richard Henderson	2020-06-26	3	-1/+122
\| *	target/arm: Implement helper_mte_checkN	Richard Henderson	2020-06-26	2	-1/+166
\| *	target/arm: Implement helper_mte_check1	Richard Henderson	2020-06-26	2	-1/+179
\| *	target/arm: Add gen_mte_checkN	Richard Henderson	2020-06-26	4	-16/+66
\| *	target/arm: Add gen_mte_check1	Richard Henderson	2020-06-26	5	-24/+95
\| *	target/arm: Move regime_tcr to internals.h	Richard Henderson	2020-06-26	2	-9/+9
\| *	target/arm: Move regime_el to internals.h	Richard Henderson	2020-06-26	2	-36/+36
\| *	target/arm: Implement the access tag cache flushes	Richard Henderson	2020-06-26	1	-0/+65
\| *	target/arm: Implement the LDGM, STGM, STZGM instructions	Richard Henderson	2020-06-26	4	-8/+153
\| *	target/arm: Simplify DC_ZVA	Richard Henderson	2020-06-26	1	-70/+26
\| *	target/arm: Restrict the values of DCZID.BS under TCG	Richard Henderson	2020-06-26	1	-0/+24
\| *	target/arm: Implement the STGP instruction	Richard Henderson	2020-06-26	1	-3/+26
\| *	target/arm: Implement LDG, STG, ST2G instructions	Richard Henderson	2020-06-26	5	-5/+386