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* target/arm: Implement SME LDR, STRRichard Henderson2022-07-112-0/+31
| | | | | | | | | | We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Export unpredicated ld/st from translate-sve.cRichard Henderson2022-07-112-12/+39
| | | | | | | | | | Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement SME LD1, ST1Richard Henderson2022-07-114-0/+756
| | | | | | | | | | | We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement SME MOVARichard Henderson2022-07-118-1/+331
| | | | | | | | | | | We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement SME ZERORichard Henderson2022-07-114-0/+44
| | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement SME RDSVL, ADDSVL, ADDSPLRichard Henderson2022-07-113-1/+54
| | | | | | | | | | These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Handle SME in sve_access_checkRichard Henderson2022-07-111-6/+16
| | | | | | | | | | The pseudocode for CheckSVEEnabled gains a check for Streaming SVE mode, and for SME present but SVE absent. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Add SME enablement checksRichard Henderson2022-07-112-0/+55
| | | | | | | | | | These functions will be used to verify that the cpu is in the correct state for a given instruction. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark LD1RO as non-streamingRichard Henderson2022-07-112-3/+2Star
| | | | | | | | | | Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark LDFF1 and LDNF1 as non-streamingRichard Henderson2022-07-112-2/+2
| | | | | | | | | | Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark gather prefetch as non-streamingRichard Henderson2022-07-113-8/+16
| | | | | | | | | | | Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. In this case, introduce PRF_ns (prefetch non-streaming) to handle the checks. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark gather/scatter load/store as non-streamingRichard Henderson2022-07-112-9/+6Star
| | | | | | | | | | Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark string/histo/crypto as non-streamingRichard Henderson2022-07-112-18/+18
| | | | | | | | | | Mark these as non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark SMMLA, UMMLA, USMMLA as non-streamingRichard Henderson2022-07-112-7/+6Star
| | | | | | | | | | Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark FTSMUL, FTMAD, FADDA as non-streamingRichard Henderson2022-07-112-7/+11
| | | | | | | | | | Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark PMULL, FMMLA as non-streamingRichard Henderson2022-07-112-11/+15
| | | | | | | | | | Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streamingRichard Henderson2022-07-112-13/+12Star
| | | | | | | | | | Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark RDFFR, WRFFR, SETFFR as non-streamingRichard Henderson2022-07-112-5/+6
| | | | | | | | | | Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Mark ADR as non-streamingRichard Henderson2022-07-113-5/+11
| | | | | | | | | | | | | Mark ADR as a non-streaming instruction, which should trap if full a64 support is not enabled in streaming mode. Removing entries from sme-fa64.decode is an easy way to see what remains to be done. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Trap non-streaming usage when Streaming SVE is activeRichard Henderson2022-07-118-2/+195
| | | | | | | | | | | | | | | | | | | | | | | | This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought to be trivially true, but the pseudocode still contains a number of conditions, and QEMU has not yet committed to dropping A32 support for EL[12] when v9 features are present. Since the computation of SME_TRAP_NONSTREAMING is necessarily different for the two modes, we might as well preserve bits within TBFLAG_ANY and allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead. Note that DDI0616A.a has typos for bits [22:21] of LD1RO in the table of instructions illegal in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Add infrastructure for disas_smeRichard Henderson2022-07-115-1/+64
| | | | | | | | | | This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Handle SME in aarch64_cpu_dump_stateRichard Henderson2022-07-111-1/+16
| | | | | | | | | Dump SVCR, plus use the correct access check for Streaming Mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge tag 'pull-target-arm-20220707' of ↵Richard Henderson2022-07-089-514/+637
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm/virt: dt: add rng-seed property * Fix MTE check in sve_ldnfff1_r * Record tagged bit for user-only in sve_probe_page * Correctly implement OS Lock and OS DoubleLock * Implement DBGDEVID, DBGDEVID1, DBGDEVID2 registers * Fix qemu-system-arm handling of LPAE block descriptors for highmem # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmLG0O8ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3h1MEACnTd+jfssa/MdtQPP8N+cp # cvrdrW+V9iho1vLPGG3d6yni6T8IMdulA5OvSkiNz2IaspY3z3u/t01PCpqEF0tA # nl3HxA65ddehzG8QHpORiP2DIJfuYUcMaruK2zMcC//0EXBOVI215hkR7oNyC0r9 # PrYb+tiDVL1t3xzXWNKMoolZwUjS6M6dloxEu2b/d0tOBvtBLI0E7y9taANHCnmZ # 8r7ih0WRELo1rzveZVOXqnZGLUjFzbCurHCmshN6xr2V6iilBaLoaGHovZ2c489Z # Fz/Ui1tyvDUoajr/Ck57GYo0BwDf9dKYkl5RkchdeY+cA88CgJAVK5pT0Rrybpf0 # lMgSAalIFcnIr2kjdnWRUqL02t+HgnOnsBTSUpgiwMNKwjfMN5NDi9294GuMCu2h # 7UyuAkQvfTwoQyFzJYzuapcnB6i5BvQjq6GxSmogzuR6kNSFptNOGimMhqCO4kN0 # fixOHOOE/aj7QoXq33V9u3ESY1IleDMX6+Zff2RLmVQYZpQKW6LpCfuwgnZrZEN3 # 4hPiL+00bY9pWlXvvEHdu0/XYx8kPXtmdzgzpm80edCLUMFOVMDQMQE1Zy/qzC7S # 8ryfC2EvSQuigD1+s6I9WxCnHVv5Byz+DXgRCjRsitDPVu2kFcEgAibzz9K1WVUW # qwQP4WGUzFD/LNUwO/Vryw== # =TzwD # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Jul 2022 05:56:23 PM +0530 # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220707' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmem target/arm: Correctly implement Feat_DoubleLock target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2 target/arm: Suppress debug exceptions when OS Lock set target/arm: Move define_debug_regs() to debug_helper.c target/arm: Fix code style issues in debug helper functions target/arm: Record tagged bit for user-only in sve_probe_page target/arm: Fix MTE check in sve_ldnfff1_r hw/arm/virt: dt: add rng-seed property Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmemPeter Maydell2022-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 39a1fd25287f5d we fixed a bug in the handling of LPAE block descriptors where we weren't correctly zeroing out some RES0 bits. However this fix has a bug because the calculation of the mask is done at the wrong width: in descaddr &= ~(page_size - 1); page_size is a target_ulong, so in the 'qemu-system-arm' binary it is only 32 bits, and the effect is that we always zero out the top 32 bits of the calculated address. Fix the calculation by forcing the mask to be calculated with the same type as descaddr. This only affects 32-bit CPUs which support LPAE (e.g. cortex-a15) when used on board models which put RAM or devices above the 4GB mark and when the 'qemu-system-arm' executable is being used. It was also masked in 7.0 by the main bug reported in https://gitlab.com/qemu-project/qemu/-/issues/1078 where the virt board incorrectly does not enable 'highmem' for 32-bit CPUs. The workaround is to use 'qemu-system-aarch64' with the same command line. Reported-by: He Zhe <zhe.he@windriver.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220627134620.3190252-1-peter.maydell@linaro.org Fixes: 39a1fd25287f5de ("target/arm: Fix handling of LPAE block descriptors") Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Correctly implement Feat_DoubleLockPeter Maydell2022-07-072-2/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The architecture defines the OS DoubleLock as a register which (similarly to the OS Lock) suppresses debug events for use in CPU powerdown sequences. This functionality is required in Arm v7 and v8.0; from v8.2 it becomes optional and in v9 it must not be implemented. Currently in QEMU we implement the OSDLR_EL1 register as a NOP. This is wrong both for the "feature implemented" and the "feature not implemented" cases: if the feature is implemented then the DLK bit should read as written and cause suppression of debug exceptions, and if it is not implemented then the bit must be RAZ/WI. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2Peter Maydell2022-07-074-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting with v7 of the debug architecture, there are three extra ID registers that add information on top of that provided in DBGDIDR. These are DBGDEVID, DBGDEVID1 and DBGDEVID2. In the v7 debug architecture, DBGDEVID is optional, present only of DBGDIDR.DEVID_imp is set. In v7.1 all three must be present. Implement the missing registers. Note that we only need to set the values in the ARMISARegisters struct for the CPUs Cortex-A7, A15, A53, A57 and A72 (plus the 32-bit 'max' which uses the Cortex-A53 values): earlier CPUs didn't implement v7 of the architecture, and our other 64-bit CPUs (Cortex-A76, Neoverse-N1 and A64fx) don't have AArch32 support at EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-5-peter.maydell@linaro.org
| * target/arm: Suppress debug exceptions when OS Lock setPeter Maydell2022-07-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "OS Lock" in the Arm debug architecture is a way for software to suppress debug exceptions while it is trying to power down a CPU and save the state of the breakpoint and watchpoint registers. In QEMU we implemented the support for writing the OS Lock bit via OSLAR_EL1 and reading it via OSLSR_EL1, but didn't implement the actual behaviour. The required behaviour with the OS Lock set is: * debug exceptions (apart from BKPT insns) are suppressed * some MDSCR_EL1 bits allow write access to the corresponding EDSCR external debug status register that they shadow (we can ignore this because we don't implement external debug) * similarly with the OSECCR_EL1 which shadows the EDECCR (but we don't implement OSECCR_EL1 anyway) Implement the missing behaviour of suppressing debug exceptions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-4-peter.maydell@linaro.org
| * target/arm: Move define_debug_regs() to debug_helper.cPeter Maydell2022-07-074-530/+538
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The target/arm/helper.c file is very long and is a grabbag of all kinds of functionality. We have already a debug_helper.c which has code for implementing architectural debug. Move the code which defines the debug-related system registers out to this file also. This affects the define_debug_regs() function and the various functions and arrays which are used only by it. The functions raw_write() and arm_mdcr_el2_eff() and define_debug_regs() now need to be global rather than local to helper.c; everything else is pure code movement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-3-peter.maydell@linaro.org
| * target/arm: Fix code style issues in debug helper functionsPeter Maydell2022-07-071-20/+38
| | | | | | | | | | | | | | | | | | | | | | Before moving debug system register helper functions to a different file, fix the code style issues (mostly block comment syntax) so checkpatch doesn't complain about the code-motion patch. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-2-peter.maydell@linaro.org
| * target/arm: Record tagged bit for user-only in sve_probe_pageRichard Henderson2022-07-071-0/+3
| | | | | | | | | | | | | | | | | | | | Fixes a bug in that we were not honoring MTE from user-only SVE. Copy the user-only MTE logic from allocation_tag_mem into sve_probe_page. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Fix MTE check in sve_ldnfff1_rRichard Henderson2022-07-071-1/+1
| | | | | | | | | | | | | | | | | | The comment was correct, but the test was not: disable mte if tagged is *not* set. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge tag 'pull-request-2022-07-07' of https://gitlab.com/thuth/qemu into ↵Richard Henderson2022-07-072-25/+24Star
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Check validity of the address in the SET PREFIX instruction * Fix booting from devices that use 4k sectors, but are not like DASDs * Re-evaluate pending interrupts after EXECUTE of certain instructions # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmLGhkURHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbU76Q//Y4mEXxWZDpJTg7tL5SZP+UzBVttnCifv # 6q+2I0keOUs6wFhPq8TzBqkazT9wlv51cNrY2Q3fU9I3dpDeRbAXZR34UD4kw5an # Q+ZQcebuGSKLjzMrIb1DLAieq8OmZR5FvDUu16BbeJr6GIQIE80lMRfWh9j30UfW # tlxkXr15BnyPx6m0rSGwzkZD2vgfj5zSUrDtYJcUsfypIA9OOBMA7yNGNlO+d94V # UZiKgNQtAoBNm4hZh2M86nsUtem+WpMTZQnDnCpMLYvFV/u9jRQBFSR+Ay41hcEN # WYuLK61rkjc9gPWSjeNNT28x8RMvFJU4YNn1UDiMRSzrigxeui6MOW3SI/h3y6tI # 94yXmXV2IuDMibvOjK07nkDaEItqPxfj6zuM2xW1Nc+l8Sk12korFBpk/AZiD0Jo # R3u36efci3zNqDRDJvhGUv8sGcv0mwO7Agq1Bm3h5941gYwzQKILHCShL7DPzvQa # h+K1MsT7vWfh5++unkGUrN/Zd9CazEylbDuWtywK8lgQcTGDO/9rab8GeXfH/5es # Tp0RGJwxmalgrAHZPK9lqgpQaGw92ct2G5odvc82EXQhgccnN9mh54BHPfdKs95E # JZVrXtZH3Gtgl5MGZ+yJevWSc9h1iRnRF4a7QC3UlVBjA/9yAWzQUAnNGZOamE/s # F+pi89oWLn8= # =UsTi # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Jul 2022 12:37:49 PM +0530 # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined] # gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-07-07' of https://gitlab.com/thuth/qemu: target/s390x: Exit tb after executing ex_value target/s390x: Remove DISAS_PC_STALE_NOCHAIN target/s390x: Remove DISAS_PC_STALE target/s390x: Remove DISAS_GOTO_TB pc-bios/s390-ccw: Update the s390-ccw bios binaries with the virtio-blk fixes pc-bios/s390-ccw/netboot.mak: Ignore Clang's warnings about GNU extensions pc-bios/s390-ccw/virtio: Remove "extern" keyword from prototypes pc-bios/s390-ccw/virtio-blkdev: Request the right feature bits pc-bios/s390-ccw: Split virtio-scsi code from virtio_blk_setup_device() pc-bios/s390-ccw/virtio: Beautify the code for reading virtqueue configuration pc-bios/s390-ccw/virtio: Read device config after feature negotiation pc-bios/s390-ccw/virtio: Set missing status bits while initializing pc-bios/s390-ccw/virtio-blkdev: Remove virtio_assume_scsi() pc-bios/s390-ccw/virtio-blkdev: Simplify/fix virtio_ipl_disk_is_valid() pc-bios/s390-ccw/bootmap: Improve the guessing logic in zipl_load_vblk() pc-bios/s390-ccw/virtio: Introduce a macro for the DASD block size pc-bios/s390-ccw: Add a proper prototype for main() target/s390x/tcg: SPX: check validity of new prefix Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/s390x: Exit tb after executing ex_valueRichard Henderson2022-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When EXECUTE sets ex_value to interrupt the constructed instruction, we implicitly disable interrupts so that the value is not corrupted. Exit to the main loop after execution, so that we re-evaluate any pending interrupts. Reported-by: Sven Schnelle <svens@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220702060228.420454-5-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * target/s390x: Remove DISAS_PC_STALE_NOCHAINRichard Henderson2022-07-061-10/+11
| | | | | | | | | | | | | | | | | | | | | | Replace this with a flag: exit_to_mainloop. We can now control the exit for each of DISAS_TOO_MANY, DISAS_PC_UPDATED, and DISAS_PC_CC_UPDATED, and fold in the check for PER. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220702060228.420454-4-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * target/s390x: Remove DISAS_PC_STALERichard Henderson2022-07-061-9/+4Star
| | | | | | | | | | | | | | | | There is nothing to distinguish this from DISAS_TOO_MANY. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220702060228.420454-3-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * target/s390x: Remove DISAS_GOTO_TBRichard Henderson2022-07-061-6/+2Star
| | | | | | | | | | | | | | | | There is nothing to distinguish this from DISAS_NORETURN. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220702060228.420454-2-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * target/s390x/tcg: SPX: check validity of new prefixJanis Schoetterl-Glausch2022-07-061-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | According to the architecture, SET PREFIX must try to access the new prefix area and recognize an addressing exception if the area is not accessible. For qemu this check prevents a crash in cpu_map_lowcore after an inaccessible prefix area has been set. Signed-off-by: Janis Schoetterl-Glausch <scgl@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220630094340.3646279-1-scgl@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | target/ppc: Fix MPC8555 and MPC8560 core type to e500v1Pali Rohár2022-07-062-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") changed core type of MPC8555 and MPC8560 from e500v1 to e500v2. But both MPC8555 and MPC8560 have just e500v1 cores, there are no features of e500v2 cores. It can be verified by reading NXP documentations: https://www.nxp.com/docs/en/data-sheet/MPC8555EEC.pdf https://www.nxp.com/docs/en/data-sheet/MPC8560EC.pdf https://www.nxp.com/docs/en/reference-manual/MPC8555ERM.pdf https://www.nxp.com/docs/en/reference-manual/MPC8560RM.pdf Therefore fix core type of MPC8555 and MPC8560 back to e500v1. Just for completeness, here is list of all Motorola/Freescale/NXP processors which were released and have e500v1 or e500v2 cores: e500v1: MPC8540 MPC8541 MPC8555 MPC8560 e500v2: BSC9131 BSC9132 C291 C292 C293 MPC8533 MPC8535 MPC8536 MPC8543 MPC8544 MPC8545 MPC8547 MPC8548 MPC8567 MPC8568 MPC8569 MPC8572 P1010 P1011 P1012 P1013 P1014 P1015 P1016 P1020 P1021 P1022 P1024 P1025 P2010 P2020 Sorted alphabetically; not by release date / generation / feature set. All this is from public information available on NXP website. Seems that qemu has support only for some subset of MPC85xx processors. Historically processors with e500 cores have mpc85xx family codename and lot of software have them in mpc85xx architecture subdirectory. Note that GCC uses -mcpu=8540 option for specifying e500v1 core and -mcpu=8548 option for specifying e500v2 core. So sometimes (mpc)8540 is alias for e500v1 and (mpc)8548 is alias for e500v2. Fixes: 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220703195029.23793-1-pali@kernel.org> [danielhb: added more context in the commit msg] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc/cpu-models: Remove the "default" CPU aliasThomas Huth2022-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | QEMU emulates a *lot* of PowerPC-based machines - having a CPU that is named "default" and cannot be used with most of those machines sounds just wrong. Thus let's remove this old and confusing alias now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220705151030.662140-1-thuth@redhat.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: Return default CPU for max CPUMurilo Opsfelder Araujo2022-07-062-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All ppc CPUs represent hardware that exists in the real world, i.e.: we do not have a "max" CPU with all possible emulated features enabled. Return the default CPU type for the machine because that has greater chance of being useful as the "max" CPU. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038 Cc: Cédric Le Goater <clg@kaod.org> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Greg Kurz <groug@kaod.org> Cc: Matheus K. Ferst <matheus.ferst@eldorado.org.br> Cc: Thomas Huth <thuth@redhat.com> Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220628205513.81917-1-muriloo@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: implement cdtbcdMatheus Ferst2022-07-064-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Implements the Convert Declets To Binary Coded Decimal instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsFromDPD, DPD2BCD, etc), a positive decimal32 with zero exponent is used as an intermediate value to convert the declets. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220629162904.105060-12-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: implement cbcdtdMatheus Ferst2022-07-064-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implements the Convert Binary Coded Decimal To Declets instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsToDPD, BCD2DPD, etc.), the BCD values are converted to decimal32 format, from which the declets are extracted. Where the behavior is undefined, we try to match the result observed in a POWER9 DD2.3. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220629162904.105060-11-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: implement addg6sMatheus Ferst2022-07-062-0/+41
| | | | | | | | | | | | | | | | | | | | | | Implements the following Power ISA v2.06 instruction: addg6s: Add and Generate Sixes Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220629162904.105060-10-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: Add flag for ISA v2.06 BCDA instructionsMatheus Ferst2022-07-062-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds an insns_flags2 for the BCD assist instructions introduced in Power ISA 2.06. These instructions are not listed in the manuals for e5500[1] and e6500[2], so the flag is only added for POWER7/8/9/10 models. [1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM.pdf [2] https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220629162904.105060-9-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: Implement mffscdrn[i] instructionsVíctor Colombo2022-07-062-0/+46
| | | | | | | | | | | | | | Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220629162904.105060-7-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: Move mffs[.] to decodetreeVíctor Colombo2022-07-063-19/+21
| | | | | | | | | | | | | | Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220629162904.105060-6-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: Move mffsl to decodetreeVíctor Colombo2022-07-063-24/+17Star
| | | | | | | | | | | | | | Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220629162904.105060-5-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: Move mffsce to decodetreeVíctor Colombo2022-07-063-32/+20Star
| | | | | | | | | | | | | | Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220629162904.105060-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: Move mffscrn[i] to decodetreeVíctor Colombo2022-07-064-48/+50
| | | | | | | | | | | | | | Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220629162904.105060-3-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | target/ppc: Fix insn32.decode style issuesVíctor Colombo2022-07-061-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | Some lines in insn32.decode have inconsistent alignment when compared to others. Fix this by changing the alignment of some lines, making it more consistent throughout the file. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220629162904.105060-2-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-16 03:17:50 +0100