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* tcg/aarch64: Remove unused code in tcg_out_opQi Hu2022-10-251-17/+14Star
| | | | | | | | | | | | | AArch64 defines the TCG_TARGET_HAS_direct_jump. So the "else" block is useless in the case of "INDEX_op_goto_tb" in function "tcg_out_op". Add an assertion and delete these codes for clarity. Suggested-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Qi Hu <huqi@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221017020826.990729-1-huqi@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Fix illegal insn from out-of-range shliRichard Henderson2022-06-021-1/+1
| | | | | | | | | | The masking in tcg_out_shl was incorrect, producing an illegal instruction, rather than merely unspecified results for the out-of-range shift. Tested-by: Joel Stanley <joel@jms.id.au> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1051 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-061-2/+2
| | | | | | | | | | | | | | | | | | | Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before. This can help to make some code independent from qemu too. gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg/aarch64: Use 'ull' suffix to force 64-bit constantRichard Henderson2022-03-311-2/+2
| | | | | | | | | Typo used only 'ul' suffix, which is still 32-bits for windows host. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/947 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add opcodes for vector nand, nor, eqvRichard Henderson2022-03-041-0/+3
| | | | | | | | | | We've had placeholders for these opcodes for a while, and should have support on ppc, s390x and avx512 hosts. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Support raising sigbus for user-onlyRichard Henderson2022-02-082-19/+74
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-1/+1
| | | | | | | | | | | | | | Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson2021-10-061-7/+7
| | | | | | | | | We're about to move this out of tcg.h, so rename it as we did when moving MemOp. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Expand MO_SIZE to 3 bitsRichard Henderson2021-10-061-2/+2
| | | | | | | | | | | We have lacked expressive support for memory sizes larger than 64-bits for a while. Fixing that requires adjustment to several points where we used this for array indexing, and two places that develop -Wswitch warnings after the change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_HAS_goto_ptrRichard Henderson2021-07-101-1/+0Star
| | | | | | | | Since 6eea04347eb6, all tcg backends support goto_ptr. Remove the conditional, making support mandatory. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAPRichard Henderson2021-06-292-57/+32Star
| | | | | | | | | | The memory bswap support in the aarch64 backend merely dates from a time when it was required. There is nothing special about the backend support that could not have been provided by the middle-end even prior to the introduction of the bswap flags. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Support bswap flagsRichard Henderson2021-06-291-0/+12
| | | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Merge tcg_out_rev{16,32,64}Richard Henderson2021-06-291-26/+16Star
| | | | | | | | Pass in the input and output size. We currently use 3 of the 5 possible combinations; the others may be used by new tcg opcodes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Move MAX_CODE_GEN_BUFFER_SIZE to tcg-target.hRichard Henderson2021-06-111-0/+1
| | | | | | | | | Remove the ifdef ladder and move each define into the appropriate header file. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Change parameters for tcg_target_const_matchRichard Henderson2021-06-041-4/+1Star
| | | | | | | | | | | | Change the return value to bool, because that's what is should have been from the start. Pass the ct mask instead of the whole TCGArgConstraint, as that's the only part that's relevant. Change the value argument to int64_t. We will need the extra width for 32-bit hosts wanting to match vector constants. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Fix tcg_out_rotlYasuo Kuwahara2021-05-271-3/+2Star
| | | | | | | | | | | The last argument of tcg_out_extr() must be in the range 0-31 if ext==0. Before the fix, when m==0 it becomes 32 and it crashes with an Illegal instruction on Apple Silicon. After the fix, it will be 0. If m is in the range 1-31, it is the same as before. Signed-off-by: Yasuo Kuwahara <kwhr00@gmail.com> Message-Id: <CAHfJ0vSXnmnTLmT0kR=a8ACRdw_UsLYOhStzUzgVEHoH8U-7sA@mail.gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina2021-03-171-1/+2
| | | | | | | | | | | | | | | | | There are two different versions of prototype for tcg_out_op and tcg_out_vec_op functions: 1) using const TCGArg *args and const int *const_args arguments 2) using const TCGArg args[TCG_MAX_OP_ARGS] and const int const_args[TCG_MAX_OP_ARGS] aguments. This duality causes warnings on GCC 11 and prevents build using --enable-werror. As second version provides more information, unify functions prototypes to this variant. Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Message-Id: <20210312121418.139093-1-mrezanin@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Fix generation of "scalar" vector operationsRichard Henderson2021-03-061-30/+181
| | | | | | | | | | For some vector operations, "1D" is not a valid type, and there are separate instructions for the 64-bit scalar operation. Tested-by: Stefan Weil <sw@weilnetz.de> Buglink: https://bugs.launchpad.net/qemu/+bug/1916112 Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Fix I3617_CMLE0Richard Henderson2021-03-061-1/+1
| | | | | | | Fix a typo in the encodeing of the cmle (zero) instruction. Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Fix constant subtraction in tcg_out_addsub2Richard Henderson2021-03-061-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | An hppa guest executing 0x000000000000e05c: ldil L%10000,r4 0x000000000000e060: ldo 0(r4),r4 0x000000000000e064: sub r3,r4,sp produces ---- 000000000000e064 000000000000e068 sub2_i32 tmp0,tmp4,r3,$0x1,$0x10000,$0x0 after folding and constant propagation. Then we hit tcg-target.c.inc:640: tcg_out_insn_3401: Assertion `aimm <= 0xfff' failed. because aimm is in fact -16, but unsigned. The ((bl < 0) ^ sub) condition which negates bl is incorrect and will always lead to this abort. If the constant is positive, sub will make it negative; if the constant is negative, sub will keep it negative. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Do not convert TCGArg to temps that are not tempsRichard Henderson2021-02-051-3/+4
| | | | | | | | | | | Fixes INDEX_op_rotli_vec for aarch64 host, where the 3rd argument is an integer, not a temporary, which now tickles an assert added in e89b28a6350. Previously, the value computed into v2 would be garbage for rotli_vec, but as the value was unused it caused no harm. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_CON_SET_HRichard Henderson2021-02-021-1/+0Star
| | | | | | | | | All backends have now been converted to tcg-target-con-set.h, so we can remove the fallback code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Split out constraint sets to tcg-target-con-set.hRichard Henderson2021-02-023-59/+66
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_CON_STR_HRichard Henderson2021-02-021-1/+0Star
| | | | | | | | | All backends have now been converted to tcg-target-con-str.h, so we can remove the fallback code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-43/+33Star
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-5/+5
| | | | | | | | Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to "t1 = -v2, t2 = c - v2". This avoids a serial dependency between t1 and t2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove movi and dupi opcodesRichard Henderson2021-01-131-3/+0Star
| | | | | | | | | These are now completely covered by mov from a TYPE_CONST temporary. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Increase tcg_out_dupi_vec immediate to int64_tRichard Henderson2021-01-131-6/+6
| | | | | | | | | | | | While we don't store more than tcg_target_long in TCGTemp, we shouldn't be limited to that for code generation. We will be able to use this for INDEX_op_dup2_vec with 2 constants. Also pass along the minimal vece that may be said to apply to the constant. This allows some simplification in the various backends. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use tcg_out_dupi_vec from temp_loadRichard Henderson2021-01-131-7/+0Star
| | | | | | | Having dupi pass though movi is confusing and arguably wrong. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Constify TCGLabelQemuLdst.raddrRichard Henderson2021-01-071-2/+1Star
| | | | | | | | | Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Constify tcg_code_gen_epilogueRichard Henderson2021-01-071-2/+1Star
| | | | | | | | | Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_SUPPORT_MIRRORRichard Henderson2021-01-071-1/+0Star
| | | | | | | | Now that all native tcg hosts support splitwx, remove the define. Replace the one use with a test for CONFIG_TCG_INTERPRETER. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Support split-wx code generationRichard Henderson2021-01-072-26/+33
| | | | | Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Use B not BL for tcg_out_goto_longRichard Henderson2021-01-071-1/+1
| | | | | | | A typo generated a branch-and-link insn instead of plain branch. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add --accel tcg,split-wx propertyRichard Henderson2021-01-071-0/+1
| | | | | | | | | Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend, so for now enabling it will result in an error. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Adjust tb_target_set_jmp_target for split-wxRichard Henderson2021-01-072-7/+7
| | | | | | | Pass both rx and rw addresses to tb_target_set_jmp_target. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Adjust tcg_register_jit for constRichard Henderson2021-01-071-1/+1
| | | | | | | | We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Adjust tcg_out_call for constRichard Henderson2021-01-071-1/+1
| | | | | | | | | We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Adjust TCGLabel for constRichard Henderson2021-01-071-1/+1
| | | | | | | | | Change TCGLabel.u.value_ptr to const, and initialize it with tcg_splitwx_to_rx. Propagate const through tcg/host/ only as far as needed to avoid errors from the value_ptr change. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Move tcg epilogue pointer out of TCGContextRichard Henderson2021-01-071-2/+2
| | | | | | | | This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* util: Enhance flush_icache_range with separate data pointerRichard Henderson2021-01-071-1/+1
| | | | | | | | | | | | | We are shortly going to have a split rw/rx jit buffer. Depending on the host, we need to flush the dcache at the rw data pointer and flush the icache at the rx code pointer. For now, the two passed pointers are identical, so there is no effective change in behaviour. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Introduce INDEX_op_qemu_st8_i32Richard Henderson2021-01-071-0/+1
| | | | | | | | | Enable this on i386 to restrict the set of input registers for an 8-bit store, as required by the architecture. This removes the last use of scratch registers for user-only mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* util: Extract flush_icache_range to cacheflush.cRichard Henderson2021-01-021-5/+0Star
| | | | | | | | | | | | This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Remove TCG_TARGET_HAS_cmp_vecRichard Henderson2020-10-081-1/+0Star
| | | | | | | The cmp_vec opcode is mandatory; this symbol is unused. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_CT_REGRichard Henderson2020-10-081-3/+0Star
| | | | | | | | This wasn't actually used for anything, really. All variable operands must accept registers, and which are indicated by the set in TCGArgConstraint.regs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Drop union from TCGArgConstraintRichard Henderson2020-10-081-7/+7
| | | | | | | | The union is unused; let "regs" appear in the main structure without the "u.regs" wrapping. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang's C11 atomic_fetch_*() functions only take a C11 atomic type pointer argument. QEMU uses direct types (int, etc) and this causes a compiler error when a QEMU code calls these functions in a source file that also included <stdatomic.h> via a system header file: $ CC=clang CXX=clang++ ./configure ... && make ../util/async.c:79:17: error: address argument to atomic operation must be a pointer to _Atomic type ('unsigned int *' invalid) Avoid using atomic_*() names in QEMU's atomic.h since that namespace is used by <stdatomic.h>. Prefix QEMU's APIs with 'q' so that atomic.h and <stdatomic.h> can co-exist. I checked /usr/include on my machine and searched GitHub for existing "qatomic_" users but there seem to be none. This patch was generated using: $ git grep -h -o '\<atomic\(64\)\?_[a-z0-9_]\+' include/qemu/atomic.h | \ sort -u >/tmp/changed_identifiers $ for identifier in $(</tmp/changed_identifiers); do sed -i "s%\<$identifier\>%q$identifier%g" \ $(git grep -I -l "\<$identifier\>") done I manually fixed line-wrap issues and misaligned rST tables. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200923105646.47864-1-stefanha@redhat.com>
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg/aarch64: Implement INDEX_op_rotl{i,v}_vecRichard Henderson2020-06-022-2/+52
| | | | | | | | For immediate rotate , we can implement this in two instructions, using SLI. For variable rotate, the oddness of aarch64 right-shift- as-negative-left-shift means a backend-specific expansion works best. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Implement gvec support for rotate by scalarRichard Henderson2020-06-021-0/+1
| | | | | | | | | | No host backend support yet, but the interfaces for rotls are in place. Only implement left-rotate for now, as the only known use of vector rotate by scalar is s390x, so any right-rotate would be unused and untestable. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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