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* tcg: Remove TCG_TARGET_CON_SET_HRichard Henderson2021-02-021-1/+0Star
| | | | | | | | | All backends have now been converted to tcg-target-con-set.h, so we can remove the fallback code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Split out constraint sets to tcg-target-con-set.hRichard Henderson2021-02-023-63/+69
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_CON_STR_HRichard Henderson2021-02-021-1/+0Star
| | | | | | | | | All backends have now been converted to tcg-target-con-str.h, so we can remove the fallback code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-56/+41Star
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove movi and dupi opcodesRichard Henderson2021-01-131-1/+0Star
| | | | | | | | | These are now completely covered by mov from a TYPE_CONST temporary. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Constify TCGLabelQemuLdst.raddrRichard Henderson2021-01-071-2/+1Star
| | | | | | | | | Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Constify tcg_code_gen_epilogueRichard Henderson2021-01-071-2/+1Star
| | | | | | | | | Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_SUPPORT_MIRRORRichard Henderson2021-01-071-1/+0Star
| | | | | | | | Now that all native tcg hosts support splitwx, remove the define. Replace the one use with a test for CONFIG_TCG_INTERPRETER. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Support split-wx code generationRichard Henderson2021-01-072-17/+22
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add --accel tcg,split-wx propertyRichard Henderson2021-01-071-0/+1
| | | | | | | | | Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend, so for now enabling it will result in an error. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Adjust tb_target_set_jmp_target for split-wxRichard Henderson2021-01-071-1/+1
| | | | | | | Pass both rx and rw addresses to tb_target_set_jmp_target. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Adjust tcg_register_jit for constRichard Henderson2021-01-071-1/+1
| | | | | | | | We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Adjust tcg_out_call for constRichard Henderson2021-01-071-1/+1
| | | | | | | | | We must change all targets at once, since all must match the declaration in tcg.c. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Adjust TCGLabel for constRichard Henderson2021-01-071-1/+1
| | | | | | | | | Change TCGLabel.u.value_ptr to const, and initialize it with tcg_splitwx_to_rx. Propagate const through tcg/host/ only as far as needed to avoid errors from the value_ptr change. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Move tcg epilogue pointer out of TCGContextRichard Henderson2021-01-071-1/+1
| | | | | | | | This value is constant across all thread-local copies of TCGContext, so we might as well move it out of thread-local storage. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Introduce INDEX_op_qemu_st8_i32Richard Henderson2021-01-071-0/+1
| | | | | | | | | Enable this on i386 to restrict the set of input registers for an 8-bit store, as required by the architecture. This removes the last use of scratch registers for user-only mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* util: Extract flush_icache_range to cacheflush.cRichard Henderson2021-01-021-5/+0Star
| | | | | | | | | | | | This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Remove TCG_CT_REGRichard Henderson2020-10-081-3/+0Star
| | | | | | | | This wasn't actually used for anything, really. All variable operands must accept registers, and which are indicated by the set in TCGArgConstraint.regs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Drop union from TCGArgConstraintRichard Henderson2020-10-081-13/+13
| | | | | | | | The union is unused; let "regs" appear in the main structure without the "u.regs" wrapping. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg/arm: Expand epilogue inlineRichard Henderson2020-02-281-10/+2Star
| | | | | | | | | It is, after all, just two instructions. Profiling on a cortex-a15, using -d nochain to increase the number of exit_tb that are executed, shows a minor improvement of 0.5%. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/arm: Split out tcg_out_epilogueRichard Henderson2020-02-281-8/+11
| | | | | | | We will shortly use this function from tcg_out_op as well. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Search includes in the parent source directoryPhilippe Mathieu-Daudé2020-01-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | All the *.inc.c files included by tcg/$TARGET/tcg-target.inc.c are in tcg/, their parent directory. To simplify the preprocessor search path, include the relative parent path: '..'. Patch created mechanically by running: $ for x in tcg-pool.inc.c tcg-ldst.inc.c; do \ sed -i "s,#include \"$x\",#include \"../$x\"," \ $(git grep -l "#include \"$x\""); \ done Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc parts) Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200101112303.20724-3-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-13/+13
| | | | | | | | | | | | | | Preparation for collapsing the two byte swaps, adjust_endianness and handle_bswap, along the I/O path. Target dependant attributes are conditionalized upon NEED_CPU_H. Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <81d9cd7d7f5aaadfa772d6c48ecee834e9cf7882.1566466906.git.tony.nguyen@bt.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Remove mostly unreachable tlb special caseRichard Henderson2019-06-101-11/+12
| | | | | | | | | | | There was nothing armv7 specific about the bic+cmp sequence, however looking at the set of guests more closely shows that the 8-bit immediate operand for the bic can only be satisfied with one guest in tree: baseline m-profile -- 10-bit pages with aligned 4-byte memory ops. Therefore it does not seem useful to keep this path. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Use LDRD to load tlb mask+tableRichard Henderson2019-06-101-26/+40
| | | | | | | | | | | | | | | | | | | | | | | | This changes the code generation for the tlb from e.g. ldr ip, [r6, #-0x10] ldr r2, [r6, #-0xc] and ip, ip, r4, lsr #8 ldrd r0, r1, [r2, ip]! ldr r2, [r2, #0x18] to ldrd r0, r1, [r6, #-0x10] and r0, r0, r4, lsr #8 ldrd r2, r3, [r1, r0]! ldr r1, [r1, #0x18] for armv7 hosts. Rearranging the register allocation in order to avoid overlap between the two ldrd pairs causes the patch to be larger than it ordinarily would be. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Move the softmmu tlb to CPUNegativeOffsetStateRichard Henderson2019-06-101-32/+8Star
| | | | | | | | | | | We have for some time had code within the tcg backends to handle large positive offsets from env. This move makes sure that need not happen. Indeed, we are able to assert at build time that simple offsets suffice for all hosts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Create struct CPUTLBRichard Henderson2019-06-101-7/+3Star
| | | | | | | | | | Move all softmmu tlb data into this structure. Arrange the members so that we are able to place mask+table together and at a smaller absolute offset from ENV. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Return bool success from tcg_out_movRichard Henderson2019-05-131-1/+2
| | | | | | | | | | | This patch merely changes the interface, aborting on all failures, of which there are currently none. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Use tcg_out_mov_reg in tcg_out_movRichard Henderson2019-05-131-1/+1
| | | | | | | | We have a function that takes an additional condition parameter over the standard backend interface. It already takes care of eliding no-op moves. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Restrict constant pool displacement to 12 bitsRichard Henderson2019-04-251-36/+21Star
| | | | | | | | | This will not necessarily restrict the size of the TB, since for v7 the majority of constant pool usage is for calls from the out-of-line ldst code, which is already at the end of the TB. But this does allow us to save one insn per reference on the off-chance. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Restart TB generation after out-of-line ldst overflowRichard Henderson2019-04-241-6/+10
| | | | | | This is part c of relocation overflow handling. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Support INDEX_op_extract2_i32Richard Henderson2019-04-242-1/+26
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add INDEX_op_extract2_{i32,i64}Richard Henderson2019-04-241-0/+1
| | | | | | | This will let backends implement the double-word shift operation. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cputlb: Remove static tlb sizingRichard Henderson2019-01-281-1/+0Star
| | | | | | | | Now that all tcg backends support TCG_TARGET_IMPLEMENTS_DYN_TLB, remove the define and the old code. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: enable dynamic TLB sizingRichard Henderson2019-01-282-71/+70Star
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: introduce dynamic TLB sizingEmilio G. Cota2019-01-281-0/+1
| | | | | | | | | | Disabled in all TCG backends for now. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20190116170114.26802-3-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add TCG_TARGET_HAS_MEMORY_BSWAPRichard Henderson2018-12-171-0/+1
| | | | | | | | For now, defined universally as true, since we previously required backends to implement swapped memory operations. Future patches may now remove that support where it is onerous. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Return false on failure from patch_relocRichard Henderson2018-12-171-6/+16
| | | | | | | | This does require an extra two checks within the slow paths to replace the assert that we're moving. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Return success from patch_relocRichard Henderson2018-12-171-1/+2
| | | | | | | | | | | This will move the assert for success from within (subroutines of) patch_reloc into the callers. It will also let new code do something different when a relocation is out of range. For the moment, all backends are trivially converted to return true. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Fold away "noaddr" branch routinesRichard Henderson2018-12-171-19/+3Star
| | | | | | | | There are one use apiece for these. There is no longer a need for preserving branch offset operands, as we no longer re-translate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Remove reloc_pc24_atomicRichard Henderson2018-12-171-8/+0Star
| | | | | | | It is unused since 3fb53fb4d12f2e7833bd1659e6013237b130ef20. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Reduce max TB opcode countRichard Henderson2018-06-151-1/+1
| | | | | | | | | | | | | | | | | | | Also, assert that we don't overflow any of two different offsets into the TB. Both unwind and goto_tb both record a uint16_t for later use. This fixes an arm-softmmu test case utilizing NEON in which there is a TB generated that runs to 7800 opcodes, and compiles to 96k on an x86_64 host. This overflows the 16-bit offset in which we record the goto_tb reset offset. Because of that overflow, we install a jump destination that goes to neverland. Boom. With this reduced op count, the same TB compiles to about 48k for aarch64, ppc64le, and x86_64 hosts, and neither assertion fires. Cc: qemu-stable@nongnu.org Reported-by: "Jason A. Donenfeld" <Jason@zx2c4.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Fix memory barrier encodingHenry Wertz2018-05-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | I found with qemu 2.11.x or newer that I would get an illegal instruction error running some Intel binaries on my ARM chromebook. On investigation, I found it was quitting on memory barriers. qemu instruction: mb $0x31 was translating as: 0x604050cc: 5bf07ff5 blpl #0x600250a8 After patch it gives: 0x604050cc: f57ff05b dmb ish In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be correct based on online docs, but due to some endian-related shenanigans it had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier for ARMv6) also should be byte swapped (and this patch does so). I have not checked for correctness of aarch64's barrier instruction. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Henry Wertz <hwertz10@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Support tlb offsets larger than 64kRichard Henderson2018-01-161-13/+17
| | | | | | AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Fix double-word comparisonsRichard Henderson2018-01-161-26/+60
| | | | | | | | | | | | The code sequence we were generating was only good for unsigned comparisons. For signed comparisions, use the sequence from gcc. Fixes booting of ppc64 firmware, with a patch changing the code sequence for ppc comparisons. Tested-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Fully convert tcg_target_op_defRichard Henderson2017-09-171-79/+107
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove tcg_regset_set32Richard Henderson2017-09-171-11/+12
| | | | | | | It's not even clear what the interface REG and VAL32 were supposed to mean. All uses had REG = 0 and VAL32 was the bitset assigned to the destination. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove tcg_regset_clearRichard Henderson2017-09-171-1/+1
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Use constant pool for callRichard Henderson2017-09-071-6/+3Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
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