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* tcg: Transition flat op_defs array to a target callbackRichard Henderson2017-01-101-2/+12
| | | | | | | | This will allow the target to tailor the constraints to the auto-detected ISA extensions. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add field extraction primitivesRichard Henderson2017-01-101-0/+4
| | | | | | | | Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of fixed position bitfields, much like we already have for deposit. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/sparc: Add support for fencePranith Kumar2016-09-161-0/+13
| | | | | | Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20160714202026.9727-10-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Support arbitrary size + alignmentRichard Henderson2016-09-161-5/+11
| | | | | | | | | | | Previously we allowed fully unaligned operations, but not operations that are aligned but with less alignment than the operation size. In addition, arm32, ia64, mips, and sparc had been omitted from the previous overalignment patch, which would have led to that alignment being enforced. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Clean up tcg-target.h header guardsMarkus Armbruster2016-07-121-2/+3
| | | | | | | | | | | | | These use guard symbols like TCG_TARGET_$target. scripts/clean-header-guards.pl doesn't like them because they don't match their file name (they should, to make guard collisions less likely). Clean them up: use guard symbol $target_TCG_TARGET_H for tcg/$target/tcg-target.h. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* tcg: Optimize spills of constantsRichard Henderson2016-07-061-0/+10
| | | | | | | | | | | While we can store constants via constrants on INDEX_op_st_i32 et al, we weren't able to spill constants to backing store. Add a new backend interface, tcg_out_sti, which may store the constant (and is allowed to fail). Rearrange the temp_* helpers so that we only attempt to directly store a constant when the temp is becoming dead/free. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Clean up direct block chaining data fieldsSergey Fedorov2016-05-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | Briefly describe in a comment how direct block chaining is done. It should help in understanding of the following data fields. Rename some fields in TranslationBlock and TCGContext structures to better reflect their purpose (dropping excessive 'tb_' prefix in TranslationBlock but keeping it in TCGContext): tb_next_offset => jmp_reset_offset tb_jmp_offset => jmp_insn_offset tb_next => jmp_target_addr jmp_next => jmp_list_next jmp_first => jmp_list_first Avoid using a magic constant as an invalid offset which is used to indicate that there's no n-th jump generated. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/sparc: Make direct jump patching thread-safeSergey Fedorov2016-05-131-1/+1
| | | | | | | | | | | Ensure direct jump patching in SPARC is atomic by using atomic_read()/atomic_set() for code patching. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <1461341333-19646-10-git-send-email-sergey.fedorov@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: check for CONFIG_DEBUG_TCG instead of NDEBUGAurelien Jarno2016-04-211-1/+1
| | | | | | | | | | Check for CONFIG_DEBUG_TCG instead of NDEBUG, drop now useless code. Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-id: 1461228530-14852-2-git-send-email-aurelien@aurel32.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tcg: use tcg_debug_assert instead of assert (fix performance regression)Aurelien Jarno2016-04-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TCG code is quite performance sensitive, but at the same time can also be quite tricky. That is why asserts that can be enabled with the --enable-debug-tcg configure option. This used to work the following way: | #include "config.h" | | ... | | #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG) | /* define it to suppress various consistency checks (faster) */ | #define NDEBUG | #endif | | ... | | #include <assert.h> Since commit 757e725b (tcg: Clean up includes) "config.h" as been replaced by "qemu/osdep.h" which itself includes <assert.h>. As a consequence the assertions are always enabled, even when using --disable-debug-tcg, causing a performance regression, especially on targets with many registers. For instance on qemu-system-ppc the speed difference is about 15%. tcg_debug_assert is controlled directly by CONFIG_DEBUG_TCG and already uses in some places. This patch replaces all the calls to assert into calss to tcg_debug_assert. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-id: 1461228530-14852-1-git-send-email-aurelien@aurel32.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tcg: Remove unnecessary osdep.h includes from tcg-target.inc.cPeter Maydell2016-02-231-1/+0Star
| | | | | | | | | | | | | | Commit 757e725b58c57d added a number of #include "qemu/osdep.h" files to the tcg-target.c files (as they were named at the time). These are unnecessary because these files are not standalone C files, and the tcg/tcg.c file which includes them will have already included osdep.h on their behalf. Remove the unneeded include directives. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1456238983-10160-4-git-send-email-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Rename tcg-target.c to tcg-target.inc.cPeter Maydell2016-02-231-0/+0
| | | | | | | | | | | Rename the per-architecture tcg-target.c files to tcg-target.inc.c. This makes it clearer that they are not intended to be standalone C files, but are instead #included into another source file. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1456238983-10160-2-git-send-email-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Clean up includesPeter Maydell2016-01-291-0/+1
| | | | | | | | | | Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-16-git-send-email-peter.maydell@linaro.org
* linux-user: remove useless macros GUEST_BASE and RESERVED_VALaurent Vivier2015-08-241-4/+4
| | | | | | | | | | | As we have removed CONFIG_USE_GUEST_BASE, we always use a guest base and the macros GUEST_BASE and RESERVED_VA become useless: replace them by their values. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1440420834-8388-1-git-send-email-laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net>
* linux-user: remove --enable-guest-base/--disable-guest-baseLaurent Vivier2015-08-241-4/+2Star
| | | | | | | | | | | | | | | | | | All tcg host architectures now support the guest base and as there is no real performance lost, it can be always enabled. Anyway, guest base use can be disabled lively by setting guest base to 0. CONFIG_USE_GUEST_BASE is defined as (USE_GUEST_BASE && USER_ONLY), it should have to be replaced by CONFIG_USER_ONLY in non CONFIG_USER_ONLY parts, but as some other parts are using !CONFIG_SOFTMMU I have chosen to use !CONFIG_SOFTMMU instead. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1440373328-9788-2-git-send-email-laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson2015-08-242-8/+9
| | | | | | | Rather than allow arbitrary shift+trunc, only concern ourselves with low and high parts. This is all that was being used anyway. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: implement real ext_i32_i64 and extu_i32_i64 opsAurelien Jarno2015-08-241-2/+6
| | | | | | | | | | | | | | Implement real ext_i32_i64 and extu_i32_i64 ops. They ensure that a 32-bit value is always converted to a 64-bit value and not propagated through the register allocator or the optimizer. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Stefan Weil <sw@weilnetz.de> Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: rename trunc_shr_i32 into trunc_shr_i64_i32Aurelien Jarno2015-08-242-3/+3
| | | | | | | | | | | The op is sometimes named trunc_shr_i32 and sometimes trunc_shr_i64_i32, and the name in the README doesn't match the name offered to the frontends. Always use the long name to make it clear it is a size changing op. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Mask TCGMemOp appropriately for indexingRichard Henderson2015-06-091-15/+15
| | | | | | | | | | The addition of MO_AMASK means that places that used inverted masks need to be changed to use positive masks, and places that failed to mask the intended bits need updating. Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Tested-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITSPaolo Bonzini2015-06-031-0/+1
| | | | | | | | | | | | This will be used to size the TLB when more than 8 MMU modes are used by the target. Limitations come from the limited size of the immediate fields (which sometimes, as in the case of Aarch64, extend to instructions that shift the immediate). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1424436345-37924-2-git-send-email-pbonzini@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* tcg: Push merged memop+mmu_idx parameter to softmmu routinesRichard Henderson2015-05-141-3/+3
| | | | | | | | The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Merge memop and mmu_idx parameters to qemu_ld/stRichard Henderson2015-05-141-5/+9
| | | | | | | | | At the tcg opcode level, not at the tcg-op.h generator level. This requires minor changes through all of the tcg backends, but none of the cpu translators. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Change generator-side labels to a pointerRichard Henderson2015-03-131-12/+10Star
| | | | | | | | | | | | | | | This is less about improved type checking than enabling a subsequent change to the representation of labels. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Tested-by: Claudio Fontana <claudio.fontana@huawei.com> Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Stefan Weil <sw@weilnetz.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use UMULXHI instructionRichard Henderson2014-09-292-1/+6
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Rename ADDX/SUBX insnsRichard Henderson2014-09-291-7/+7
| | | | | | | The pre-v9 ADDX/SUBX insns were renamed ADDC/SUBC for v9. Standardizing on the v9 name makes things less confusing. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use ADDXC in setcond_i64Richard Henderson2014-09-291-0/+17
| | | | | | Similar to the ADDC tricks we use in setcond_i32. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fix setcond_i32 uninitialized valueRichard Henderson2014-09-291-2/+5
| | | | | | We failed to swap c1 and c2 correctly for NE c2 == 0. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use ADDXC in addsub2_i64Richard Henderson2014-09-292-5/+29
| | | | | | | On T4 and newer Sparc chips we have an add-with-carry insn that takes its input from %xcc instead of %icc. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Support addsub2_i64Richard Henderson2014-09-292-9/+67
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove TCG_TARGET_HAS_new_ldstRichard Henderson2014-06-041-2/+0Star
| | | | | | | Since all backends have been converted, remove the compatibility code. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Make debug_frame constRichard Henderson2014-05-281-13/+9Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove unreachable code in tcg_out_op and op_defsRichard Henderson2014-05-121-18/+3Star
| | | | | | | | | | | The INDEX_op_call case has just been obsoleted; the mov and movi cases have not been reachable for years. Attempt to document this both in each tcg_out_op switch, and via TCG_OPF_NOT_PRESENT. Because of the TCG_OPF_NOT_PRESENT change, this must be done for all targets in a single commit. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Create tcg_out_callRichard Henderson2014-05-121-8/+14
| | | | | | Rename the existing tcg_out_calli to tcg_out_call_nodelay. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson2014-05-122-69/+60Star
| | | | | | | And use tcg pointer differencing functions as appropriate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Accept stores of zeroRichard Henderson2014-04-281-2/+2
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fix small 32-bit moviRichard Henderson2014-04-281-0/+5
| | | | | | We tested imm13 before discarding garbage high bits. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Fixup function argument typesRichard Henderson2014-04-281-66/+51Star
| | | | | | | | Use TCGReg everywhere appropriate. Use int32_t for all arguments that may be registers or immediate constants. Merge tcg_out_addi into its only caller. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Hoist common argument loads in tcg_out_opRichard Henderson2014-04-281-63/+60Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Don't handle mov/movi in tcg_out_opRichard Henderson2014-04-281-7/+6Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Tidy check_fit_* testsRichard Henderson2014-04-281-15/+20
| | | | | | | Use sextract instead of raw bit shifting for the tests. Introduce a new check_fit_ptr macro to make it clear we're looking at pointers. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Implement muls2_i32Richard Henderson2014-04-282-4/+16
| | | | | | | Using the 32-bit SMUL is a tad more efficient than resorting to extending and using the 64-bit MULX. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use the RETURN instructionRichard Henderson2014-04-281-4/+10
| | | | | | Saves one insn per TB exit over JMPL+RESTORE. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use 64-bit registers with sparcv8plusRichard Henderson2014-04-282-354/+185Star
| | | | | | | | Quite a lot of effort was spent composing and decomposing 64-bit quantities in registers, when we should just create them and leave them as one 64-bit register. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Support trunc_shr_i32Richard Henderson2014-04-282-1/+9
| | | | | | | Unlike a 64-bit shift op, allows the output to be in %l or %i registers for sparcv8plus. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Remove most uses of TCG_TARGET_REG_BITSRichard Henderson2014-04-281-33/+37
| | | | | | | Replace with SPARC64 define. Soon even sparcv8plus will use 64-bit register as far as TCG is concerned. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add INDEX_op_trunc_shr_i32Richard Henderson2014-04-281-0/+1
| | | | | | Let the backend do something special for truncation. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Use HOST_WORDS_BIGENDIANRichard Henderson2014-04-191-2/+0Star
| | | | | | Instead of rolling a local TCG_TARGET_WORDS_BIGENDIAN. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Use the type parameter to tcg_target_const_matchRichard Henderson2014-04-191-1/+7
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add TCGType parameter to tcg_target_const_matchRichard Henderson2014-04-191-1/+1
| | | | | | | | Most 64-bit targets need to be able to ignore the high bits of a TCG_TYPE_I32 value. Suggested-by: Stuart Brady <sdb@zubnet.me.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-sparc: Convert to new ldst opcodesRichard Henderson2014-03-172-100/+53Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
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