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* tcg/arm: Implement TCG_TARGET_HAS_rotv_vecRichard Henderson2021-06-041-1/+34
| | | | | | | Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement TCG_TARGET_HAS_roti_vecRichard Henderson2021-06-043-0/+17
| | | | | | | | Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec. For NEON, this is shift-right followed by shift-left-and-insert. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement TCG_TARGET_HAS_shv_vecRichard Henderson2021-06-042-1/+63
| | | | | | | | | | The three vector shift by vector operations are all implemented via expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec, as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the instruction stream, and therefore also do not appear in tcg_target_op_def. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement TCG_TARGET_HAS_bitsel_vecRichard Henderson2021-06-043-3/+22
| | | | | | | | | NEON has 3 instructions implementing this 4 argument operation, with each insn overlapping a different logical input onto the destination register. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement TCG_TARGET_HAS_minmax_vecRichard Henderson2021-06-042-1/+25
| | | | | | | This is minimum and maximum, signed and unsigned. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement TCG_TARGET_HAS_sat_vecRichard Henderson2021-06-042-1/+25
| | | | | | | This is saturating add and subtract, signed and unsigned. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement TCG_TARGET_HAS_mul_vecRichard Henderson2021-06-042-1/+7
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement TCG_TARGET_HAS_shi_vecRichard Henderson2021-06-042-1/+28
| | | | | | | This consists of the three immediate shifts: shli, shri, sari. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement andc, orc, abs, neg, not vector operationsRichard Henderson2021-06-043-5/+44
| | | | | | | | These logical and arithmetic operations are optional, but are trivial to accomplish with the existing infrastructure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement minimal vector operationsRichard Henderson2021-06-044-6/+202
| | | | | | | | Implementing dup2, add, sub, and, or, xor as the minimal set. This allows us to actually enable neon in the header file. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement tcg_out_dup*_vecRichard Henderson2021-06-041-8/+275
| | | | | | | | Most of dupi is copied from tcg/aarch64, which has the same encoding for AdvSimdExpandImm. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement tcg_out_mov for vector typesRichard Henderson2021-06-041-6/+46
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement tcg_out_ld/st for vector typesRichard Henderson2021-06-041-6/+64
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Add host vector frameworkRichard Henderson2021-06-045-24/+158
| | | | | | | | | | | Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Change parameters for tcg_target_const_matchRichard Henderson2021-06-0410-36/+12Star
| | | | | | | | | | | | Change the return value to bool, because that's what is should have been from the start. Pass the ct mask instead of the whole TCGArgConstraint, as that's the only part that's relevant. Change the value argument to int64_t. We will need the extra width for 32-bit hosts wanting to match vector constants. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* docs: fix references to docs/devel/atomics.rstStefano Garzarella2021-06-021-1/+1
| | | | | | | | | | | | | | | Commit 15e8699f00 ("atomics: convert to reStructuredText") converted docs/devel/atomics.txt to docs/devel/atomics.rst. We still have several references to the old file, so let's fix them with the following command: sed -i s/atomics.txt/atomics.rst/ $(git grep -l docs/devel/atomics.txt) Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210517151702.109066-3-sgarzare@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tcg/aarch64: Fix tcg_out_rotlYasuo Kuwahara2021-05-271-3/+2Star
| | | | | | | | | | | The last argument of tcg_out_extr() must be in the range 0-31 if ext==0. Before the fix, when m==0 it becomes 32 and it crashes with an Illegal instruction on Apple Silicon. After the fix, it will be 0. If m is in the range 1-31, it is the same as before. Signed-off-by: Yasuo Kuwahara <kwhr00@gmail.com> Message-Id: <CAHfJ0vSXnmnTLmT0kR=a8ACRdw_UsLYOhStzUzgVEHoH8U-7sA@mail.gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Do not include cpu.h if it's not really necessaryThomas Huth2021-05-023-3/+0Star
| | | | | | | | Stop including cpu.h in files that don't need it. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-4-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth2021-05-021-1/+0Star
| | | | | | | | Stop including sysemu/sysemu.h in files that don't need it. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-2-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* tcg/mips: Fix SoftTLB comparison on mips backendKele Huang2021-04-051-1/+1
| | | | | | | | | | | | | | | | The addrl used to compare with SoftTLB entry should be sign-extended in common case, and it will cause constant failing in SoftTLB comparisons for the addrl whose address is over 0x80000000 on the emulation of 32-bit guest on 64-bit host. This is an important performance bug fix. Spec2000 gzip rate increase from ~45 to ~140 on Loongson 3A4000 (MIPS compatible platform). Signed-off-by: Kele Huang <kele.hwang@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210401100457.191458-1-kele.hwang@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Workaround macOS 11.2 mprotect bugRichard Henderson2021-03-241-3/+7
| | | | | | | | | | | | | | | There's a change in mprotect() behaviour [1] in the latest macOS on M1 and it's not yet clear if it's going to be fixed by Apple. As a short-term fix, ignore failures setting up the guard pages. [1] https://gist.github.com/hikalium/75ae822466ee4da13cbbe486498a191f Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Buglink: https://bugs.launchpad.net/qemu/+bug/1914849 Message-Id: <20210320165720.1813545-3-richard.henderson@linaro.org>
* tcg: Do not set guard pages on the rx portion of code_gen_bufferRichard Henderson2021-03-241-7/+5Star
| | | | | | | | | | | The rw portion of the buffer is the only one in which overruns can be generated. Allow the rx portion to be more completely covered by huge pages. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20210320165720.1813545-2-richard.henderson@linaro.org>
* tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina2021-03-178-19/+31
| | | | | | | | | | | | | | | | | There are two different versions of prototype for tcg_out_op and tcg_out_vec_op functions: 1) using const TCGArg *args and const int *const_args arguments 2) using const TCGArg args[TCG_MAX_OP_ARGS] and const int const_args[TCG_MAX_OP_ARGS] aguments. This duality causes warnings on GCC 11 and prevents build using --enable-werror. As second version provides more information, unify functions prototypes to this variant. Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Message-Id: <20210312121418.139093-1-mrezanin@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_r[iI]Richard Henderson2021-03-171-15/+35
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_vRichard Henderson2021-03-171-4/+10
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm}Richard Henderson2021-03-171-17/+53
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrrrclRichard Henderson2021-03-171-8/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrrrRichard Henderson2021-03-171-6/+15
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrrrrrRichard Henderson2021-03-171-8/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrclRichard Henderson2021-03-171-6/+15
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrrbbRichard Henderson2021-03-171-7/+16
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrrrrcRichard Henderson2021-03-171-9/+21
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrrcRichard Henderson2021-03-171-6/+15
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrrRichard Henderson2021-03-171-5/+14
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrRichard Henderson2021-03-171-13/+23
| | | | | | | At the same time, validate the type argument in tcg_out_mov. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_pRichard Henderson2021-03-171-6/+12
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_lRichard Henderson2021-03-171-3/+11
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tcg_out_op_rrsRichard Henderson2021-03-171-43/+37Star
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Push opcode emit into each caseRichard Henderson2021-03-171-3/+32
| | | | | | | | | We're about to split out bytecode output into helpers, but we can't do that one at a time if tcg_out_op_t is being done outside of the switch. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Implement the disassembler properlyRichard Henderson2021-03-171-0/+283
| | | | | | | | | Actually print arguments as opposed to simply the opcodes and, uselessly, the argument counts. Reuse all of the helpers developed as part of the interpreter. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove tci_disasRichard Henderson2021-03-172-12/+0Star
| | | | | | | | This function is unused. It's not even the disassembler, which is print_insn_tci, located in disas/tci.c. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Hoist op_size checking into tci_args_*Richard Henderson2021-03-171-14/+73
| | | | | | | | | This performs the size check while reading the arguments, which means that we don't have to arrange for it to be done after the operation. Which tidies all of the branches. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm}Richard Henderson2021-03-171-66/+81
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bitsRichard Henderson2021-03-172-6/+6
| | | | | | | | | We are currently using the "natural" size routine, which uses 64-bits on a 64-bit host. The TCGMemOpIdx operand has 11 bits, so we can safely reduce to 32-bits. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Clean up deposit operationsRichard Henderson2021-03-173-28/+30
| | | | | | | | | | | | Use the correct set of asserts during code generation. We do not require the first input to overlap the output; the existing interpreter already supported that. Split out tci_args_rrrbb in the translator. Use the deposit32/64 functions rather than inline expansion. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrrrRichard Henderson2021-03-171-5/+11
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out tci_args_rrrrrrRichard Henderson2021-03-171-11/+20
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Reuse tci_args_l for goto_tbRichard Henderson2021-03-173-23/+9Star
| | | | | | | | | Convert to indirect jumps, as it's less complicated. Then we just have a pointer to the tb address at which the chain is stored, from which we read. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Reuse tci_args_l for exit_tbRichard Henderson2021-03-172-10/+5Star
| | | | | | | | | | Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label != NULL has to be removed because that is a valid value for exit_tb. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Reuse tci_args_l for calls.Richard Henderson2021-03-171-19/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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