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* tcg/i386: Hoist common arguments in tcg_out_opRichard Henderson2017-01-101-102/+95Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/i386: Fuly convert tcg_target_op_defRichard Henderson2017-01-101-142/+198
| | | | | | | Use a switch instead of searching a table. Share constraints between 32-bit and 64-bit, when at all possible. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Handle clz opcodeRichard Henderson2017-01-102-2/+36
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/mips: Handle clz opcodeRichard Henderson2017-01-102-2/+51
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/arm: Handle ctz and clz opcodesRichard Henderson2017-01-102-2/+29
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/aarch64: Handle ctz and clz opcodesRichard Henderson2017-01-102-4/+52
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/ppc: Handle ctz and clz opcodesRichard Henderson2017-01-102-4/+73
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add clz and ctz opcodesRichard Henderson2017-01-1016-0/+246
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Allow an operand to be matching or a constantRichard Henderson2017-01-102-35/+41
| | | | | | | | This allows an output operand to match an input operand only when the input operand needs a register. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Pass the opcode width to target_parse_constraintRichard Henderson2017-01-1010-85/+53Star
| | | | | | | | | | | | This will let us choose how to interpret a given constraint depending on whether the opcode is 32- or 64-bit. Which will let us share more constraint combinations between opcodes. At the same time, change the interface to return the advanced pointer instead of passing it in/out by reference. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Transition flat op_defs array to a target callbackRichard Henderson2017-01-1011-77/+136
| | | | | | | | This will allow the target to tailor the constraints to the auto-detected ISA extensions. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add markup for output requires new registerRichard Henderson2017-01-102-12/+23
| | | | | | | | This is the same concept as, and same markup as, the early clobber markup in gcc. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/optimize: Fold movcond 0/1 into setcondRichard Henderson2017-01-101-0/+15
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Support deposit into zeroRichard Henderson2017-01-101-4/+26
| | | | | | | Since we can no longer use matching constraints, this does mean we must handle that data movement by hand. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Implement field extraction opcodesRichard Henderson2017-01-102-2/+13
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Expose host facilities to tcg-target.hRichard Henderson2017-01-102-104/+96Star
| | | | | | | This lets us expose facilities to TCG_TARGET_HAS_* defines directly, rather than hiding behind function calls. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/ppc: Implement field extraction opcodesRichard Henderson2017-01-102-2/+12
| | | | | Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/mips: Implement field extraction opcodesRichard Henderson2017-01-102-1/+12
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/i386: Implement field extraction opcodesRichard Henderson2017-01-102-3/+47
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/arm: Implement field extraction opcodesRichard Henderson2017-01-102-2/+26
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/arm: Move isa detection to tcg-target.hRichard Henderson2017-01-102-44/+33Star
| | | | | | | | This allows us to use this detection within the TCG_TARGET_HAS_* macros, instead of requiring a function call into tcg-target.inc.c. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/aarch64: Implement field extraction opcodesRichard Henderson2017-01-102-4/+18
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add deposit_z expanderRichard Henderson2017-01-102-0/+149
| | | | | | | While we don't require a new opcode, it is handy to have an expander that knows the first source is zero. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Minor adjustments to deposit expandersRichard Henderson2017-01-101-2/+4
| | | | | | | | | | Assert that len is not 0. Since we have asserted that ofs + len <= N, a later check for len == N implies that ofs == 0. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add field extraction primitivesRichard Henderson2017-01-1015-2/+426
| | | | | | | | Adds tcg_gen_extract_* and tcg_gen_sextract_* for extraction of fixed position bitfields, much like we already have for deposit. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-mips: Adjust qemu_ld/st for mips64Jin Guojie2017-01-061-57/+146
| | | | | | | | | Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-11-git-send-email-jinguojie@loongson.cn>
* tcg-mips: Adjust calling conventions for mips64Jin Guojie2017-01-062-10/+30
| | | | | | | | | Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-10-git-send-email-jinguojie@loongson.cn>
* tcg-mips: Add tcg unwind infoJin Guojie2017-01-061-0/+44
| | | | | | | | | Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-9-git-send-email-jinguojie@loongson.cn>
* tcg-mips: Adjust prologue for mips64Jin Guojie2017-01-061-29/+25Star
| | | | | | | | | | | Take stack frame parameters out from the function body. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-8-git-send-email-jinguojie@loongson.cn>
* tcg-mips: Adjust load/store functions for mips64Jin Guojie2017-01-061-3/+11
| | | | | | | | | | | | | tcg_out_ldst: using a generic ALIAS_PADD to avoid ifdefs tcg_out_ld: generates LD or LW tcg_out_st: generates SD or SW Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-7-git-send-email-jinguojie@loongson.cn>
* tcg-mips: Adjust move functions for mips64Jin Guojie2017-01-061-9/+25
| | | | | | | | | | | | tcg_out_mov: using OPC_OR as most mips assemblers do; tcg_out_movi: extended to 64-bit immediate. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-6-git-send-email-jinguojie@loongson.cn>
* tcg-mips: Add bswap32u and bswap64Jin Guojie2017-01-061-3/+99
| | | | | | | | | | | | | | | | Without the mips32r2 instructions to perform swapping, bswap is quite large, dominating the size of each reverse-endian qemu_ld/qemu_st operation. Create two subroutines in the prologue block. The subroutines require extra reserved registers (TCG_TMP[2, 3]). Using these within qemu_ld means that we need not place additional restrictions on the qemu_ld outputs. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-5-git-send-email-jinguojie@loongson.cn>
* tcg-mips: Support 64-bit opcodesJin Guojie2017-01-062-10/+353
| | | | | | | | | | | | Bulk patch adding 64-bit opcodes into tcg_out_op. Note that mips64 is as yet neither complete nor enabled. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-4-git-send-email-jinguojie@loongson.cn>
* tcg-mips: Add mips64 opcodesJin Guojie2017-01-061-75/+118
| | | | | | | | | | | | | Since the mips manual tables are in octal, reorg all of the opcodes into that format for clarity. Note that the 64-bit opcodes are as yet unused. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-3-git-send-email-jinguojie@loongson.cn>
* tcg-mips: Move bswap code to a subroutineJin Guojie2017-01-062-70/+139
| | | | | | | | | | | | | | | | Without the mips32r2 instructions to perform swapping, bswap is quite large, dominating the size of each reverse-endian qemu_ld/qemu_st operation. Create a subroutine in the prologue block. The subroutine requires extra reserved registers (TCG_TMP[2, 3]). Using these within qemu_ld means that we need not place additional restrictions on the qemu_ld outputs. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-2-git-send-email-jinguojie@loongson.cn>
* tcg/s390: Remove 'R' constraintRichard Henderson2016-12-241-15/+10Star
| | | | | | Since R0 is reserved, we don't need a special case constraint. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/s390: Fix setcond expansionRichard Henderson2016-12-241-20/+30
| | | | | | | | We can't use LOAD AND TEST for unsigned data and then expect to extract the result with ADD LOGICAL WITH CARRY. Fall through to using COMPARE LOGICAL IMMEDIATE instead. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: correct 32-bit tcg_gen_ld8s_i64 sign-extensionJoseph Myers2016-11-011-1/+1
| | | | | | | | | | | | | | | | The version of tcg_gen_ld8s_i64 for 32-bit systems does a load into the low part of the return value - then attempts a sign extension into the high part, but wrongly sets the high part to a sign extension of itself rather than of the low part. This results in TCG internal errors from the use of the uninitialized high part (in some GCC tests of AArch64 NEON shift intrinsics, in particular). This patch corrects the sign-extension logic, making it match other functions such as tcg_gen_ld16s_i64. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Joseph Myers <joseph@codesourcery.com> Message-Id: <alpine.DEB.2.20.1610272333560.22353@digraph.polyomino.org.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/tcg.h: Improve documentation of TCGv_i32 etc typesPeter Maydell2016-11-011-8/+30
| | | | | | | | | | | | The typedefs we use for the TCGv_i32, TCGv_i64 and TCGv_ptr types are somewhat confusing, because we define them as pointers to structs, but the structs themselves are never defined. Explain in the comments a bit more clearly why this is OK and what is going on under the hood. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1477067922-26202-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add tcg_gen_mulsu2_{i32,i64,tl}Richard Henderson2016-11-012-0/+47
| | | | | | | | This multiply has one signed input and one unsigned input, producing the full double-width result. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1475011433-24456-2-git-send-email-rth@twiddle.net>
* log: Add locking to large logging blocksRichard Henderson2016-11-011-0/+8
| | | | | | | | | | | | | | | | Reuse the existing locking provided by stdio to keep in_asm, cpu, op, op_opt, op_ind, and out_asm as contiguous blocks. While it isn't possible to interleave e.g. in_asm or op_opt logs because of the TB lock protecting all code generation, it is possible to interleave cpu logs, or to interleave a cpu dump with an out_asm dump. For mingw32, we appear to have no viable solution for this. The locking functions are not properly exported from the system runtime library. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: comment on which functions have to be called with tb_lock heldPaolo Bonzini2016-10-311-0/+2
| | | | | | | | | | | | | | | | | | | softmmu requires more functions to be thread-safe, because translation blocks can be invalidated from e.g. notdirty callbacks. Probably the same holds for user-mode emulation, it's just that no one has ever tried to produce a coherent locking there. This patch will guide the introduction of more tb_lock and tb_unlock calls for system emulation. Note that after this patch some (most) of the mentioned functions are still called outside tb_lock/tb_unlock. The next one will rectify this. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20161027151030.20863-7-alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Emit barriers with parallel_cpusRichard Henderson2016-10-261-11/+1Star
| | | | | | Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add CONFIG_ATOMIC64Richard Henderson2016-10-263-13/+70
| | | | | | | | | | | | Allow qemu to build on 32-bit hosts without 64-bit atomic ops. Even if we only allow 32-bit hosts to multi-thread emulate 32-bit guests, we still need some way to handle the 32-bit guest using a 64-bit atomic operation. Do so by dropping back to single-step. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add atomic128 helpersRichard Henderson2016-10-261-1/+23
| | | | | | | | | | | | | | | Force the use of cmpxchg16b on x86_64. Wikipedia suggests that only very old AMD64 (circa 2004) did not have this instruction. Further, it's required by Windows 8 so no new cpus will ever omit it. If we truely care about these, then we could check this at startup time and then avoid executing paths that use it. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add atomic helpersRichard Henderson2016-10-264-0/+500
| | | | | | | | | | Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add EXCP_ATOMICRichard Henderson2016-10-261-0/+1
| | | | | | | | | | When we cannot emulate an atomic operation within a parallel context, this exception allows us to stop the world and try again in a serial context. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: try sti when moving a constant into a dead memory tempPaolo Bonzini2016-10-241-29/+27Star
| | | | | | | | | | | | | | | | | | This comes from free from unifying tcg_reg_alloc_mov and tcg_reg_alloc_movi's handling of TEMP_VAL_CONST. It triggers often on moves to cc_dst, such as the following translation of "sub $0x3c,%esp": before: after: subl $0x3c,%ebp subl $0x3c,%ebp movl %ebp,0x10(%r14) movl %ebp,0x10(%r14) movl $0x3c,%ebx movl $0x3c,0x2c(%r14) movl %ebx,0x2c(%r14) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1473945360-13663-1-git-send-email-pbonzini@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* qemu-tech: move text from qemu-tech to tcg/READMEPaolo Bonzini2016-10-071-0/+5
| | | | | Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg/optimize: move default return out of if statementAlex Bennée2016-10-041-2/+1Star
| | | | | | | | | | | This is to appease sanitizer builds which complain that: "error: control reaches end of non-void function" Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20160930213106.20186-5-alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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