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* tcg/mips: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-56/+46Star
| | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-14/+13Star
| | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/ppc: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-58/+46Star
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-43/+33Star
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-023-56/+41Star
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Split out target constraints to tcg-target-con-str.hRichard Henderson2021-02-024-74/+62Star
| | | | | | | | | | This eliminates the target-specific function target_parse_constraint and folds it into the single caller, process_op_defs. Since this is done directly into the switch statement, duplicates are compilation errors rather than silently ignored at runtime. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Tidy register constraint definitionsRichard Henderson2021-02-021-20/+20
| | | | | | | | | | | | | Create symbolic constants for all low-byte-addressable and second-byte-addressable registers. Create a symbol for the registers that need reserving for softmmu. There is no functional change for 's', as this letter is only used for i386. The BYTEL name is correct for the action we wish from the constraint. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Move constraint type check to tcg_target_const_matchRichard Henderson2021-02-021-11/+17
| | | | | | | | | Rather than check the type when filling in the constraint, check it when matching the constant. This removes the only use of the type argument to target_parse_constraint. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Remove TCG_TARGET_HAS_* ifdefsRichard Henderson2021-02-021-82/+0Star
| | | | | | | The opcodes always exist, regardless of whether or not they are enabled. Remove the unnecessary ifdefs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Drop L and S constraintsRichard Henderson2021-02-021-6/+4Star
| | | | | | | These are identical to the 'r' constraint. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Restrict tci_write_reg16() to 64-bit hostsPhilippe Mathieu-Daudé2021-01-271-0/+2
| | | | | | | | | | | | | | | | Restrict tci_write_reg16() to 64-bit hosts to fix on 32-bit ones: [520/1115] Compiling C object libqemu-arm-linux-user.fa.p/tcg_tci.c.o FAILED: libqemu-arm-linux-user.fa.p/tcg_tci.c.o tcg/tci.c:132:1: error: 'tci_write_reg16' defined but not used [-Werror=unused-function] tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value) ^~~~~~~~~~~~~~~ Fixes: 2f160e0f979 ("tci: Add implementation for INDEX_op_ld16u_i64") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-Id: <20210123094107.2340222-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* tcg: Restart code generation when we run out of tempsRichard Henderson2021-01-241-3/+8
| | | | | | | | | | | | Some large translation blocks can generate so many unique constants that we run out of temps to hold them. In this case, longjmp back to the start of code generation and restart with a smaller translation block. Buglink: https://bugs.launchpad.net/bugs/1912065 Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Toggle page execution for Apple SiliconRoman Bolshakov2021-01-231-0/+1
| | | | | | | | | | | | | | | Pages can't be both write and executable at the same time on Apple Silicon. macOS provides public API to switch write protection [1] for JIT applications, like TCG. 1. https://developer.apple.com/documentation/apple_silicon/porting_just-in-time_compilers_to_apple_silicon Tested-by: Alexander Graf <agraf@csgraf.de> Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20210113032806.18220-1-r.bolshakov@yadro.com> [rth: Inline the qemu_thread_jit_* functions; drop the MAP_JIT change for a follow-on patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/aarch64: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-5/+5
| | | | | | | | Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to "t1 = -v2, t2 = c - v2". This avoids a serial dependency between t1 and t2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/ppc: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-17/+27
| | | | | | | | Improve expand_vec_shi to use sign-extraction for MO_32. This allows a single VSPLTISB instruction to load all of the valid shift constants. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove tcg_gen_dup{8,16,32,64}i_vecRichard Henderson2021-01-131-20/+0Star
| | | | | | | | These interfaces have been replaced by tcg_gen_dupi_vec and tcg_constant_vec. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/i386: Use tcg_constant_vec with tcg vec expandersRichard Henderson2021-01-131-13/+13
| | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add tcg_reg_alloc_dup2Richard Henderson2021-01-131-0/+97
| | | | | | | There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove movi and dupi opcodesRichard Henderson2021-01-1312-42/+1Star
| | | | | | | | | These are now completely covered by mov from a TYPE_CONST temporary. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tci: Add special tci_movi_{i32,i64} opcodesRichard Henderson2021-01-132-4/+4
| | | | | | | | The normal movi opcodes are going away. We need something for TCI to use internally. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use tcg_constant_{i32,i64,vec} with gvec expandersRichard Henderson2021-01-132-77/+58Star
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use tcg_constant_{i32,i64} with tcg int expandersRichard Henderson2021-01-131-120/+107Star
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert tcg_gen_dupi_vec to TCG_CONSTRichard Henderson2021-01-133-40/+15Star
| | | | | | | | Because we now store uint64_t in TCGTemp, we can now always store the full 64-bit duplicate immediate. So remove the difference between 32- and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Use tcg_constant_internal with constant foldingRichard Henderson2021-01-131-59/+49Star
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Adjust TempOptInfo allocationRichard Henderson2021-01-131-26/+34
| | | | | | | | | | | | Do not allocate a large block for indexing. Instead, allocate for each temporary as they are seen. In general, this will use less memory, if we consider that most TBs do not touch every target register. This also allows us to allocate TempOptInfo for new temps created during optimization. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Improve find_better_copyRichard Henderson2021-01-131-15/+12Star
| | | | | | Prefer TEMP_CONST over anything else. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Introduce TYPE_CONST temporariesRichard Henderson2021-01-132-49/+188
| | | | | | | | | These will hold a single constant for the duration of the TB. They are hashed, so that each value has one temp across the TB. Not used yet, this is all infrastructure. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Expand TempOptInfo to 64-bitsRichard Henderson2021-01-131-19/+21
| | | | | | | This propagates the extended value of TCGTemp.val that we did before. In addition, it will be required for vector constants. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Rename struct tcg_temp_info to TempOptInfoRichard Henderson2021-01-131-16/+16
| | | | | | | | Fix this name vs our coding style. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Expand TCGTemp.val to 64-bitsRichard Henderson2021-01-131-1/+1
| | | | | | | This will reduce the differences between 32-bit and 64-bit hosts, allowing full 64-bit constants to be created with the same interface. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add temp_readonlyRichard Henderson2021-01-131-11/+10Star
| | | | | | | | | In most, but not all, places that we check for TEMP_FIXED, we are really testing that we do not modify the temporary. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Consolidate 3 bits into enum TCGTempKindRichard Henderson2021-01-132-54/+80
| | | | | | | | | The temp_fixed, temp_global, temp_local bits are all related. Combine them into a single enumeration. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Increase tcg_out_dupi_vec immediate to int64_tRichard Henderson2021-01-134-33/+69
| | | | | | | | | | | | While we don't store more than tcg_target_long in TCGTemp, we shouldn't be limited to that for code generation. We will be able to use this for INDEX_op_dup2_vec with 2 constants. Also pass along the minimal vece that may be said to apply to the constant. This allows some simplification in the various backends. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use tcg_out_dupi_vec from temp_loadRichard Henderson2021-01-134-34/+46
| | | | | | | Having dupi pass though movi is confusing and arguably wrong. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Constify TCGLabelQemuLdst.raddrRichard Henderson2021-01-078-15/+8Star
| | | | | | | | | Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Constify tcg_code_gen_epilogueRichard Henderson2021-01-079-17/+9Star
| | | | | | | | | Now that all native tcg hosts support splitwx, make this pointer const. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_TARGET_SUPPORT_MIRRORRichard Henderson2021-01-079-9/+0Star
| | | | | | | | Now that all native tcg hosts support splitwx, remove the define. Replace the one use with a test for CONFIG_TCG_INTERPRETER. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Support split-wx code generationRichard Henderson2021-01-072-17/+22
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/mips: Support split-wx code generationRichard Henderson2021-01-072-20/+25
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/mips: Do not assert on relocation overflowRichard Henderson2021-01-071-34/+19Star
| | | | | | | | | This target was not updated with 7ecd02a06f8, and so did not allow re-compilation with relocation overflow. Remove reloc_26 and reloc_26_val as unused. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/riscv: Support split-wx code generationRichard Henderson2021-01-072-19/+24
| | | | | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/riscv: Remove branch-over-branch fallbackRichard Henderson2021-01-071-50/+6Star
| | | | | | | | | Since 7ecd02a06f8, we are prepared to re-start code generation with a smaller TB if a relocation is out of range. We no longer need to leave a nop in the stream Just In Case. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/riscv: Fix branch range checksRichard Henderson2021-01-071-13/+15
| | | | | | | | | | | | The offset even checks were folded into the range check incorrectly. By offsetting by 1, and not decrementing the width, we silently allowed out of range branches. Assert that the offset is always even instead. Move tcg_out_goto down into the CONFIG_SOFTMMU block so that it is not unused. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/s390: Support split-wx code generationRichard Henderson2021-01-072-40/+31Star
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/s390: Use tcg_tbrel_diffRichard Henderson2021-01-071-8/+8
| | | | | | | Use tcg_tbrel_diff when we need a displacement to a label, and with a NULL argument when we need the normalizing addend. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/sparc: Support split-wx code generationRichard Henderson2021-01-072-12/+14
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/sparc: Use tcg_tbrel_diffRichard Henderson2021-01-071-8/+7Star
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/ppc: Support split-wx code generationRichard Henderson2021-01-072-24/+31
| | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TBRichard Henderson2021-01-071-3/+2Star
| | | | | | | | The maximum TB code gen size is UINT16_MAX, which the current code does not support. Use our utility function to optimally add an arbitrary constant. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/ppc: Use tcg_tbrel_diffRichard Henderson2021-01-071-3/+3
| | | | | | | Use tcg_tbrel_diff when we need a displacement to a label, and with a NULL argument when we need the normalizing addend. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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