summaryrefslogtreecommitdiffstats
path: root/tci.c
Commit message (Collapse)AuthorAgeFilesLines
* tcg: Mask TCGMemOp appropriately for indexingRichard Henderson2015-06-091-4/+4
| | | | | | | | | | The addition of MO_AMASK means that places that used inverted masks need to be changed to use positive masks, and places that failed to mask the intended bits need updating. Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Tested-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Push merged memop+mmu_idx parameter to softmmu routinesRichard Henderson2015-05-141-15/+14Star
| | | | | | | | The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Merge memop and mmu_idx parameters to qemu_ld/stRichard Henderson2015-05-141-10/+10
| | | | | | | | | At the tcg opcode level, not at the tcg-op.h generator level. This requires minor changes through all of the tcg backends, but none of the cpu translators. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Remove unused opcodesRichard Henderson2015-02-131-13/+0Star
| | | | | | | | We no longer need INDEX_op_end to terminate the list, nor do we need 5 forms of nop, since we just remove the TCGOp instead. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* Merge remote-tracking branch 'remotes/bonzini/softmmu-smap' into stagingPeter Maydell2014-06-051-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/bonzini/softmmu-smap: (33 commits) target-i386: cleanup x86_cpu_get_phys_page_debug target-i386: fix protection bits in the TLB for SMEP target-i386: support long addresses for 4MB pages (PSE-36) target-i386: raise page fault for reserved bits in large pages target-i386: unify reserved bits and NX bit check target-i386: simplify pte/vaddr calculation target-i386: raise page fault for reserved physical address bits target-i386: test reserved PS bit on PML4Es target-i386: set correct error code for reserved bit access target-i386: introduce support for 1 GB pages target-i386: introduce do_check_protect label target-i386: tweak handling of PG_NX_MASK target-i386: commonize checks for PAE and non-PAE target-i386: commonize checks for 4MB and 4KB pages target-i386: commonize checks for 2MB and 4KB pages target-i386: fix coding standards in x86_cpu_handle_mmu_fault target-i386: simplify SMAP handling in MMU_KSMAP_IDX target-i386: fix kernel accesses with SMAP and CPL = 3 target-i386: move check_io helpers to seg_helper.c target-i386: rename KSMAP to KNOSMAP ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-051-0/+1
| | | | | | | | | | | | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | tci: Convert to new ldst opcodesRichard Henderson2014-06-041-146/+176
|/ | | | | Tested-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tci: Mask shift counts to avoid undefined behaviorRichard Henderson2014-04-191-10/+10
| | | | | | | TCG now requires unspecified behavior rather than a potential crash, bring the C shift within the letter of the law. Signed-off-by: Richard Henderson <rth@twiddle.net>
* misc: Use new rotate functionsStefan Weil2013-09-251-4/+4
| | | | Signed-off-by: Stefan Weil <sw@weilnetz.de>
* tci: Add implementation of rotl_i64, rotr_i64Stefan Weil2013-09-251-1/+9
| | | | | | | | It is used by qemu-ppc64 when running Debian's busybox-static. Cc: qemu-stable <qemu-stable@nongnu.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* tci: Fix qemu-alpha on 32 bit hosts (wrong assertions)Stefan Weil2013-09-201-12/+0Star
| | | | | | | | | | | | | | | | Debian busybox-static for alpha has a load address of 0x0000000120000000 which is mapped to 0x0000000020000000 for 32 bit hosts. qemu-alpha uses the TCG opcodes qemu_ld32, qemu_ld64, qemu_st32 and qemu_st64 which all raise the assertion (taddr == host_addr). Remove all assertions of this type because they are either wrong or unnecessary (when sizeof(tcg_target_ulong) >= sizeof(target_ulong)). Cc: qemu-stable <qemu-stable@nongnu.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg: Change tcg_qemu_tb_exec return to uintptr_tRichard Henderson2013-09-021-2/+2
| | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tci: Make tcg temporaries local to tcg_qemu_tb_execRichard Henderson2013-04-111-0/+6
| | | | | | | | | | We're moving away from the temporaries stored in env. Make sure we can differentiate between temp stores and possibly bogus stores for extra call arguments. Move TCG_AREG0 and TCG_REG_CALL_STACK out of the way of the parameter passing registers. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off by: Stefan Weil <sw@weilnetz.de>
* tci: Avoid code before declarationsRichard Henderson2013-04-111-3/+4
| | | | | | | This only valid with c99 extensions enabled, and easy to avoid. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off by: Stefan Weil <sw@weilnetz.de>
* tci: Use a local variable for envRichard Henderson2013-04-111-7/+1Star
| | | | | | | | | Since we have total conversion away from global AREG0, we do not need a global variable named "env". Retain that name as the function parameter inside the interpreter. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off by: Stefan Weil <sw@weilnetz.de>
* tci: Use 32-bit signed offsets to loads/storesRichard Henderson2013-04-111-14/+22
| | | | | | | | Since the change to tcg_exit_req, the first insn of every TB is a load with a negative offset from env. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off by: Stefan Weil <sw@weilnetz.de>
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tci: Fix type of tci_read_labelRichard Henderson2012-11-241-2/+2
| | | | | | | | | | | Fixes the pointer truncation that was occurring for branches. Cc: Stefan Weil <sw@weilnetz.de> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Stefan Weil <sw@weilnetz.de> Tested-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tci: Support deposit operationsStefan Weil2012-11-181-0/+22
| | | | | | | | The operations for INDEX_op_deposit_i32 and INDEX_op_deposit_i64 are now supported and enabled by default. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: remove obsolete jmp opAurelien Jarno2012-10-061-1/+0Star
| | | | | | | | | | | | | The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* tci: Fix for AREG0 free modeStefan Weil2012-09-271-4/+9
| | | | | | | | | | | | Support for helper functions with 5 arguments was missing in the code generator and in the interpreter. There is no need to pass the constant TCG_AREG0 from the code generator to the interpreter. Remove that code for the INDEX_op_qemu_st* opcodes. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl2012-09-151-12/+0Star
| | | | | | | | | | | | | Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets, remove dead code and support for !CONFIG_TCG_PASS_AREG0 case. Remove dyngen-exec.h and all references to it. Although included by hw/spapr_hcall.c, it does not seem to use it. Remove unused HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* tci: Support INDEX_op_bswap64_i64Stefan Weil2012-06-221-1/+0Star
| | | | | | | | Running the Windows 7 (64 bit) boot process needs INDEX_op_bswap64_i64. It was already implemented, but untested. Remove the TODO() statement. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* tci: Fix wrong macro name for debug codeStefan Weil2012-05-081-1/+1
| | | | | | | | | | | | | Code which is compiled with CONFIG_TCG_DEBUG (set by configure option --enable-debug-tcg) should not disable the assert macro by defining NDEBUG. With the wrong macro name CONFIG_TCG_DEBUG, all assertions in tci.c were completely useless because NDEBUG was always defined. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* tci: GETPC() macro must return an uintptr_tStefan Weil2012-04-211-2/+2
| | | | | | | | | | | | Change the data type of tci_tb_ptr, so GETPC() returns an uintptr_t now (like for all other TCG targets). This completes commit 2050396801ca0c8359364d61eaadece951006057 and fixes builds with TCI. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tci: Support targets with CONFIG_TCG_PASS_AREG0 (fix broken build)Stefan Weil2012-04-071-12/+23
| | | | | | | | | | | | | Builds with --enable-tcg-interpreter failed because more and more targets (currently alpha and sparc) replaced the global env in AREG0 by function parameters. Convert the TCG interpreter to use the new helper functions and add defines for those targets which still use AREG0. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* w64: Fix data type of next_tb and tcg_qemu_tb_execStefan Weil2012-03-171-2/+2
| | | | | | | | | | | | | | | | | | | next_tb is the numeric value of a tcg target (= QEMU host) address. Using tcg_target_ulong instead of unsigned long shows this and makes the code portable for hosts with an unusual size of long (w64). The type cast '(long)(next_tb & ~3)' was not needed (casting unsigned long to long does not change the bits, and nor does casting long to pointer for most (= all non w64) hosts. It is removed here. Macro or function tcg_qemu_tb_exec is used to set next_tb. The function also returns next_tb. Therefore tcg_qemu_tb_exec must return a tcg_target_ulong. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Rename CPUState -> CPUArchStateAndreas Färber2012-03-141-2/+2
| | | | | | | | | | | | | Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
* tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson2011-11-141-19/+19
| | | | | | | | | Most targets did not name the enum; tci used TCGRegister. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* tcg: Add interpreter for bytecodeStefan Weil2011-10-311-0/+1208
Signed-off-by: Stefan Weil <sw@weilnetz.de>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 20:25:37 +0100