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* target/arm: Fix mte page crossing testRichard Henderson2021-06-162-1/+32
| | | | | | | | | | | | | | The test was off-by-one, because tag_last points to the last byte of the tag to check, thus tag_last - prev_page will equal TARGET_PAGE_SIZE when we use the first byte of the next page. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/403 Reported-by: Peter Collingbourne <pcc@google.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210612195707.840217-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* test/tcg/aarch64: Add mte-5Richard Henderson2021-04-302-1/+45
| | | | | | | | Buglink: https://bugs.launchpad.net/bugs/1921948 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416183106.1516563-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* accel/tcg: Preserve PAGE_ANON when changing page permissionsRichard Henderson2021-04-123-2/+46
| | | | | | | | | | | | | Using mprotect() to change PROT_* does not change the MAP_ANON previously set with mmap(). Our linux-user version of MTE only works with MAP_ANON pages, so losing PAGE_ANON caused MTE to stop working. Reported-by: Stephen Long <steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* semihosting: move semihosting tests to multiarchAlex Bennée2021-03-242-18/+18
| | | | | | | | | | | | | It may be arm-compat-semihosting but more than one architecture uses it so lets move the tests into the multiarch area. We gate it on the feature and split the semicall.h header between the arches. Also clean-up a bit of the Makefile messing about to one common set of runners. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323165308.15244-6-alex.bennee@linaro.org>
* tests/tcg/aarch64: Add mte smoke testsRichard Henderson2021-02-166-0/+235
| | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210212184902.1251044-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Use the proper TBI settings for linux-userRichard Henderson2021-02-161-1/+0Star
| | | | | | | | | | | | | | We were fudging TBI1 enabled to speed up the generated code. Now that we've improved the code generation, remove this. Also, tidy the comment to reflect the current code. The pauth test was testing a kernel address (-1) and making incorrect assumptions about TBI1; stick to userland addresses. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210212184902.1251044-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée2021-01-181-0/+11
| | | | | | | | | | | | | | | | | | While GDB can work with any XML description given to it there is special handling for SVE registers on the GDB side which makes the users life a little better. The changes aren't that major and all the registers save the $vg reported the same. All that changes is: - report org.gnu.gdb.aarch64.sve - use gdb nomenclature for names and types - minor re-ordering of the types to match reference - re-enable ieee_half (as we know gdb supports it now) - $vg is now a 64 bit int - check $vN and $zN aliasing in test Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Machado <luis.machado@linaro.org> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org>
* gdbstub: implement a softmmu based testAlex Bennée2021-01-182-0/+2
| | | | | | | | | | | | | | | | | This adds a new tests that allows us to test softmmu only features including watchpoints. To do achieve this we need to: - add _exit: labels to the boot codes - write a memory.py test case - plumb the test case into the build system - tweak the run_test script to: - re-direct output when asked - use socket based connection for all tests - add a small pause before connection Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-6-alex.bennee@linaro.org>
* tests/tcg/aarch64: Add bti smoke testsRichard Henderson2020-10-274-0/+239
| | | | | | | | | | | The note test requires gcc 10 for -mbranch-protection=standard. The mmap test uses PROT_BTI and does not require special compiler support. Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201021173749.111103-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Fix AddPAC error indicationRichard Henderson2020-08-032-1/+34
| | | | | | | | | | | | | | | | | | | | | The definition of top_bit used in this function is one higher than that used in the Arm ARM psuedo-code, which put the error indication at top_bit - 1 at the wrong place, which meant that it wasn't visible to Auth. Fixing the definition of top_bit requires more changes, because its most common use is for the count of bits in top_bit:bot_bit, which would then need to be computed as top_bit - bot_bit + 1. For now, prefer the minimal fix to the error indication alone. Fixes: 63ff0ca94cb Reported-by: Derrick McKee <derrick.mckee@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200728195706.11087-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added comment about the divergence from the pseudocode] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tests/tcg: ensure -cpu max also used for plugin runAlex Bennée2020-06-161-1/+2
| | | | | | | | | | | The check-tcg plugins build was failing because some special case tests that needed -cpu max failed because the plugin variant hadn't carried across the QEMU_OPTS tweak. Guests which globally set QEMU_OPTS=-cpu FOO where unaffected. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200615141922.18829-3-alex.bennee@linaro.org>
* tests/tcg: build plugin list from contents of src directoryAlex Bennée2020-06-161-1/+1
| | | | | | | | | If you jump back and forth between branches while developing plugins you end up debugging failures caused by plugins left in the build directory. Fix this by basing plugins on the source tree instead. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200615141922.18829-2-alex.bennee@linaro.org>
* tests/tcg: fix invocation of the memory record/replay testsAlex Bennée2020-05-271-1/+1
| | | | | | | | | | I'm not sure when this broke but we should use EXTRA_RUNS for "virtual" tests which are not generated from the binary names. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200520140541.30256-5-alex.bennee@linaro.org>
* tests/tcg: add a multiarch linux-user gdb testAlex Bennée2020-05-061-3/+2Star
| | | | | | | | | | When the gdbstub code was converted to the new API we missed a few snafus in the various guests. Add a simple gdb test script which can be used on all our linux-user guests to check for obvious failures. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200430190122.4592-9-alex.bennee@linaro.org>
* tests/tcg: drop inferior.was_attached() testAlex Bennée2020-05-062-6/+0Star
| | | | | | | | | | This test seems flaky and reports attachment even when we failed to negotiate the architecture. However the fetching of the guest architecture will fail tripping up the gdb AttributeError which will trigger our early no error status exit from the test Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200430190122.4592-5-alex.bennee@linaro.org>
* tests/tcg: better trap gdb failuresAlex Bennée2020-05-062-2/+0Star
| | | | | | | | | | | | | It seems older and non-multiarach aware GDBs might not fail gracefully when faced with something they don't know. For example when faced with a target XML for s390x the Ubuntu 18.04 gdb will generate an internal fault and prompt for a core dump. Work around this by invoking GDB in a more batch orientated way and then trying to filter out between test failures and gdb failures. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200430190122.4592-4-alex.bennee@linaro.org>
* tests/tcg/aarch64: add test-sve-ioctl guest-debug testAlex Bennée2020-03-172-2/+94
| | | | | | | | | This test exercises the gdbstub while runing the sve-iotcl test. I haven't plubmed it into make system as we need a way of verifying if gdb has the right support for SVE. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200316172155.971-26-alex.bennee@linaro.org>
* tests/tcg/aarch64: add SVE iotcl testAlex Bennée2020-03-172-0/+74
| | | | | | | | | | | | | This is a fairly bare-bones test of setting the various vector sizes for SVE which will only fail if the PR_SVE_SET_VL can't reduce the user-space vector length by powers of 2. However we will also be able to use it in a future test which exercises the GDB stub. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200316172155.971-25-alex.bennee@linaro.org>
* tests/tcg/aarch64: add a gdbstub testcase for SVE registersAlex Bennée2020-03-172-0/+99
| | | | | | | | | | A very simple test case which sets and reads SVE registers while running a test case. We don't really need to compile a SVE binary for this case but we will later so keep it simple for now. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200316172155.971-24-alex.bennee@linaro.org>
* tests/tcg/aarch64: userspace system register testAlex Bennée2020-03-172-0/+178
| | | | | | | | | | This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. We need a SVE aware compiler as we are testing the id_aa64zfr0_el1 register in the set. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200316172155.971-21-alex.bennee@linaro.org>
* tests/tcg/aarch64: Add newline in pauth-1 printfRichard Henderson2020-03-051-1/+1
| | | | | | | | | | Make the output just a bit prettier when running by hand. Cc: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tests/tcg: take into account expected clashes pauth-4Alex Bennée2020-02-251-17/+37
| | | | | | | | | | | Pointer authentication isn't perfect so measure the percentage of failed checks. As we want to vary the pointer we work through a bunch of different addresses. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Robert Foley <robert.foley@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200225124710.14152-20-alex.bennee@linaro.org>
* tests/tcg: include a skip runner for pauth3 with pluginsAlex Bennée2020-02-251-0/+2
| | | | | | | | | If we have plugins enabled we still need to have built the test to be able to run it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Robert Foley <robert.foley@linaro.org> Message-Id: <20200225124710.14152-2-alex.bennee@linaro.org>
* tests/tcg: gate pauth-% tests on having compiler supportAlex Bennée2020-02-042-3/+11
| | | | | | | | | Otherwise we end up failing to build our tests on CI which may have older compilers that the user expects. We can get rid of this once we can fallback to multiarch containers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200203090932.19147-14-alex.bennee@linaro.org>
* tests/tcg/aarch64: Add pauth-4Richard Henderson2020-01-232-1/+26
| | | | | | | | | | Perform the set of operations and test described in LP 1859713. Suggested-by: Adrien GRASSEIN <adrien.grassein@smile.fr> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200116230809.19078-5-richard.henderson@linaro.org [PMM: fixed hard-coded tabs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tests/tcg/aarch64: Add pauth-3Richard Henderson2020-01-232-1/+44
| | | | | | | | | This is the test vector from the QARMA paper, run through PACGA. Suggested-by: Vincent Dehors <vincent.dehors@smile.fr> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200116230809.19078-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tests/tcg/aarch64: Fix compilation parameters for pauth-%Richard Henderson2020-01-233-4/+1Star
| | | | | | | | | | | | | | | | We were incorrectly requiring ARMv8.4 support for the pauth tests, but Pointer Authentication is an ARMv8.3 extension. Further, hiding the required architecture within asm() is not correct. Correct the architecture version requested, and specify it in the cflags of the (cross-) compiler rather than in the asm. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200116230809.19078-3-richard.henderson@linaro.org [PMM: tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tests/tcg: add user version of dumb-as-bricks semiconsole testAlex Bennée2020-01-091-0/+7
| | | | | | | | There are linux-user users of semihosting so we'd better check things work for them as well. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg: add a dumb-as-bricks semihosting console testAlex Bennée2020-01-092-1/+48
| | | | | | | | | We don't run this during check-tcg as we would need to check stuff is echoed back. However we can still build the binary so people can test it manually. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg: enable plugin testingAlex Bennée2019-10-281-0/+6
| | | | | | | | | | | | | | | | If CONFIG_PLUGINS is enabled then lets enable testing for all our TCG targets. This is a simple smoke test that ensure we don't crash or otherwise barf out by running each plugin against each test. There is a minor knock on effect for additional runners which need specialised QEMU_OPTS which will also need to declare a plugin version of the runner. If this gets onerous we might need to add another helper. Checking the results of the plugins is left for a later exercise. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg: move "virtual" tests to EXTRA_TESTSAlex Bennée2019-10-281-1/+1
| | | | | | | Otherwise clever expanders like the plugins test get unstuck. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* Merge remote-tracking branch ↵Peter Maydell2019-09-301-0/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20190927' into staging target-arm queue: * Fix the CBAR register implementation for Cortex-A53, Cortex-A57, Cortex-A72 * Fix direct booting of Linux kernels on emulated CPUs which have an AArch32 EL3 (incorrect NSACR settings meant they could not access the FPU) * semihosting cleanup: do more work at translate time and less work at runtime # gpg: Signature made Fri 27 Sep 2019 15:32:43 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190927: hw/arm/boot: Use the IEC binary prefix definitions hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots tests/tcg: add linux-user semihosting smoke test for ARM target/arm: remove run-time semihosting checks for linux-user target/arm: remove run time semihosting checks target/arm: handle A-profile semihosting at translate time target/arm: handle M-profile semihosting at translate time tests/tcg: clean-up some comments after the de-tangling target/arm: fix CBAR register for AArch64 CPUs Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # tests/tcg/arm/Makefile.target
| * tests/tcg: add linux-user semihosting smoke test for ARMAlex Bennée2019-09-271-0/+5
| | | | | | | | | | | | | | | | | | | | We already use semihosting for the system stuff so this is a simple smoke test to ensure we are working OK on linux-user. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190913151845.12582-7-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tests/tcg: clean-up some comments after the de-tanglingAlex Bennée2019-09-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | These were missed in the recent de-tangling so have been updated to be more actuate. I've also built up ARM_TESTS in a manner similar to AARCH64_TESTS for better consistency. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190913151845.12582-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | tests/tcg: add simple record/replay smoke test for aarch64Alex Bennée2019-09-261-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds two new tests that re-use the memory test to check basic record replay functionality is still working. We have to define our own runners rather than using the default pattern as we want to change the test name but re-use the memory binary. We declare the test binaries as PHONY as they don't really exist. [AJB: A better test would output some sort of timer value or other otherwise variable value so we could compare the record and replay outputs and ensure they match] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Pavel Dovgalyuk <dovgaluk@ispras.ru>
* | tests/tcg: add generic version of float_convsAlex Bennée2019-09-261-0/+748
| | | | | | | | | | | | | | | | | | | | | | This is broadly similar to the existing fcvt test for ARM but using the generic float testing framework. We should be able to pare down the ARM fcvt test case to purely half-precision with or without the Alt HP provision. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* | tests/tcg: add float_madds test to multiarchAlex Bennée2019-09-261-0/+768
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a generic floating point multiply and accumulate test for single precision floating point values. I've split of the common float functions into a helper library so additional tests can use the same common code. As I don't have references for all architectures I've allowed some flexibility for tests to pass without reference files. They can be added as we get collect them. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* | tests/tcg: clean-up some comments after the de-tanglingAlex Bennée2019-09-261-1/+2
|/ | | | | | | | | | | These were missed in the recent de-tangling so have been updated to be more actuate. I've also built up ARM_TESTS in a manner similar to AARCH64_TESTS for better consistency. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* tests/tcg: move configuration to a sub-shell scriptPaolo Bonzini2019-09-101-8/+0Star
| | | | | | | | | | | | | | | | | | | | Avoid the repeated inclusions of config-target.mak, which have risks of namespace pollution, and instead build minimal configuration files in a configuration script. The same configuration files can also be included in Makefile and Makefile.qemu [AJB 10/09/19] In the original PR this had inadvertently enabled tests for ppc64abi32. However as the rest of the multiarch tests work rather than disabling the otherwise correctly functioning build I've just skipped the failing linux-test test. For some reason I can't debug it with TCG so I'm leaving that to the PPC maintainers to look at. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-4-pbonzini@redhat.com> [AJB: s/docker/container/, rm last bits from configure, ppc6432abi hack] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <rth@twiddle.net>
* tests/tcg: cleanup Makefile inclusionsPaolo Bonzini2019-09-101-5/+7
| | | | | | | | | | | | | | | | | | | | | Rename Makefile.probe to Makefile.prereqs and make it actually define rules for the tests. Rename Makefile to Makefile.target, since it is not a toplevel makefile. Rename Makefile.include to Makefile.qemu and disentangle it from the QEMU Makefile.target, so that it is invoked recursively by tests/Makefile.include. Tests are now placed in tests/tcg/$(TARGET). Drop the usage of TARGET_BASE_ARCH, which is ignored by everything except x86_64 and aarch64. Fix x86 tests by using -cpu max and, while at it, standardize on QEMU_OPTS for aarch64 tests too. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-3-pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg: use EXTRA_CFLAGS everywherePaolo Bonzini2019-09-101-2/+2
| | | | | | | | | | | For i386 specifically, this allows using the host GCC to compile the i386 tests. But, it should really be done for all targets, unless we want to pass $(EXTRA_CFLAGS) directly as part of $(CC). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-2-pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* target/arm: Fix output of PAuth AuthRichard Henderson2019-06-132-1/+62
| | | | | | | | | | | | | The ARM pseudocode installs the error_code into the original pointer, not the encrypted pointer. The difference applies within the 7 bits of pac data; the result should be the sign extension of bit 55. Add a testcase to that effect. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tests/tcg/multiarch: expand system memory test to cover moreAlex Bennée2019-05-281-0/+2
| | | | | | | | | | | | | | Expand the memory test to cover move of the softmmu code. Specifically we: - improve commentary - add some helpers (for later BE support) - reduce boiler plate into helpers - add signed reads at various sizes/offsets - required -DCHECK_UNALIGNED Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg/aarch64: add system boot.SAlex Bennée2019-05-283-0/+295
| | | | | | | | | | This provides the bootstrap and low level helper functions for an aarch64 kernel. We use semihosting to handle test output and exiting the emulation. semihosting's parameter passing is a little funky so we end up using the stack and pointing to that as the parameter block. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg/arm: account for pauth randomnessAlex Bennée2019-03-121-6/+20
| | | | | | | | | Pointer authentication isn't guaranteed to always detect a clash between different keys. Take this into account in the test by running several times and checking the percentage hit rate of the test. Cc: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* docker: add debian-buster-arm64-crossAlex Bennée2019-02-081-1/+1
| | | | | | | We can't build QEMU with this but we can use this image to build newer arm64 testcases which need more up to date tools. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg/aarch64: Add pauth smoke testRichard Henderson2019-02-052-1/+28
| | | | | | | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190201195404.30486-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tests/tcg: add run, diff, and skip helper macrosAlex Bennée2018-06-201-4/+2Star
| | | | | | | | | | | As we aren't using the default runners for all the test cases it is easy to miss out things like timeouts. To help with this we add some helpers and use them so we only need to make core changes in one place. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* tests/tcg/arm: add fcvt test cases for AArch32/64Alex Bennée2018-06-202-0/+3287
| | | | | | | | | | This runs through the usual float to float conversions and crucially also runs with ARM Alternative Half Precision Format. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* tests/tcg: enable building for AArch64Alex Bennée2018-06-201-0/+8
We only have compilers for the (default) little endian variants. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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