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* target/openrisc: Rename the cpu from or32 to or1kRichard Henderson2017-02-131-2/+2
| | | | | | This is in keeping with the toolchain and or1ksim. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-openrisc: Correct carry flag check of l.addc and l.addic test casesSebastian Macke2013-11-202-7/+11
| | | | | | | | The test cases did not correctly test for the carry flag. Signed-off-by: Sebastian Macke <sebastian@macke.de> Reviewed-by: Jia Liu <proljc@gmail.com> Signed-off-by: Jia Liu <proljc@gmail.com>
* target-or32: Add testcasesJia Liu2012-07-2752-0/+2579
Add testcases for OpenRISC. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>