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* tests/docker: move our arm64 cross compile to BusterAlex Bennée2019-09-101-1/+1
| | | | | | | | | Now Buster is released we can unify our cross build images for both QEMU and tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* tests/tcg: add .gitignore for in source buildsAlex Bennée2019-09-101-0/+5
| | | | | | | This hides the new build artefacts from the re-organised TCG tests when you are doing an in-source build. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg: move configuration to a sub-shell scriptPaolo Bonzini2019-09-1019-145/+269
| | | | | | | | | | | | | | | | | | | | Avoid the repeated inclusions of config-target.mak, which have risks of namespace pollution, and instead build minimal configuration files in a configuration script. The same configuration files can also be included in Makefile and Makefile.qemu [AJB 10/09/19] In the original PR this had inadvertently enabled tests for ppc64abi32. However as the rest of the multiarch tests work rather than disabling the otherwise correctly functioning build I've just skipped the failing linux-test test. For some reason I can't debug it with TCG so I'm leaving that to the PPC maintainers to look at. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-4-pbonzini@redhat.com> [AJB: s/docker/container/, rm last bits from configure, ppc6432abi hack] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <rth@twiddle.net>
* tests/tcg: cleanup Makefile inclusionsPaolo Bonzini2019-09-109-60/+86
| | | | | | | | | | | | | | | | | | | | | Rename Makefile.probe to Makefile.prereqs and make it actually define rules for the tests. Rename Makefile to Makefile.target, since it is not a toplevel makefile. Rename Makefile.include to Makefile.qemu and disentangle it from the QEMU Makefile.target, so that it is invoked recursively by tests/Makefile.include. Tests are now placed in tests/tcg/$(TARGET). Drop the usage of TARGET_BASE_ARCH, which is ignored by everything except x86_64 and aarch64. Fix x86 tests by using -cpu max and, while at it, standardize on QEMU_OPTS for aarch64 tests too. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-3-pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg: use EXTRA_CFLAGS everywherePaolo Bonzini2019-09-106-10/+10
| | | | | | | | | | | For i386 specifically, this allows using the host GCC to compile the i386 tests. But, it should really be done for all targets, unless we want to pass $(EXTRA_CFLAGS) directly as part of $(CC). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-2-pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/docker: fix "cc" command to work with podmanAlex Bennée2019-09-101-1/+1
| | | | | | | | | | Podman requires a little bit of additional magic to the uid mapping which was already done for the normal RunCommand. We simplify the logic by pushing it directly into the Docker::run method to avoid instantiating an extra Docker() object and ensure the CC command always runs as the current user. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* target/mips: tests/tcg: Fix target configurations for MSA testsAleksandar Markovic2019-08-198-2028/+2576
| | | | | | | | | | | | At this moment, the only MIPS CPUs that are emulated in QEMU and support MSA extension are R5600 (mips32r5), and I6400/I6500 (mips64r6). Therefore, mips32r5 and mips64r6 are the only ISAs that could support MSA in QEMU. This means mips32r6 currently do not make much sense, and mips32r5 support for MSA tests is needed, which is done by this patch. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-38-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: tests/tcg: Add optional printing of more detailed failure infoAleksandar Markovic2019-08-191-1/+22
| | | | | | | | | | | There is a need for printing input and output data for failure cases, for debugging purpose. This is achieved by this patch, and only if a preprocessor constant is manually set to 1. (Assumption is that the need for such printout is relatively rare.) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-37-git-send-email-aleksandar.markovic@rt-rk.com>
* tests/tcg: fix diff-out pass to properly report failureAlex Bennée2019-07-101-1/+5
| | | | | | | | A side effect of piping the output to head is squash the exit status of the diff command. Fix this by only doing the pipe if the diff failed and then ensuring the status is non-zero. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg: fix up test-i386-fprem.ref generationAlex Bennée2019-07-101-2/+2
| | | | | | | | | | | We never shipped the reference data in the source tree because it's quite big (64M). As a result the only option is to generate it locally. Although we have a rule to generate the reference file we missed the dependency and location changes, probably because it's only run for SLOW test runs. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/tests: target/mips: Correct MSA test compilation and execution orderAleksandar Markovic2019-07-028-48/+48
| | | | | | | | | Correct MSA test compilation and execution order, for the sake of consistence. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1562068213-11307-4-git-send-email-aleksandar.markovic@rt-rk.com>
* tcg/tests: target/mips: Amend MSA integer multiply testsAleksandar Markovic2019-07-028-891/+891
| | | | | | | | | | Amend MSA fixed point multiply tests: correct output values for MADDV.B, MADDV.H, MADDV.W, MADDV.D, MSUBV.B, MSUBV.H, MSUBV.W and MSUBD.D. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1562068213-11307-3-git-send-email-aleksandar.markovic@rt-rk.com>
* tcg/tests: target/mips: Amend MSA fixed point multiply testsAleksandar Markovic2019-07-0217-0/+1840
| | | | | | | | | Amend MSA fixed point multiply tests: add tests for MADD_Q.H, MADD_Q.W, MADDR_Q.H, MADDR_Q.W, MSUB_Q.H, MSUB_Q.W, MSUBR_Q.H and MSUBR_Q.W. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1562068213-11307-2-git-send-email-aleksandar.markovic@rt-rk.com>
* Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190701' into stagingPeter Maydell2019-07-021-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - cleanup/refactoring in the cpu feature code - fix for a tcg test case - halt/clear support for vfio-ccw, and use a new helper # gpg: Signature made Mon 01 Jul 2019 12:08:41 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190701: s390x: add cpu feature/model files to KVM section vfio-ccw: support async command subregion vfio-ccw: use vfio_set_irq_signaling s390x/cpumodel: Prepend KDSA features with "KDSA" s390x/cpumodel: Rework CPU feature definition tests/tcg/s390x: Fix alignment of csst parameter list Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Merge tag 's390x-tcg-2019-06-21' into s390-next-stagingCornelia Huck2019-06-241-1/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One fix for a tcg test case and two cleanups/refactorings of cpu feature definitions. # gpg: Signature made Fri 21 Jun 2019 03:37:37 PM CEST # gpg: using RSA key 1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A # gpg: issuer "david@redhat.com" # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [full] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] * tag 's390x-tcg-2019-06-21': s390x/cpumodel: Prepend KDSA features with "KDSA" s390x/cpumodel: Rework CPU feature definition tests/tcg/s390x: Fix alignment of csst parameter list Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| | * tests/tcg/s390x: Fix alignment of csst parameter listRichard Henderson2019-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parameter list given in general register 1 shall be aligned on a quadword boundary. This test currently succeeds or fails depending on the compiler version used and the accidential layout of the function's stack frame. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
* | | tests/tcg: target/mips: Fix some test cases for pack MSA instructionsAleksandar Markovic2019-06-2612-384/+384
| | | | | | | | | | | | | | | | | | | | | | | | Fix certian test cases for MSA pack instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-8-git-send-email-aleksandar.markovic@rt-rk.com>
* | | tests/tcg: target/mips: Add support for MSA MIPS32R6 testingsAleksandar Markovic2019-06-264-0/+1980
| | | | | | | | | | | | | | | | | | | | | | | | Add files for MSA MIPS32R6 target testings (copiling and running). Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-7-git-send-email-aleksandar.markovic@rt-rk.com>
* | | tests/tcg: target/mips: Add support for MSA big-endian target testingsAleksandar Markovic2019-06-265-633/+1631
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add files for MSA big-endian target testings (copiling and running). Little-endian files are renamed and ammended too. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-6-git-send-email-aleksandar.markovic@rt-rk.com>
* | | tests/tcg: target/mips: Amend tests for MSA int multiply instructionsAleksandar Markovic2019-06-2610-0/+1744
| | | | | | | | | | | | | | | | | | | | | | | | Amend tests for MSA int multiply instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-5-git-send-email-aleksandar.markovic@rt-rk.com>
* | | tests/tcg: target/mips: Amend tests for MSA int dot product instructionsAleksandar Markovic2019-06-2615-0/+2644
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add tests for instructions whose result depends on the value in destination register (prior to instruction execution). Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-4-git-send-email-aleksandar.markovic@rt-rk.com>
* | | tests/tcg: target/mips: Add tests for MSA move instructionsAleksandar Markovic2019-06-264-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | Add tests for MSA move instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-3-git-send-email-aleksandar.markovic@rt-rk.com>
* | | tests/tcg: target/mips: Add tests for MSA bit move instructionsAleksandar Markovic2019-06-2614-4/+2415
|/ / | | | | | | | | | | | | | | Add tests for MSA bit move instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-2-git-send-email-aleksandar.markovic@rt-rk.com>
* | tests/tcg: target/mips: Amend tests for MSA pack instructionsAleksandar Markovic2019-06-2113-12/+708
| | | | | | | | | | | | | | | | | | Add tests for cases when destination register is the same as one of source registers. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561031359-6727-3-git-send-email-aleksandar.markovic@rt-rk.com>
* | tests/tcg: target/mips: Include isa/ase and group name in test outputAleksandar Markovic2019-06-21260-736/+1492
|/ | | | | | | | | | | | | | | | For better appearance and usefullnes, include ISA/ASE name and instruction group name in the output of tests. For example, all this data will be displayed for FMAX_A.W test: | MSA | Float Max Min | FMAX_A.W | | PASS: 80 | FAIL: 0 | elapsed time: 0.16 ms | (the data will be displayed in one row; they are presented here in two rows not to exceed the width of the commit message) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561031359-6727-2-git-send-email-aleksandar.markovic@rt-rk.com>
* target/arm: Fix output of PAuth AuthRichard Henderson2019-06-132-1/+62
| | | | | | | | | | | | | The ARM pseudocode installs the error_code into the original pointer, not the encrypted pointer. The difference applies within the 7 bits of pac data; the result should be the sign extension of bit 55. Add a testcase to that effect. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tests/tcg/x86_64: add a PVH crt.o for x86_64 system testsAlex Bennée2019-06-123-0/+311
| | | | | | | Instead of doing the full real to 64 bit dance we are attempting to leverage Xen's PVH boot spec to go from 32 bit to 64 bit. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg: clean-up VPATH/TESTS for i386Alex Bennée2019-06-121-7/+2Star
| | | | | | | | Since we only run build the multiarch tests and we use a fully resolved path for the crt object we don't need the wildcard or VPATH messing about. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg: better detect truncated readsAlex Bennée2019-06-121-5/+31
| | | | | | | | | If we've truncated a wider read we can detect the condition earlier by looking at the number of zeros we've read. So we don't trip up on cases where we have written zeros to the start of the buffer we also ensure we only start each offset read from the right address. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg: target/mips: Add README for MSA testsAleksandar Markovic2019-06-073-0/+904
| | | | | | | | | Add README for MSA tests. This is just to explain how to run tests even without Makefile. Makefile will be provided later on. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-11-git-send-email-aleksandar.markovic@rt-rk.com>
* tests/tcg: target/mips: Add tests for MSA FP max/min instructionsAleksandar Markovic2019-06-078-0/+1240
| | | | | | | | | | | | | | | | | | Add tests for MSA FP max/min instructions. This includes following instructions: * FMAX.W - float maximum (words) * FMAX.D - float maximum (doublewords) * FMAX_A.W - float maximum absolute (words) * FMAX_A.D - float maximum absolute (doublewords) * FMIN.W - float minimum (words) * FMIN.D - float minimum (doublewords) * FMIN_A.W - float minimum absolute (words) * FMIN_A.D - float minimum absolute (doublewords) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-10-git-send-email-aleksandar.markovic@rt-rk.com>
* tests/tcg: target/mips: Add utility function reset_msa_registers()Aleksandar Markovic2019-06-07227-4/+504
| | | | | | | | | | | | Add function reset_msa_registers() and utilize it in each MSA test. This is needed to ensure independency of test results on the state of MSA registers before test execution. This also allows for correction of tests for VSHF* instructions, that are now independent on the previous state of MSA registers. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-9-git-send-email-aleksandar.markovic@rt-rk.com>
* tests/tcg: target/mips: Move four tests to a better locationAleksandar Markovic2019-06-074-0/+0
| | | | | | | | | | Move tests for <MUL|MULR>_Q.<H|B> from "integer multiply" directory to "fixed-point multiply" directory, since they do not operate on integers, but on fixed point numbers. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-8-git-send-email-aleksandar.markovic@rt-rk.com>
* tests/tcg: target/mips: Add tests for MSA shift instructionsAleksandar Markovic2019-06-0720-0/+3060
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add tests for MSA shift instructions. This includes following instructions: * SLL.B - shift left logical (bytes) * SLL.H - shift left logical (halfwords) * SLL.W - shift left logical (words) * SLL.D - shift left logical (doublewords) * SRA.B - shift right arithmetic (bytes) * SRA.H - shift right arithmetic (halfwords) * SRA.W - shift right arithmetic (words) * SRA.D - shift right arithmetic (doublewords) * SRAR.B - shift right arithmetic rounded (bytes) * SRAR.H - shift right arithmetic rounded (halfwords) * SRAR.W - shift right arithmetic rounded (words) * SRAR.D - shift right arithmetic rounded (doublewords) * SRL.B - shift right logical (bytes) * SRL.H - shift right logical (halfwords) * SRL.W - shift right logical (words) * SRL.D - shift right logical (doublewords) * SRLR.B - shift right logical rounded (bytes) * SRLR.H - shift right logical rounded (halfwords) * SRLR.W - shift right logical rounded (words) * SRLR.D - shift right logical rounded (doublewords) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-7-git-send-email-aleksandar.markovic@rt-rk.com>
* tests/tcg: target/mips: Amend and rearrange MSA wrappersAleksandar Markovic2019-06-071-160/+300
| | | | | | | | | Amend and rearrange MSA wrappers to follow the same organization as in MSA tests. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-6-git-send-email-aleksandar.markovic@rt-rk.com>
* tests/tcg: target/mips: Add tests for MSA bit set instructionsAleksandar Markovic2019-06-0112-0/+1836
| | | | | | | | | | | | | | | | | | | | | | Add tests for MSA bit set instructions. This includes following instructions: * BCLR.B - clear bit (bytes) * BCLR.H - clear bit (halfwords) * BCLR.W - clear bit (words) * BCLR.D - clear bit (doublewords) * BNEG.B - negate bit (bytes) * BNEG.H - negate bit (halfwords) * BNEG.W - negate bit (words) * BNEG.D - negate bit (doublewords) * BSET.B - set bit (bytes) * BSET.H - set bit (halfwords) * BSET.W - set bit (words) * BSET.D - set bit (doublewords) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1555699081-24577-5-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Amend and cleanup MSA TCG testsAleksandar Markovic2019-06-01155-240/+4211
| | | | | | | | | | | | | Add missing bits and peaces of the tests of the emulation of certain MSA (non-immediate variants): some tests were missing two last cases; some instructions were missing wrappers; some test included wrong headers; some tests were missing altogether; updated some copywright preambles; do several other minor cleanups. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1555699081-24577-4-git-send-email-aleksandar.markovic@rt-rk.com>
* tests: Fix up docker cross builds for ppc64 (BE) targetsDavid Gibson2019-05-291-0/+3
| | | | | | | | We currently have docker cross building targets for powerpc (32-bit, BE) and ppc64el (64-bit, LE), but not for pcp64 (64-bit, BE). This is an irritating gap in make check-tcg coverage so correct it. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* tests/tcg/alpha: add system boot.SRichard Henderson2019-05-283-0/+575
| | | | | | | | | | This provides the bootstrap and low level helper functions for an alpha kernel. We use direct access to the DP264 serial port for test output, and hard machine halt to exit the emulation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190501184306.15208-1-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg/multiarch: expand system memory test to cover moreAlex Bennée2019-05-283-72/+282
| | | | | | | | | | | | | | Expand the memory test to cover move of the softmmu code. Specifically we: - improve commentary - add some helpers (for later BE support) - reduce boiler plate into helpers - add signed reads at various sizes/offsets - required -DCHECK_UNALIGNED Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg/minilib: support %c format charAlex Bennée2019-05-281-0/+3
| | | | | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg/multiarch: move the system memory testAlex Bennée2019-05-281-0/+0
| | | | | | | | | There is nothing inherently architecture specific about the memory test although we may have to manage different restrictions of unaligned access across architectures. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg/aarch64: add system boot.SAlex Bennée2019-05-283-0/+295
| | | | | | | | | | This provides the bootstrap and low level helper functions for an aarch64 kernel. We use semihosting to handle test output and exiting the emulation. semihosting's parameter passing is a little funky so we end up using the stack and pointing to that as the parameter block. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg/multiarch: add hello world system testAlex Bennée2019-05-282-1/+1
| | | | | | | | This is not really i386 only, we can have the same test for all architectures supporting system tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg/multiarch: add support for multiarch system testsAlex Bennée2019-05-282-0/+15
| | | | | | | | | | We can certainly support some common tests for system emulation that make use of our minimal defined boot.S support. It will still be up to individual architectures to ensure they build so we provide a MULTIARCH_TESTS variable that they can tack onto TESTS themselves. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/xtensa: implement exclusive access optionMax Filippov2019-05-151-0/+48
| | | | | | | | | | | The Exclusive Instructions provide a general-purpose mechanism for atomic updates of memory-based synchronization variables that can be used for exclusion algorithms. Use cmpxchg-based implementation that is sufficient for the typical use of exclusive access in atomic operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* tests/tcg/xtensa: clean up test setMax Filippov2019-03-233-167/+1Star
| | | | | | | | | | | Drop test_fail: we know that exit simcall works. Now that it's not run automatically there's no point in keeping it. Drop test_pipeline: we're not modeling pipeline, we don't control ccount and there's no plan to do so. Enable test_boolean: it won't break on cores without boolean option, it will do testing on cores with boolean option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* target/xtensa: fix break_dependency for repeated resourcesMax Filippov2019-03-221-0/+17
| | | | | | | | | | | | | | | | break_dependency incorrectly handles the case of dependency on an opcode that references the same register multiple times. E.g. the following instruction is translated incorrectly: { or a2, a3, a3 ; or a3, a2, a2 } This happens because resource indices of both dependency graph nodes are incremented, and a copy for the second instance of the same register in the ending node is not done. Only increment resource index of the ending node of the dependency. Add test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
* tests/tcg/arm: account for pauth randomnessAlex Bennée2019-03-121-6/+20
| | | | | | | | | Pointer authentication isn't guaranteed to always detect a clash between different keys. Take this into account in the test by running several times and checking the percentage hit rate of the test. Cc: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* tests/tcg/i386: add memory test to exercise softmmuAlex Bennée2019-03-121-0/+243
| | | | | | | This is a simple test to check various access patterns to memory including unaligned access. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
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