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* target/i386: fix cmpxchg with 32-bit register destinationPaolo Bonzini2022-11-152-0/+43
| | | | | | | | | | | | | | | | | | | | | Unlike the memory case, where "the destination operand receives a write cycle without regard to the result of the comparison", rm must not be touched altogether if the write fails, including not zero-extending it on 64-bit processors. This is not how the movcond currently works, because it is always followed by a gen_op_mov_reg_v to rm. To fix it, introduce a new function that is similar to gen_op_mov_reg_v but writes to a TCG temporary. Considering that gen_extu(ot, oldv) is not needed in the memory case either, the two cases for register and memory destinations are different enough that one might as well fuse the two "if (mod == 3)" into one. So do that too. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/508 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [rth: Add a test case ] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'pull-testing-for-7.2-011122-3' of https://github.com/stsquad/qemu ↵Stefan Hajnoczi2022-11-013-19/+10Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging testing and plugin updates for 7.2: - cleanup win32/64 docker files - update test-mingw test - add flex/bison to debian-all-test - handle --enable-static/--disable-pie in config - extend timeouts on x86_64 avocado tests - add flex/bison to debian-hexagon-cross - use regular semihosting for nios2 check-tcg - fix obscure linker error to nios2 softmmu tests - various windows portability fixes for tests - clean-up of MAINTAINERS - use -machine none when appropriate in avocado - make raspi2_initrd test detect shutdown - disable sh4 rd2 tests on gitlab - re-enable threadcount/linux-test for sh4 - clean-up s390x handling of "ex" instruction - better handle new CPUs in execlog plugin - pass CONFIG_DEBUG_TCG to plugin builds - try and avoid races in test-io-channel-command - speed up ssh key checking for tests/vm # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmNhI/MACgkQ+9DbCVqe # KkSFXggAg0HIpBDcNz0V5Mh5p69F14pwbDSygKqGDFBebdOHeL7f+WCvQPUGEWxp # 814zjvRY3SC4Mo4mtzguRvNu0styaUpemvRw5FDYK48GpEjg2eVxTnAFD4nr7ud0 # dhw3iaHP+RjA6s3EpPUqQ5nlZEgFJ+Tvkckk3wKSpksBYA4tJra6Uey5kpZ27x0T # KOzB2P6w+9B/B11n/aeSxvRPZdnXt2MyfS/3pwwfoFYioEyaEQ3Ie6ooachtdSL3 # PEvnJVK0VVYbZQwBXJlycNLlK/D++s4AEwmnZ5GmvDFuXlkRO9YMy9Wa5TKJl7gz # 76Aw1KHsE03SyAPvH4bE7eGkIwhJOQ== # =6hXE # -----END PGP SIGNATURE----- # gpg: Signature made Tue 01 Nov 2022 09:49:39 EDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-testing-for-7.2-011122-3' of https://github.com/stsquad/qemu: (31 commits) tests/vm: use -o IdentitiesOnly=yes for ssh tests/unit: cleanups for test-io-channel-command contrib/plugins: protect execlog's last_exec expansion contrib/plugins: enable debug on CONFIG_DEBUG_TCG tests/tcg: include CONFIG_PLUGIN in config-host.mak target/s390x: fake instruction loading when handling 'ex' target/s390x: don't probe next pc for EXecuted insns target/s390x: don't use ld_code2 to probe next pc tests/tcg: re-enable threadcount for sh4 tests/tcg: re-enable linux-test for sh4 tests/avocado: disable sh4 rd2 tests on Gitlab tests/avocado: raspi2_initrd: Wait for guest shutdown message before stopping tests/avocado: set -machine none for userfwd and vnc tests MAINTAINERS: fix-up for check-tcg Makefile changes MAINTAINERS: add features_to_c.sh to gdbstub files MAINTAINERS: add entries for the key build bits hw/usb: dev-mtp: Use g_mkdir() block/vvfat: Unify the mkdir() call tcg: Avoid using hardcoded /tmp semihosting/arm-compat-semi: Avoid using hardcoded /tmp ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/tcg: re-enable threadcount for sh4Alex Bennée2022-10-311-6/+0Star
| | | | | | | | | | | | | | | | | | | | | | This test was marked as broken due to bug #856 which was fixed by ab419fd8a0 (target/sh4: Fix TB_FLAG_UNALIGN). Local testing shows this is solid now so lets re-enable the test. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20221027183637.2772968-23-alex.bennee@linaro.org>
| * tests/tcg: re-enable linux-test for sh4Alex Bennée2022-10-311-6/+0Star
| | | | | | | | | | | | | | | | | | | | | | This test was marked as broken due to bug #704 which was fixed by aee14c77f4 (linux-user: Rewrite do_getdents, do_getdents64). Local testing shows this is solid now so lets re-enable the test. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20221027183637.2772968-22-alex.bennee@linaro.org>
| * tests/tcg/nios2: Tweak 10m50-ghrd.ldRichard Henderson2022-10-311-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | More closely follow the default linker script for nios2. This magically fixes a problem resolving .got relocs from the toolchain's libgcc.a. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1258 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221024035341.2971123-1-richard.henderson@linaro.org> Message-Id: <20221027183637.2772968-10-alex.bennee@linaro.org>
| * tests/tcg: use regular semihosting for nios2-softmmuAlex Bennée2022-10-311-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | The nios2 code now plugs into the common semihosting code so we can use the same redirect invocation as the other boards. There is however a bug raised for the fact the tests don't seem to be completing properly and silently passing anyway: https://gitlab.com/qemu-project/qemu/-/issues/1258 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221027183637.2772968-9-alex.bennee@linaro.org>
* | tests/tcg/multiarch: Add munmap-pthread.cIlya Leoshkevich2022-10-312-0/+82
|/ | | | | | | | | Add a test to detect races between munmap() and creating new threads. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20221028124227.2354792-3-iii@linux.ibm.com> [rth: add more return insns] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg/s390x: Add a test for the vistr instructionThomas Huth2022-10-282-0/+49
| | | | | | | | | | | This test can be used to verify that the change in the previous commit is indeed fixing the problem with the M3 vs. M4 field mixup. Message-Id: <20221012182755.1014853-4-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* tests/tcg/s390x: Test compiler flags only once, not every timeThomas Huth2022-10-271-10/+17
| | | | | | | | | | | This is common practice, see the Makefile.target in the aarch64 folder for example. Suggested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20221012182755.1014853-2-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/i386: implement FMA instructionsPaolo Bonzini2022-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | The only issue with FMA instructions is that there are _a lot_ of them (30 opcodes, each of which comes in up to 4 versions depending on VEX.W and VEX.L; a total of 96 possibilities). However, they can be implement with only 6 helpers, two for scalar operations and four for packed operations. (Scalar versions do not do any merging; they only affect the bottom 32 or 64 bits of the output operand. Therefore, there is no separate XMM and YMM of the scalar helpers). First, we can reduce the number of helpers to one third by passing four operands (one output and three inputs); the reordering of which operands go to the multiply and which go to the add is done in emit.c. Second, the different instructions also dispatch to the same softfloat function, so the flags for float32_muladd and float64_muladd are passed in the helper as int arguments, with a little extra complication to handle FMADDSUB and FMSUBADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: implement F16C instructionsPaolo Bonzini2022-10-202-2/+23
| | | | | | | | | | | | | | | | | | | F16C only consists of two instructions, which are a bit peculiar nevertheless. First, they access only the low half of an YMM or XMM register for the packed-half operand; the exact size still depends on the VEX.L flag. This is similar to the existing avx_movx flag, but not exactly because avx_movx is hardcoded to affect operand 2. To this end I added a "ph" format name; it's possible to reuse this approach for the VPMOVSX and VPMOVZX instructions, though that would also require adding two more formats for the low-quarter and low-eighth of an operand. Second, VCVTPS2PH is somewhat weird because it *stores* the result of the instruction into memory rather than loading it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tests/tcg: extend SSE tests to AVXPaolo Bonzini2022-10-183-94/+112
| | | | | | | Extracted from a patch by Paul Brook <paul@nowt.org>. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tests/tcg: move compiler tests to MakefilesPaolo Bonzini2022-10-065-1/+36
| | | | | | | | | | Further decoupling of tests/tcg from the main QEMU Makefile, and making the build more similar between the cross compiler case and the vetted container images. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-25-alex.bennee@linaro.org>
* tests/tcg: clean up calls to run-testPaolo Bonzini2022-10-0611-43/+34Star
| | | | | | | | | | | | Almost all invocations of run-test have either "$* on $(TARGET_NAME)" or "$< on $(TARGET_NAME)" as the last argument. So provide a default test name, while allowing an escape hatch for custom names. As an additional simplification, remove the need to do shell quoting. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-24-alex.bennee@linaro.org>
* tests/tcg: unify ppc64 and ppc64le MakefilesPaolo Bonzini2022-10-069-26/+1Star
| | | | | | | | | | | Make tests/tcg/ppc64le include tests/tcg/ppc64 instead of duplicating the rules. Because the ppc64le vpath includes tests/tcg/ppc64 but not vice versa, the tests have to be moved from tests/tcg/ppc64le/ to tests/tcg/ppc64. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-23-alex.bennee@linaro.org>
* tests/tcg: add distclean rulePaolo Bonzini2022-10-061-0/+3
| | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-22-alex.bennee@linaro.org>
* tests: simplify Makefile invocation for tests/tcgPaolo Bonzini2022-10-061-1/+1
| | | | | | | | | | | | | | | Remove the DOCKER_SCRIPT and TARGET variable from the Makefile invocation for tests/tcg. For DOCKER_SCRIPT, resolve the path to docker.py in configure; for TARGET, move it to config-$(TARGET).mak and use a symbolic link to break the cycle. The symbolic link is still needed because tests/tcg includes dummy config files for targets that are not buildable. Once that is cleaned up, the symbolic link will go away too. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220929114231.583801-20-alex.bennee@linaro.org>
* tests/tcg/linux-test: Add linux-madvise testIlya Leoshkevich2022-09-271-0/+70
| | | | | | | | | | Add a test that checks madvise(MADV_DONTNEED) behavior with anonymous and file mappings in order to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220906000839.1672934-6-iii@linux.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* Merge tag 'pull-hex-20220919' of https://github.com/quic/qemu into stagingStefan Hajnoczi2022-09-221-0/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hexagon update remove unused encodings add fmin/fmax tests for signed zero # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmMou7IACgkQewJE+xLe # RCIYbQgAgjFujecgbbCJfBPVMmpTXNOgk+Jt3w+jfg7/WJRZuhxAU3xB2qpismUH # 5MntMlFHAGOjlPXfg6U5AZFSw3RhlanH/RChHpVKuL6peOXFImIfEqdyVXHXfCuu # FlpQFGwJ3Rs50UJhd7lVdlx0I7lup4E4X77hFvFcZQP6aNrt6Ic1Zq5eXhEq9k2A # NnXol1R416JRT/senujYVvcTpgYVHlQCS+4dJEzKUqvFlTdo7lnAbPdjO8MPrz7B # 0NgPUGjGZJ70Dcqvd1n8HePIU1YyKTlHJNaWyTlAmw4MECyHyAJnd64jEMNECDb5 # 0BrpHcY1HCt1Rh4QratemTfJglAJlA== # =UUyr # -----END PGP SIGNATURE----- # gpg: Signature made Mon 19 Sep 2022 14:57:54 EDT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20220919' of https://github.com/quic/qemu: Hexagon (tests/tcg/hexagon): add fmin/fmax tests for signed zero Hexagon (target/hexagon) remove unused encodings Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * Hexagon (tests/tcg/hexagon): add fmin/fmax tests for signed zeroMatheus Tavares Bernardino2022-09-191-0/+10
| | | | | | | | | | | | | | Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com>
* | tests/tcg: remove old SSE testsPaolo Bonzini2022-09-191-573/+0Star
| | | | | | | | | | | | | | | | | | The new testsuite is much more comprehensive, so remove the old one; it is also buggy (the pinsrw test uses incorrect constraints, with = instead of +, and the golden output for the fxsave tests differs depending on how the C library uses SSE and AVX instructions). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | tests/tcg: refine MMX support in SSE testsPaolo Bonzini2022-09-191-6/+26
| | | | | | | | | | | | | | Extend the support to memory operands, and skip MMX instructions that were introduced in SSE times, because they are now covered in test-mmx. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | tests/tcg: i386: add MMX and 3DNow! testsPaolo Bonzini2022-09-196-5/+583
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the test-avx.py generator to produce tests specifically for MMX and 3DNow. Using a separate generator introduces some code duplication, but is a simpler approach because of test-avx's extra complexity to support 3- and 4-operand AVX instructions. If needed, a common library can be introduced later. While at it, for consistency move all the -cpu max rules to the same place. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | tests/tcg: i386: fix typos in 3DNow! instructionsPaolo Bonzini2022-09-181-2/+2
|/ | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/riscv: Make translator stop before the end of a pageRichard Henderson2022-09-062-0/+80
| | | | | | | | | | | | Right now the translator stops right *after* the end of a page, which breaks reporting of fault locations when the last instruction of a multi-insn translation block crosses a page boundary. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1155 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/i386: Make translator stop before the end of a pageIlya Leoshkevich2022-09-062-1/+77
| | | | | | | | | | | | | | | | | | | | | | Right now translator stops right *after* the end of a page, which breaks reporting of fault locations when the last instruction of a multi-insn translation block crosses a page boundary. An implementation, like the one arm and s390x have, would require an i386 length disassembler, which is burdensome to maintain. Another alternative would be to single-step at the end of a guest page, but this may come with a performance impact. Fix by snapshotting disassembly state and restoring it after we figure out we crossed a page boundary. This includes rolling back cc_op updates and emitted ops. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1143 Message-Id: <20220817150506.592862-4-iii@linux.ibm.com> [rth: Simplify end-of-insn cross-page checks.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/s390x: Make translator stop before the end of a pageIlya Leoshkevich2022-09-063-0/+246
| | | | | | | | | | | Right now translator stops right *after* the end of a page, which breaks reporting of fault locations when the last instruction of a multi-insn translation block crosses a page boundary. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220817150506.592862-3-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg/i386: Move smc_code2 to an executable sectionRichard Henderson2022-09-061-1/+1
| | | | | | | | | | | | We're about to start validating PAGE_EXEC, which means that we've got to put this code into a section that is both writable and executable. Note that this test did not run on hardware beforehand either. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tests/tcg: i386: add SSE testsPaul Brook2022-09-017-3/+5359
| | | | | | | | | | | | | | | Tests for correct operation of most x86-64 SSE instructions. It should cover all combinations of overlapping register and memory operands on a set of random-ish data. Results are bit-identical to an Intel i5-8500, with the exception of the RCPSS and RSQRT approximations where the real CPU gives less accurate results (the Intel spec allows relative errors up to 1.5 * 2^-12) Signed-off-by: Paul Brook <paul@nowt.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220424220204.2493824-42-paul@nowt.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tests/tcg: i386: extend BMI testPaolo Bonzini2022-09-012-8/+162
| | | | | | | | | Cover all BMI1 and BMI2 instructions, both 32- and 64-bit. Due to the use of inlines, the test now has to be compiled with -O2. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tests/tcg: x86_64: improve consistency with i386Paolo Bonzini2022-09-012-2/+4
| | | | | | | | Include test-i386-bmi2, and specify manually the tests (only one for now) that need -cpu max. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/loongarch: Remove cpu_fcsr0Richard Henderson2022-08-092-0/+16
| | | | | | | | | | | | All of the fpu operations are defined with TCG_CALL_NO_WG, but they all modify FCSR0. The most efficient way to fix this is to remove cpu_fcsr0, and instead use explicit load and store operations for the two instructions that manipulate that value. Acked-by: Qi Hu <huqi@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Reported-by: Feiyang Chen <chenfeiyang@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'pull-request-2022-08-01' of https://gitlab.com/thuth/qemu into ↵Richard Henderson2022-08-011-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging - Some fixes for various tests - Improve wordings in some files # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmLn6aYRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWekg/+NVIT1jp3tcbfPIE6pB0vI/AhqN3i2hUd # zfJ4V3rSe5tg54JpmuuSt542mp4BDM9bPfYcY/DYESWEtW0c9wv80iP/5LFdJF0G # GYtk7Q4pRXvB32kF0v9OxjCEGPUeEqSRrDrsI/Ify5evEIhr55oHPnDjN/US1Bx+ # TIuVfmyz8jhSPHsUvZzfVyFxkHre1+BWDxgM3zxoHFIaWEscIPE1KhwRILbKIxWx # MHpL8JLAneGFwljQoUAMCl7GzHkVna59RhqkbBJ+8iTaNGipQj9FhHZBo2CulO0J # SR7scWowYN8Jt2FNMe3tcKM2xQn/2Fg2TEK4sp6q+hCXhJuvFfWFHBiFYTNpagFA # LGgZmPfDr4uZtMEqY4AdEZdL14YZcoM9E/RpW7GhSvMHy73wOj16O8luH1bU0jtG # 6X1VvAZlw8/Son1Tbq2CC6WejlMfJFXSzF6Fy6M7SflMPW44vJOs5uKdW405MYjE # Pksbfz1rwoNfK+1qBNQop7SccgDRvPtlLf3lDAU9V/JHWVEITs1KTfyS+46U8jKA # 9SVBzKuTpVd+aXvMgvMAmmqnyvUBPHJ9KcFq4vHNbIETsGaQsXu0Q6waBmpcK8YB # KUL/g0EsdfhkpVVgKYZ4Bzj7shG6SKTdwc/lUcOt+wQuDrZZzaC+A2cu/6ReQN6T # BIHtoaxTz8E= # =K6RW # -----END PGP SIGNATURE----- # gpg: Signature made Mon 01 Aug 2022 07:56:38 AM PDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined] # gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-08-01' of https://gitlab.com/thuth/qemu: tests/qtest/migration-test: Run the dirty ring tests only with the x86 target trivial: Fix duplicated words misc: fix commonly doubled up words tests/unit/test-qga: Replace the word 'blacklist' in the guest agent unit test migration-test: Allow test to run without uffd migration-test: Use migrate_ensure_converge() for auto-converge tests/tcg/linux-test: Fix random hangs in test_socket Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tests/tcg/linux-test: Fix random hangs in test_socketIlya Leoshkevich2022-08-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | test_socket hangs randomly in connect(), especially when run without qemu. Apparently the reason is that linux started treating backlog value of 0 literally instead of rounding it up since v4.4 (commit ef547f2ac16b). So set it to 1 instead. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20220725144251.192720-1-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | Hexagon (tests/tcg/hexagon) reference file for float_convdTaylor Simpson2022-08-011-0/+988
| | | | | | | | | | | | | | | | The test is in tests/tcg/multiarch/float_convd.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220718230320.24444-4-tsimpson@quicinc.com>
* | Hexagon (tests/tcg/hexagon) Fix alignment in load_unpack.cTaylor Simpson2022-08-011-7/+7
| | | | | | | | | | | | | | | | | | The increment used in :brev tests was causing unaligned addresses Change the increment and the relevant expected values Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220718230320.24444-3-tsimpson@quicinc.com>
* | Hexagon (target/hexagon) make VyV operands use a unique tempTaylor Simpson2022-08-011-0/+45
|/ | | | | | | | | | | | | VyV operand is only used in the vshuff and vdeal instructions. These instructions write to both VyV and VxV operands. In the case where both operands are the same register, we need a separate location for VyV. We use the existing vtmp field in CPUHexagonState. Test case added in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220718230320.24444-2-tsimpson@quicinc.com>
* tests/tcg/s390x: Test unaligned accesses to lowcoreIlya Leoshkevich2022-07-292-0/+28
| | | | | | | | | | Add a small test to avoid regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220725223746.227063-3-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* Merge tag 'pull-request-2022-07-20' of https://gitlab.com/thuth/qemu into ↵Peter Maydell2022-07-202-0/+418
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Fixes for s390x floating point vector instructions # gpg: Signature made Wed 20 Jul 2022 08:14:50 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-07-20' of https://gitlab.com/thuth/qemu: tests/tcg/s390x: test signed vfmin/vfmax target/s390x: fix NaN propagation rules target/s390x: fix handling of zeroes in vfmin/vfmax Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # fpu/softfloat-specialize.c.inc
| * tests/tcg/s390x: test signed vfmin/vfmaxIlya Leoshkevich2022-07-192-0/+418
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a test to prevent regressions. Try all floating point value sizes and all combinations of floating point value classes. Verify the results against PoP tables, which are represented as close to the original as possible - this produces a lot of checkpatch complaints, but it seems to be justified in this case. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220713182612.3780050-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | Merge tag 'pull-hex-20220719-1' of https://github.com/quic/qemu into stagingPeter Maydell2022-07-203-5/+264
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recall that the semantics of a Hexagon mem_noshuf packet are that the store effectively happens before the load. There are two bug fixes in this series. # gpg: Signature made Tue 19 Jul 2022 22:25:19 BST # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20220719-1' of https://github.com/quic/qemu: Hexagon (target/hexagon) fix bug in mem_noshuf load exception Hexagon (target/hexagon) fix store w/mem_noshuf & predicated load Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | Hexagon (target/hexagon) fix bug in mem_noshuf load exceptionTaylor Simpson2022-07-192-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantics of a mem_noshuf packet are that the store effectively happens before the load. However, in cases where the load raises an exception, we cannot simply execute the store first. This change adds a probe to check that the load will not raise an exception before executing the store. If the load is predicated, this requires special handling. We check the condition before performing the probe. Since, we need the EA to perform the check, we move the GET_EA portion inside CHECK_NOSHUF_PRED. Test case added in tests/tcg/hexagon/mem_noshuf_exception.c Suggested-by: Alessandro Di Federico <ale@rev.ng> Suggested-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220707210546.15985-3-tsimpson@quicinc.com>
| * | Hexagon (target/hexagon) fix store w/mem_noshuf & predicated loadTaylor Simpson2022-07-191-5/+117
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call the CHECK_NOSHUF macro multiple times: once in the fGEN_TCG_PRED_LOAD() and again in fLOAD(). Before this commit, a packet with a store and a predicated load with mem_noshuf that gets encoded like this: { P0 = cmp.eq(R17,#0x0) memw(R18+#0x0) = R2 if (!P0.new) R3 = memw(R17+#0x4) } ... would end up generating a branch over both the load and the store like so: ... brcond_i32 loc17,$0x0,eq,$L1 mov_i32 loc18,store_addr_1 qemu_st_i32 store_val32_1,store_addr_1,leul,0 qemu_ld_i32 loc16,loc7,leul,0 set_label $L1 ... Test cases added to tests/tcg/hexagon/mem_noshuf.c Co-authored-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220707210546.15985-2-tsimpson@quicinc.com>
* | tests/tcg/loongarch64: Add pcadd related instructions testSong Gao2022-07-192-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | This includes: - PCADDI - PCADDU12I - PCADDU18I - PCALAU12I Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220716085426.3098060-9-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tests/tcg/loongarch64: Add fp comparison instructions testSong Gao2022-07-192-0/+38
| | | | | | | | | | | | | | | | | | | | Choose some instructions to test: - FCMP.cond.S - cond: ceq clt cle cne seq slt sle sne Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220716085426.3098060-8-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tests/tcg/loongarch64: Add fclass testSong Gao2022-07-192-0/+131
| | | | | | | | | | | | | | | | | | This includes: - FCLASS.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220716085426.3098060-7-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tests/tcg/loongarch64: Add div and mod related instructions testSong Gao2022-07-192-0/+55
| | | | | | | | | | | | | | | | | | | | This includes: - DIV.{W[U]/D[U]} - MOD.{W[U]/D[U]} Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220716085426.3098060-6-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tests/tcg/loongarch64: Add clo related instructions testSong Gao2022-07-192-0/+103
| | | | | | | | | | | | | | | | | | | | This includes: - CL{O/Z}.{W/D} - CT{O/Z}.{W/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220716085426.3098060-5-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | tests/tcg/loongarch64: Add float reference filesPhilippe Mathieu-Daudé2022-07-193-0/+2504
|/ | | | | | | | | | Generated on Loongson-3A5000 (CPU revision 0x0014c011). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220104132022.2146857-1-f4bug@amsat.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220716085426.3098060-2-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell2022-07-125-4/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * fuzzing fixes (Alexander) * fix cross compilation CFLAGS and compiler choice * do not specify -bios option for tests/vm * miscellaneous fixes * preparation for pre-install tree in the build directory (Akihiko) # gpg: Signature made Tue 12 Jul 2022 13:47:19 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: meson: place default firmware path under .../share qga: Relocate a path emitted in the help text build: Do not depend on pc-bios for config-host.mak accel: kvm: Fix memory leak in find_stats_descriptors audio/dbus: fix building fuzz: only use generic-fuzz targets on oss-fuzz build: improve -fsanitize-coverage-allowlist check build: try both native and cross compilers configure: pass whole target name to probe_target_compiler tests/tcg: compile system emulation tests as freestanding configure: write EXTRA_CFLAGS for all sub-Makefiles configure: allow more host/target combos to use the host compiler configure, pc-bios/vof: pass cross CFLAGS correctly configure, pc-bios/s390-ccw: pass cross CFLAGS correctly configure, pc-bios/optionrom: pass cross CFLAGS correctly pc-bios/optionrom: use -m16 unconditionally scsi/lsi53c895a: fix use-after-free in lsi_do_msgout (CVE-2022-0216) tests/vm: do not specify -bios option Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # pc-bios/s390-ccw/netboot.mak
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-04 20:17:12 +0100