From 8063db0fc8256e3f6b9b33c246bd926f3a2dbb12 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Mon, 31 Oct 2022 13:25:29 +0000 Subject: target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F As per an unpublished document, in later reversion of chips CP0St_{KX, SX, UX} is not writeable and hardcoded to 1. Without those bits set, kernel is unable to access XKPHYS address segment. So just set them up on CPU reset. Signed-off-by: Jiaxun Yang Acked-by: Richard Henderson Message-Id: <20221031132531.18122-2-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e997c1b9cb..7a565466cb 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -302,6 +302,12 @@ static void mips_cpu_reset(DeviceState *dev) env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); + if (env->insn_flags & INSN_LOONGSON2F) { + /* Loongson-2F has those bits hardcoded to 1 */ + env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | + (1 << CP0St_UX); + } + /* * Vectored interrupts not implemented, timer on int 7, * no performance counters. -- cgit v1.2.3-55-g7522