From c8b69a2a92bebed915af69bb685816e715956ecc Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sat, 31 Jul 2021 00:27:17 +0200 Subject: target/mips: Remove JR opcode unused arguments JR opcode (Jump Register) only takes 1 argument, $rs. JALR (Jump And Link Register) takes 3: $rs, $rd and $hint. Commit 6af0bf9c7c3 added their processing into decode_opc() as: case 0x08 ... 0x09: /* Jumps */ gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa); having both opcodes handled in the same function: gen_compute_branch. Per JR encoding, both $rd and $hint ('sa') are decoded as zero. Later this code got extracted to decode_opc_special(), commit 7a387fffce5 used definitions instead of magic values: case OPC_JR ... OPC_JALR: gen_compute_branch(ctx, op1, rs, rd, sa); Finally commit 0aefa33318b moved OPC_JR out of decode_opc_special, to a new 'decode_opc_special_legacy' function: @@ -15851,6 +15851,9 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) + case OPC_JR: + gen_compute_branch(ctx, op1, 4, rs, rd, sa); + break; @@ -15933,7 +15936,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) - case OPC_JR ... OPC_JALR: + case OPC_JALR: gen_compute_branch(ctx, op1, 4, rs, rd, sa); break; Since JR is now handled individually, it is pointless to decode and pass it unused arguments. Replace them by simple zero value to avoid confusion with this opcode. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210730225507.2642827-1-f4bug@amsat.org> Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 5b03545f09..bf71724f3f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -14203,7 +14203,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) break; #endif case OPC_JR: - gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4); + gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4); break; case OPC_SPIM: #ifdef MIPS_STRICT_STANDARD -- cgit v1.2.3-55-g7522 From 2e176eaf9c54a23ea2f37ccbeef2045f422b0e30 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Thu, 29 Jul 2021 16:02:57 +0200 Subject: target/mips: Simplify PREF opcode check_insn() checks for any bit in the set, and INSN_R5900 is just another bit added to the set. No need to special-case it. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210801234202.3167676-2-f4bug@amsat.org> Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index bf71724f3f..6b95cca052 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15739,12 +15739,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) /* Treat as NOP. */ break; case OPC_PREF: - if (ctx->insn_flags & INSN_R5900) { - /* Treat as NOP. */ - } else { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); - /* Treat as NOP. */ - } + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900); + /* Treat as NOP. */ break; /* Floating point (COP1). */ -- cgit v1.2.3-55-g7522 From 4919f69c658be36c97d63660bd41377b06ea6822 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sat, 31 Jul 2021 15:23:47 +0200 Subject: target/mips: Decode vendor extensions before MIPS ISAs In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree") we misplaced the decoder call. Move it to the correct place. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210801234202.3167676-3-f4bug@amsat.org> Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 6b95cca052..490add3fc1 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16094,6 +16094,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) /* Transition to the auto-generated decoder. */ + /* Vendor specific extensions */ + if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { + return; + } + /* ISA extensions */ if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { return; @@ -16103,9 +16108,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { return; } - if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { - return; - } if (decode_opc_legacy(env, ctx)) { return; -- cgit v1.2.3-55-g7522 From 12f79f11731194d7cb61c4a0d9b2de5416a773de Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sun, 1 Aug 2021 20:29:29 +0200 Subject: target/mips: Merge 32-bit/64-bit Release6 decodetree definitions We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210801234202.3167676-4-f4bug@amsat.org> Reviewed-by: Richard Henderson --- target/mips/tcg/meson.build | 3 +-- target/mips/tcg/mips32r6.decode | 36 ----------------------------- target/mips/tcg/mips64r6.decode | 27 ---------------------- target/mips/tcg/rel6.decode | 49 ++++++++++++++++++++++++++++++++++++++++ target/mips/tcg/rel6_translate.c | 16 ++++--------- 5 files changed, 55 insertions(+), 76 deletions(-) delete mode 100644 target/mips/tcg/mips32r6.decode delete mode 100644 target/mips/tcg/mips64r6.decode create mode 100644 target/mips/tcg/rel6.decode diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index bf4001e574..70fa3dd57d 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,6 +1,5 @@ gen = [ - decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'), - decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'), + decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), ] diff --git a/target/mips/tcg/mips32r6.decode b/target/mips/tcg/mips32r6.decode deleted file mode 100644 index 837c991edc..0000000000 --- a/target/mips/tcg/mips32r6.decode +++ /dev/null @@ -1,36 +0,0 @@ -# MIPS32 Release 6 instruction set -# -# Copyright (C) 2020 Philippe Mathieu-Daudé -# -# SPDX-License-Identifier: LGPL-2.1-or-later -# -# Reference: -# MIPS Architecture for Programmers Volume II-A -# The MIPS32 Instruction Set Reference Manual, Revision 6.06 -# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06) -# - -&rtype rs rt rd sa - -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype - -LSA 000000 ..... ..... ..... 000 .. 000101 @lsa - -REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) - -REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 - -REMOVED 011111 ----- ----- ---------- 011001 # LWLE -REMOVED 011111 ----- ----- ---------- 011010 # LWRE -REMOVED 011111 ----- ----- ---------- 100001 # SWLE -REMOVED 011111 ----- ----- ---------- 100010 # SWRE - -REMOVED 100010 ----- ----- ---------------- # LWL -REMOVED 100110 ----- ----- ---------------- # LWR -REMOVED 101010 ----- ----- ---------------- # SWL -REMOVED 101110 ----- ----- ---------------- # SWR - -REMOVED 101111 ----- ----- ---------------- # CACHE -REMOVED 110000 ----- ----- ---------------- # LL -REMOVED 110011 ----- ----- ---------------- # PREF -REMOVED 111000 ----- ----- ---------------- # SC diff --git a/target/mips/tcg/mips64r6.decode b/target/mips/tcg/mips64r6.decode deleted file mode 100644 index b58d8009cc..0000000000 --- a/target/mips/tcg/mips64r6.decode +++ /dev/null @@ -1,27 +0,0 @@ -# MIPS64 Release 6 instruction set -# -# Copyright (C) 2020 Philippe Mathieu-Daudé -# -# SPDX-License-Identifier: LGPL-2.1-or-later -# -# Reference: -# MIPS Architecture for Programmers Volume II-A -# The MIPS64 Instruction Set Reference Manual, Revision 6.06 -# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) -# - -&rtype rs rt rd sa !extern - -&REMOVED !extern - -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype - -DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa - -REMOVED 011010 ----- ----- ---------------- # LDL -REMOVED 011011 ----- ----- ---------------- # LDR -REMOVED 101100 ----- ----- ---------------- # SDL -REMOVED 101101 ----- ----- ---------------- # SDR - -REMOVED 110100 ----- ----- ---------------- # LLD -REMOVED 111100 ----- ----- ---------------- # SCD diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode new file mode 100644 index 0000000000..ed069c5166 --- /dev/null +++ b/target/mips/tcg/rel6.decode @@ -0,0 +1,49 @@ +# MIPS32 Release 6 instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# +# MIPS Architecture for Programmers Volume II-A +# The MIPS32 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06) +# +# MIPS Architecture for Programmers Volume II-A +# The MIPS64 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) + +&rtype rs rt rd sa + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype + +LSA 000000 ..... ..... ..... 000 .. 000101 @lsa +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa + +REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) + +REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 + +REMOVED 011010 ----- ----- ---------------- # LDL +REMOVED 011011 ----- ----- ---------------- # LDR + +REMOVED 011111 ----- ----- ---------- 011001 # LWLE +REMOVED 011111 ----- ----- ---------- 011010 # LWRE +REMOVED 011111 ----- ----- ---------- 100001 # SWLE +REMOVED 011111 ----- ----- ---------- 100010 # SWRE + +REMOVED 100010 ----- ----- ---------------- # LWL +REMOVED 100110 ----- ----- ---------------- # LWR +REMOVED 101010 ----- ----- ---------------- # SWL +REMOVED 101100 ----- ----- ---------------- # SDL +REMOVED 101101 ----- ----- ---------------- # SDR +REMOVED 101110 ----- ----- ---------------- # SWR + +REMOVED 101111 ----- ----- ---------------- # CACHE + +REMOVED 110000 ----- ----- ---------------- # LL +REMOVED 110011 ----- ----- ---------------- # PREF +REMOVED 110100 ----- ----- ---------------- # LLD +REMOVED 111000 ----- ----- ---------------- # SC +REMOVED 111100 ----- ----- ---------------- # SCD diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c index 0354370927..ae2e023a81 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -13,9 +13,8 @@ #include "exec/helper-gen.h" #include "translate.h" -/* Include the auto-generated decoder. */ -#include "decode-mips32r6.c.inc" -#include "decode-mips64r6.c.inc" +/* Include the auto-generated decoders. */ +#include "decode-rel6.c.inc" bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) { @@ -31,13 +30,8 @@ static bool trans_LSA(DisasContext *ctx, arg_rtype *a) static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) { - return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); -} - -bool decode_isa_rel6(DisasContext *ctx, uint32_t insn) -{ - if (TARGET_LONG_BITS == 64 && decode_mips64r6(ctx, insn)) { - return true; + if (TARGET_LONG_BITS != 64) { + return false; } - return decode_mips32r6(ctx, insn); + return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); } -- cgit v1.2.3-55-g7522 From 34fe9fa3683a7ff54315c62960eba6eeac2a36ac Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 27 Jul 2021 21:13:49 +0200 Subject: target/mips: Rename 'rtype' as 'r' We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> Reviewed-by: Richard Henderson --- target/mips/tcg/msa.decode | 4 +-- target/mips/tcg/msa_translate.c | 4 +-- target/mips/tcg/rel6.decode | 4 +-- target/mips/tcg/rel6_translate.c | 4 +-- target/mips/tcg/tx79.decode | 14 ++++----- target/mips/tcg/tx79_translate.c | 62 ++++++++++++++++++++-------------------- 6 files changed, 46 insertions(+), 46 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index bf132e36b9..74d99f6862 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -11,11 +11,11 @@ # - The MIPS64 SIMD Architecture Module, Revision 1.12 # (Document Number: MD00868-1D-MSA64-AFP-01.12) -&rtype rs rt rd sa +&r rs rt rd sa &msa_bz df wt s16 -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz ...... ... .. wt:5 s16:16 &msa_bz df=3 @bz_df ...... ... df:2 wt:5 s16:16 &msa_bz diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index eed2eca6c9..8170a8df26 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -2261,12 +2261,12 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) return true; } -static bool trans_LSA(DisasContext *ctx, arg_rtype *a) +static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } -static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) +static bool trans_DLSA(DisasContext *ctx, arg_r *a) { if (TARGET_LONG_BITS != 64) { return false; diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode index ed069c5166..d6989cf56e 100644 --- a/target/mips/tcg/rel6.decode +++ b/target/mips/tcg/rel6.decode @@ -14,9 +14,9 @@ # The MIPS64 Instruction Set Reference Manual, Revision 6.06 # (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) -&rtype rs rt rd sa +&r rs rt rd sa -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c index ae2e023a81..d631851258 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -23,12 +23,12 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) return true; } -static bool trans_LSA(DisasContext *ctx, arg_rtype *a) +static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } -static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) +static bool trans_DLSA(DisasContext *ctx, arg_r *a) { if (TARGET_LONG_BITS != 64) { return false; diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode index 03a25a5096..57d87a2076 100644 --- a/target/mips/tcg/tx79.decode +++ b/target/mips/tcg/tx79.decode @@ -11,20 +11,20 @@ # when creating helpers common to those for the individual # instruction patterns. -&rtype rs rt rd sa +&r rs rt rd sa -&itype base rt offset +&i base rt offset ########################################################################### # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. -@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=0 -@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0 -@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0 -@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r sa=0 +@rt_rd ...... ..... rt:5 rd:5 ..... ...... &r sa=0 rs=0 +@rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0 +@rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0 -@ldst ...... base:5 rt:5 offset:16 &itype +@ldst ...... base:5 rt:5 offset:16 &i ########################################################################### diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c index 395d6afa1f..6d51fe17c1 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -64,28 +64,28 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) * MTLO1 rs Move To LO1 Register */ -static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) +static bool trans_MFHI1(DisasContext *ctx, arg_r *a) { gen_store_gpr(cpu_HI[1], a->rd); return true; } -static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) +static bool trans_MFLO1(DisasContext *ctx, arg_r *a) { gen_store_gpr(cpu_LO[1], a->rd); return true; } -static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) +static bool trans_MTHI1(DisasContext *ctx, arg_r *a) { gen_load_gpr(cpu_HI[1], a->rs); return true; } -static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) +static bool trans_MTLO1(DisasContext *ctx, arg_r *a) { gen_load_gpr(cpu_LO[1], a->rs); @@ -116,7 +116,7 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word */ -static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a, +static bool trans_parallel_arith(DisasContext *ctx, arg_r *a, void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64)) { TCGv_i64 ax, bx; @@ -146,19 +146,19 @@ static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a, } /* Parallel Subtract Byte */ -static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a) +static bool trans_PSUBB(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_vec_sub8_i64); } /* Parallel Subtract Halfword */ -static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a) +static bool trans_PSUBH(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_vec_sub16_i64); } /* Parallel Subtract Word */ -static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a) +static bool trans_PSUBW(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_vec_sub32_i64); } @@ -189,25 +189,25 @@ static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a) */ /* Parallel And */ -static bool trans_PAND(DisasContext *ctx, arg_rtype *a) +static bool trans_PAND(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_and_i64); } /* Parallel Or */ -static bool trans_POR(DisasContext *ctx, arg_rtype *a) +static bool trans_POR(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_or_i64); } /* Parallel Exclusive Or */ -static bool trans_PXOR(DisasContext *ctx, arg_rtype *a) +static bool trans_PXOR(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_xor_i64); } /* Parallel Not Or */ -static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) +static bool trans_PNOR(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_nor_i64); } @@ -237,7 +237,7 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) * PCEQW rd, rs, rt Parallel Compare for Equal Word */ -static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a, +static bool trans_parallel_compare(DisasContext *ctx, arg_r *a, TCGCond cond, unsigned wlen) { TCGv_i64 c0, c1, ax, bx, t0, t1, t2; @@ -286,37 +286,37 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a, } /* Parallel Compare for Greater Than Byte */ -static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a) +static bool trans_PCGTB(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_GE, 8); } /* Parallel Compare for Equal Byte */ -static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a) +static bool trans_PCEQB(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8); } /* Parallel Compare for Greater Than Halfword */ -static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a) +static bool trans_PCGTH(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_GE, 16); } /* Parallel Compare for Equal Halfword */ -static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a) +static bool trans_PCEQH(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16); } /* Parallel Compare for Greater Than Word */ -static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a) +static bool trans_PCGTW(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_GE, 32); } /* Parallel Compare for Equal Word */ -static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) +static bool trans_PCEQW(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32); } @@ -334,7 +334,7 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) * SQ rt, offset(base) Store Quadword */ -static bool trans_LQ(DisasContext *ctx, arg_itype *a) +static bool trans_LQ(DisasContext *ctx, arg_i *a) { TCGv_i64 t0; TCGv addr; @@ -369,7 +369,7 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a) return true; } -static bool trans_SQ(DisasContext *ctx, arg_itype *a) +static bool trans_SQ(DisasContext *ctx, arg_i *a) { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv addr = tcg_temp_new(); @@ -437,7 +437,7 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a) */ /* Parallel Pack to Word */ -static bool trans_PPACW(DisasContext *ctx, arg_rtype *a) +static bool trans_PPACW(DisasContext *ctx, arg_r *a) { TCGv_i64 a0, b0, t0; @@ -473,7 +473,7 @@ static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b) tcg_gen_deposit_i64(dh, a, b, 0, 32); } -static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen) +static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen) { TCGv_i64 ax, bx; @@ -514,19 +514,19 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen) } /* Parallel Extend Lower from Byte */ -static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTLB(DisasContext *ctx, arg_r *a) { return trans_PEXTLx(ctx, a, 8); } /* Parallel Extend Lower from Halfword */ -static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTLH(DisasContext *ctx, arg_r *a) { return trans_PEXTLx(ctx, a, 16); } /* Parallel Extend Lower from Word */ -static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTLW(DisasContext *ctx, arg_r *a) { TCGv_i64 ax, bx; @@ -549,7 +549,7 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a) } /* Parallel Extend Upper from Word */ -static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTUW(DisasContext *ctx, arg_r *a) { TCGv_i64 ax, bx; @@ -593,7 +593,7 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a) */ /* Parallel Copy Halfword */ -static bool trans_PCPYH(DisasContext *s, arg_rtype *a) +static bool trans_PCPYH(DisasContext *s, arg_r *a) { if (a->rd == 0) { /* nop */ @@ -615,7 +615,7 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a) } /* Parallel Copy Lower Doubleword */ -static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) +static bool trans_PCPYLD(DisasContext *s, arg_r *a) { if (a->rd == 0) { /* nop */ @@ -638,7 +638,7 @@ static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) } /* Parallel Copy Upper Doubleword */ -static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) +static bool trans_PCPYUD(DisasContext *s, arg_r *a) { if (a->rd == 0) { /* nop */ @@ -657,7 +657,7 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) } /* Parallel Rotate 3 Words Left */ -static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a) +static bool trans_PROT3W(DisasContext *ctx, arg_r *a) { TCGv_i64 ax; -- cgit v1.2.3-55-g7522 From fb3164e412dac312cc472968d049ee1a074dd7d3 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sat, 7 Aug 2021 09:36:49 +0200 Subject: target/mips: Introduce generic TRANS() macro for decodetree helpers Plain copy/paste of the TRANS() macro introduced in the PPC commit f2aabda8ac9 ("target/ppc: Move D/DS/X-form integer loads to decodetree") to the MIPS target. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210808173018.90960-2-f4bug@amsat.org> --- target/mips/tcg/translate.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index c25fad597d..791e3e2c7e 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -202,4 +202,12 @@ bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); #endif +/* + * Helpers for implementing sets of trans_* functions. + * Defer the implementation of NAME to FUNC, with optional extra arguments. + */ +#define TRANS(NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { return FUNC(ctx, a, __VA_ARGS__); } + #endif -- cgit v1.2.3-55-g7522 From 07565cbf4abb81efa6dc4742c243bdc4b3444398 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Mon, 16 Nov 2020 16:39:20 +0100 Subject: target/mips: Extract NEC Vr54xx helper definitions Extract the NEC Vr54xx helper definitions to 'vendor-vr54xx_helper.h'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201120210844.2625602-15-f4bug@amsat.org> --- target/mips/helper.h | 18 +++--------------- target/mips/tcg/vr54xx_helper.h.inc | 24 ++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 15 deletions(-) create mode 100644 target/mips/tcg/vr54xx_helper.h.inc diff --git a/target/mips/helper.h b/target/mips/helper.h index a9c6c7d1a3..de32d82e98 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -16,21 +16,6 @@ DEF_HELPER_3(lld, tl, env, tl, int) #endif #endif -DEF_HELPER_3(muls, tl, env, tl, tl) -DEF_HELPER_3(mulsu, tl, env, tl, tl) -DEF_HELPER_3(macc, tl, env, tl, tl) -DEF_HELPER_3(maccu, tl, env, tl, tl) -DEF_HELPER_3(msac, tl, env, tl, tl) -DEF_HELPER_3(msacu, tl, env, tl, tl) -DEF_HELPER_3(mulhi, tl, env, tl, tl) -DEF_HELPER_3(mulhiu, tl, env, tl, tl) -DEF_HELPER_3(mulshi, tl, env, tl, tl) -DEF_HELPER_3(mulshiu, tl, env, tl, tl) -DEF_HELPER_3(macchi, tl, env, tl, tl) -DEF_HELPER_3(macchiu, tl, env, tl, tl) -DEF_HELPER_3(msachi, tl, env, tl, tl) -DEF_HELPER_3(msachiu, tl, env, tl, tl) - DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) #ifdef TARGET_MIPS64 DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) @@ -609,3 +594,6 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) #endif /* !CONFIG_USER_ONLY */ #include "tcg/msa_helper.h.inc" + +/* Vendor extensions */ +#include "tcg/vr54xx_helper.h.inc" diff --git a/target/mips/tcg/vr54xx_helper.h.inc b/target/mips/tcg/vr54xx_helper.h.inc new file mode 100644 index 0000000000..50b1f5b818 --- /dev/null +++ b/target/mips/tcg/vr54xx_helper.h.inc @@ -0,0 +1,24 @@ +/* + * MIPS NEC Vr54xx instruction emulation helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_3(muls, tl, env, tl, tl) +DEF_HELPER_3(mulsu, tl, env, tl, tl) +DEF_HELPER_3(macc, tl, env, tl, tl) +DEF_HELPER_3(maccu, tl, env, tl, tl) +DEF_HELPER_3(msac, tl, env, tl, tl) +DEF_HELPER_3(msacu, tl, env, tl, tl) +DEF_HELPER_3(mulhi, tl, env, tl, tl) +DEF_HELPER_3(mulhiu, tl, env, tl, tl) +DEF_HELPER_3(mulshi, tl, env, tl, tl) +DEF_HELPER_3(mulshiu, tl, env, tl, tl) +DEF_HELPER_3(macchi, tl, env, tl, tl) +DEF_HELPER_3(macchiu, tl, env, tl, tl) +DEF_HELPER_3(msachi, tl, env, tl, tl) +DEF_HELPER_3(msachiu, tl, env, tl, tl) -- cgit v1.2.3-55-g7522 From 6629f79f53ea9a1caa3f3c842fa3d02488116486 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Mon, 16 Nov 2020 16:41:05 +0100 Subject: target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c Extract NEC Vr54xx helpers from op_helper.c to a new file: 'vr54xx_helper.c'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201120210844.2625602-14-f4bug@amsat.org> --- target/mips/tcg/meson.build | 1 + target/mips/tcg/op_helper.c | 118 --------------------------------- target/mips/tcg/vr54xx_helper.c | 142 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+), 118 deletions(-) create mode 100644 target/mips/tcg/vr54xx_helper.c diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 70fa3dd57d..ff618a159b 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -18,6 +18,7 @@ mips_ss.add(files( 'translate.c', 'translate_addr_const.c', 'txx9_translate.c', + 'vr54xx_helper.c', )) mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index fafbf1faca..ef3dafcbb3 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -26,124 +26,6 @@ #include "exec/memop.h" #include "fpu_helper.h" -/* 64 bits arithmetic for 32 bits hosts */ -static inline uint64_t get_HILO(CPUMIPSState *env) -{ - return ((uint64_t)(env->active_tc.HI[0]) << 32) | - (uint32_t)env->active_tc.LO[0]; -} - -static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) -{ - env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); - return env->active_tc.HI[0] = (int32_t)(HILO >> 32); -} - -static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) -{ - target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); - env->active_tc.HI[0] = (int32_t)(HILO >> 32); - return tmp; -} - -/* Multiplication variants of the vr54xx. */ -target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2)); -} - -target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (uint64_t)get_HILO(env) + - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)get_HILO(env) + - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (uint64_t)get_HILO(env) - - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)get_HILO(env) - - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); -} - -target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - static inline target_ulong bitswap(target_ulong v) { v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) | diff --git a/target/mips/tcg/vr54xx_helper.c b/target/mips/tcg/vr54xx_helper.c new file mode 100644 index 0000000000..2255bd1116 --- /dev/null +++ b/target/mips/tcg/vr54xx_helper.c @@ -0,0 +1,142 @@ +/* + * MIPS VR5432 emulation helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" + +/* 64 bits arithmetic for 32 bits hosts */ +static inline uint64_t get_HILO(CPUMIPSState *env) +{ + return ((uint64_t)(env->active_tc.HI[0]) << 32) | + (uint32_t)env->active_tc.LO[0]; +} + +static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) +{ + env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); + return env->active_tc.HI[0] = (int32_t)(HILO >> 32); +} + +static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) +{ + target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); + env->active_tc.HI[0] = (int32_t)(HILO >> 32); + return tmp; +} + +/* Multiplication variants of the vr54xx. */ +target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2)); +} + +target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (uint64_t)get_HILO(env) + (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)get_HILO(env) + (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (uint64_t)get_HILO(env) - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)get_HILO(env) - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); +} + +target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} -- cgit v1.2.3-55-g7522 From 9d0053923904215d95e8e5ab14b38bb792a0a68f Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 28 Jul 2021 13:18:48 +0200 Subject: target/mips: Introduce decodetree structure for NEC Vr54xx extension The decoder is called but doesn't decode anything. This will ease reviewing the next commit. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210801235926.3178085-3-f4bug@amsat.org> Reviewed-by: Richard Henderson --- target/mips/tcg/meson.build | 2 ++ target/mips/tcg/translate.c | 3 +++ target/mips/tcg/translate.h | 1 + target/mips/tcg/vr54xx.decode | 8 ++++++++ target/mips/tcg/vr54xx_translate.c | 19 +++++++++++++++++++ 5 files changed, 33 insertions(+) create mode 100644 target/mips/tcg/vr54xx.decode create mode 100644 target/mips/tcg/vr54xx_translate.c diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index ff618a159b..8f6f7508b6 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -2,6 +2,7 @@ gen = [ decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), + decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'), ] mips_ss.add(gen) @@ -19,6 +20,7 @@ mips_ss.add(files( 'translate_addr_const.c', 'txx9_translate.c', 'vr54xx_helper.c', + 'vr54xx_translate.c', )) mips_ss.add(when: 'TARGET_MIPS64', if_true: files( 'tx79_translate.c', diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 490add3fc1..3436363993 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16098,6 +16098,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { return; } + if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { + return; + } /* ISA extensions */ if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 791e3e2c7e..bb0a6b8d74 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -201,6 +201,7 @@ bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); #if defined(TARGET_MIPS64) bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); #endif +bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn); /* * Helpers for implementing sets of trans_* functions. diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode new file mode 100644 index 0000000000..f6b3e42c99 --- /dev/null +++ b/target/mips/tcg/vr54xx.decode @@ -0,0 +1,8 @@ +# MIPS VR5432 instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: VR5432 Microprocessor User’s Manual +# (Document Number U13751EU5V0UM00) diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c new file mode 100644 index 0000000000..13e58fdd8d --- /dev/null +++ b/target/mips/tcg/vr54xx_translate.c @@ -0,0 +1,19 @@ +/* + * VR5432 extensions translation routines + * + * Reference: VR5432 Microprocessor User’s Manual + * (Document Number U13751EU5V0UM00) + * + * Copyright (c) 2021 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" +#include "internal.h" + +/* Include the auto-generated decoder. */ +#include "decode-vr54xx.c.inc" -- cgit v1.2.3-55-g7522 From 5fa38eedbd0b3fad052a11c5efc8031a20ed9b25 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 28 Jul 2021 13:20:42 +0200 Subject: target/mips: Convert Vr54xx MACC* opcodes to decodetree Convert the following Integer Multiply-Accumulate opcodes: * MACC Multiply, accumulate, and move LO * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO Since all opcodes are generated using the same pattern, we add the gen_helper_mult_acc_t typedef and MULT_ACC() macro to remove boilerplate code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210808173018.90960-6-f4bug@amsat.org> --- target/mips/tcg/translate.c | 16 ---------------- target/mips/tcg/vr54xx.decode | 9 +++++++++ target/mips/tcg/vr54xx_translate.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 16 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 3436363993..fd8ffadf06 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -300,16 +300,12 @@ enum { enum { OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT, OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU, - OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT, - OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU, OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT, OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU, OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT, OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU, OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT, OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU, - OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT, - OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU, OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT, OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU, }; @@ -3780,12 +3776,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, case OPC_VR54XX_MULSU: gen_helper_mulsu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACC: - gen_helper_macc(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCU: - gen_helper_maccu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSAC: gen_helper_msac(t0, cpu_env, t0, t1); break; @@ -3804,12 +3794,6 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, case OPC_VR54XX_MULSHIU: gen_helper_mulshiu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MACCHI: - gen_helper_macchi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCHIU: - gen_helper_macchiu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSACHI: gen_helper_msachi(t0, cpu_env, t0, t1); break; diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index f6b3e42c99..73778f101a 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -6,3 +6,12 @@ # # Reference: VR5432 Microprocessor User’s Manual # (Document Number U13751EU5V0UM00) + +&r rs rt rd + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r + +MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd +MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd +MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c index 13e58fdd8d..0e2d460c98 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -17,3 +17,36 @@ /* Include the auto-generated decoder. */ #include "decode-vr54xx.c.inc" + +/* + * Integer Multiply-Accumulate Instructions + * + * MACC Multiply, accumulate, and move LO + * MACCHI Multiply, accumulate, and move HI + * MACCHIU Unsigned multiply, accumulate, and move HI + * MACCU Unsigned multiply, accumulate, and move LO + */ + +static bool trans_mult_acc(DisasContext *ctx, arg_r *a, + void (*gen_helper_mult_acc)(TCGv, TCGv_ptr, TCGv, TCGv)) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, a->rs); + gen_load_gpr(t1, a->rt); + + gen_helper_mult_acc(t0, cpu_env, t0, t1); + + gen_store_gpr(t0, a->rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return false; +} + +TRANS(MACC, trans_mult_acc, gen_helper_macc); +TRANS(MACCHI, trans_mult_acc, gen_helper_macchi); +TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu); +TRANS(MACCU, trans_mult_acc, gen_helper_maccu); -- cgit v1.2.3-55-g7522 From a5e2932068f1b09fa3be3b79a88f935b6e9620c3 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 28 Jul 2021 13:25:53 +0200 Subject: target/mips: Convert Vr54xx MUL* opcodes to decodetree Convert the following Integer Multiply-Accumulate opcodes: * MULHI Multiply and move HI * MULHIU Unsigned multiply and move HI * MULS Multiply, negate, and move LO * MULSHI Multiply, negate, and move HI * MULSHIU Unsigned multiply, negate, and move HI * MULSU Unsigned multiply, negate, and move LO Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210808173018.90960-7-f4bug@amsat.org> --- target/mips/tcg/translate.c | 24 ------------------------ target/mips/tcg/vr54xx.decode | 6 ++++++ target/mips/tcg/vr54xx_translate.c | 12 ++++++++++++ 3 files changed, 18 insertions(+), 24 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index fd8ffadf06..4b7f2d9ae8 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -298,14 +298,8 @@ enum { #define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) enum { - OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT, - OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU, OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT, OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU, - OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT, - OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU, - OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT, - OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU, OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT, OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU, }; @@ -3770,30 +3764,12 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, gen_load_gpr(t1, rt); switch (opc) { - case OPC_VR54XX_MULS: - gen_helper_muls(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSU: - gen_helper_mulsu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSAC: gen_helper_msac(t0, cpu_env, t0, t1); break; case OPC_VR54XX_MSACU: gen_helper_msacu(t0, cpu_env, t0, t1); break; - case OPC_VR54XX_MULHI: - gen_helper_mulhi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULHIU: - gen_helper_mulhiu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHI: - gen_helper_mulshi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHIU: - gen_helper_mulshiu(t0, cpu_env, t0, t1); - break; case OPC_VR54XX_MSACHI: gen_helper_msachi(t0, cpu_env, t0, t1); break; diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index 73778f101a..79bb5175ea 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -11,7 +11,13 @@ @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r +MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd +MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd +MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd +MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd +MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c index 0e2d460c98..9f35b2c7e5 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -25,6 +25,12 @@ * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO + * MULHI Multiply and move HI + * MULHIU Unsigned multiply and move HI + * MULS Multiply, negate, and move LO + * MULSHI Multiply, negate, and move HI + * MULSHIU Unsigned multiply, negate, and move HI + * MULSU Unsigned multiply, negate, and move LO */ static bool trans_mult_acc(DisasContext *ctx, arg_r *a, @@ -50,3 +56,9 @@ TRANS(MACC, trans_mult_acc, gen_helper_macc); TRANS(MACCHI, trans_mult_acc, gen_helper_macchi); TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu); TRANS(MACCU, trans_mult_acc, gen_helper_maccu); +TRANS(MULHI, trans_mult_acc, gen_helper_mulhi); +TRANS(MULHIU, trans_mult_acc, gen_helper_mulhiu); +TRANS(MULS, trans_mult_acc, gen_helper_muls); +TRANS(MULSHI, trans_mult_acc, gen_helper_mulshi); +TRANS(MULSHIU, trans_mult_acc, gen_helper_mulshiu); +TRANS(MULSU, trans_mult_acc, gen_helper_mulsu); -- cgit v1.2.3-55-g7522 From bf7720024c62c9e2707b11aa7fe178be691b2f35 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 28 Jul 2021 13:26:10 +0200 Subject: target/mips: Convert Vr54xx MSA* opcodes to decodetree Convert the following Integer Multiply-Accumulate opcodes: * MSAC Multiply, negate, accumulate, and move LO * MSACHI Multiply, negate, accumulate, and move HI * MSACHIU Unsigned multiply, negate, accumulate, and move HI * MSACU Unsigned multiply, negate, accumulate, and move LO Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210808173018.90960-8-f4bug@amsat.org> --- target/mips/tcg/translate.c | 55 ++------------------------------------ target/mips/tcg/vr54xx.decode | 4 +++ target/mips/tcg/vr54xx_translate.c | 8 ++++++ 3 files changed, 14 insertions(+), 53 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4b7f2d9ae8..30780deb96 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -294,16 +294,6 @@ enum { R6_OPC_SDBBP = 0x0e | OPC_SPECIAL, }; -/* Multiplication variants of the vr54xx. */ -#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) - -enum { - OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT, - OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU, - OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT, - OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU, -}; - /* REGIMM (rt field) opcodes */ #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16))) @@ -3754,40 +3744,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); } -static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) -{ - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); - - switch (opc) { - case OPC_VR54XX_MSAC: - gen_helper_msac(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACU: - gen_helper_msacu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHI: - gen_helper_msachi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHIU: - gen_helper_msachiu(t0, cpu_env, t0, t1); - break; - default: - MIPS_INVAL("mul vr54xx"); - gen_reserved_instruction(ctx); - goto out; - } - gen_store_gpr(t0, rd); - - out: - tcg_temp_free(t0); - tcg_temp_free(t1); -} - static void gen_cl(DisasContext *ctx, uint32_t opc, int rd, int rs) { @@ -14104,13 +14060,12 @@ static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx) static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) { - int rs, rt, rd, sa; + int rs, rt, rd; uint32_t op1; rs = (ctx->opcode >> 21) & 0x1f; rt = (ctx->opcode >> 16) & 0x1f; rd = (ctx->opcode >> 11) & 0x1f; - sa = (ctx->opcode >> 6) & 0x1f; op1 = MASK_SPECIAL(ctx->opcode); switch (op1) { @@ -14140,13 +14095,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_MULT: case OPC_MULTU: - if (sa) { - check_insn(ctx, INSN_VR54XX); - op1 = MASK_MUL_VR54XX(ctx->opcode); - gen_mul_vr54xx(ctx, op1, rd, rs, rt); - } else { - gen_muldiv(ctx, op1, rd & 3, rs, rt); - } + gen_muldiv(ctx, op1, rd & 3, rs, rt); break; case OPC_DIV: case OPC_DIVU: diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode index 79bb5175ea..4fc708d80a 100644 --- a/target/mips/tcg/vr54xx.decode +++ b/target/mips/tcg/vr54xx.decode @@ -15,9 +15,13 @@ MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd +MSAC 000000 ..... ..... ..... 00111011000 @rs_rt_rd +MSACU 000000 ..... ..... ..... 00111011001 @rs_rt_rd MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd +MSACHI 000000 ..... ..... ..... 01111011000 @rs_rt_rd +MSACHIU 000000 ..... ..... ..... 01111011001 @rs_rt_rd diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c index 9f35b2c7e5..3e2c98f2c6 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -25,6 +25,10 @@ * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO + * MSAC Multiply, negate, accumulate, and move LO + * MSACHI Multiply, negate, accumulate, and move HI + * MSACHIU Unsigned multiply, negate, accumulate, and move HI + * MSACU Unsigned multiply, negate, accumulate, and move LO * MULHI Multiply and move HI * MULHIU Unsigned multiply and move HI * MULS Multiply, negate, and move LO @@ -56,6 +60,10 @@ TRANS(MACC, trans_mult_acc, gen_helper_macc); TRANS(MACCHI, trans_mult_acc, gen_helper_macchi); TRANS(MACCHIU, trans_mult_acc, gen_helper_macchiu); TRANS(MACCU, trans_mult_acc, gen_helper_maccu); +TRANS(MSAC, trans_mult_acc, gen_helper_msac); +TRANS(MSACHI, trans_mult_acc, gen_helper_msachi); +TRANS(MSACHIU, trans_mult_acc, gen_helper_msachiu); +TRANS(MSACU, trans_mult_acc, gen_helper_msacu); TRANS(MULHI, trans_mult_acc, gen_helper_mulhi); TRANS(MULHIU, trans_mult_acc, gen_helper_mulhiu); TRANS(MULS, trans_mult_acc, gen_helper_muls); -- cgit v1.2.3-55-g7522 From 98d207cf9c232e6ac451b2aba24baa007956f578 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Fri, 13 Aug 2021 12:37:12 +0200 Subject: target/mips: Document Loongson-3A CPU definitions Document the cores on which each Loongson-3A CPU is based (see commit af868995e1b, "target/mips: Add Loongson-3 CPU definition"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Huacai Chen Message-Id: <20210813110149.1432692-2-f4bug@amsat.org> --- target/mips/cpu-defs.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index e03b2a998c..c6ab3af190 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -805,7 +805,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - .name = "Loongson-3A1000", + .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */ .CP0_PRid = 0x6305, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | @@ -835,7 +835,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - .name = "Loongson-3A4000", /* GS464V-based */ + .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */ .CP0_PRid = 0x14C000, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | -- cgit v1.2.3-55-g7522 From 71ed30b7d4c7bc7d8069eba601d7384e378f3024 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Fri, 13 Aug 2021 12:36:46 +0200 Subject: target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter 1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements 48 virtual address bits in each 64-bit segment, not 40. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Huacai Chen Message-Id: <20210813110149.1432692-3-f4bug@amsat.org> --- target/mips/cpu-defs.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index c6ab3af190..cbc45fcb0e 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -828,7 +828,7 @@ const mips_def_t mips_defs[] = (0x1 << FCR0_D) | (0x1 << FCR0_S), .CP1_fcr31 = 0, .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 42, + .SEGBITS = 48, .PABITS = 48, .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT, -- cgit v1.2.3-55-g7522 From c1feb46d12a7e7aeed804f2cca69f509c1bea8ef Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Mon, 16 Aug 2021 02:04:04 +0200 Subject: target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT We already call check_cp1_enabled() earlier in the "pre-conditions" checks for GSLWXC1 and GSLDXC1 in gen_loongson_lsdc2() prologue. Remove the duplicated calls. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Huacai Chen Message-Id: <20210816001031.1720432-1-f4bug@amsat.org> --- target/mips/tcg/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 30780deb96..a58d50e40e 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -4693,7 +4693,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, break; #endif case OPC_GSLWXC1: - check_cp1_enabled(ctx); gen_base_offset_addr(ctx, t0, rs, offset); if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); @@ -4706,7 +4705,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt, break; #if defined(TARGET_MIPS64) case OPC_GSLDXC1: - check_cp1_enabled(ctx); gen_base_offset_addr(ctx, t0, rs, offset); if (rd) { gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); -- cgit v1.2.3-55-g7522 From b24339bcd05b9d772f86c74732932bac98a15f4e Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Thu, 12 Aug 2021 15:45:45 +0200 Subject: target/mips: Remove gen_helper_0e3i() gen_helper_0e3i() is unused since commit 895c2d04359 ("target-mips: switch to AREG0 free mode"), remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210816205107.2051495-2-f4bug@amsat.org> --- target/mips/tcg/translate.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index a58d50e40e..c0f8a04b47 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1249,12 +1249,6 @@ TCGv_i64 fpu_f64[32]; tcg_temp_free_i32(helper_tmp); \ } while (0) -#define gen_helper_0e3i(name, arg1, arg2, arg3, arg4) do { \ - TCGv_i32 helper_tmp = tcg_const_i32(arg4); \ - gen_helper_##name(cpu_env, arg1, arg2, arg3, helper_tmp); \ - tcg_temp_free_i32(helper_tmp); \ - } while (0) - #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 -- cgit v1.2.3-55-g7522 From 53152abfc148ebfb7843ef3596f4be5bc8e5eff9 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Thu, 12 Aug 2021 15:41:40 +0200 Subject: target/mips: Remove gen_helper_1e2i() gen_helper_1e2i() is unused since commit 33a07fa2db6 ("target/mips: reimplement SC instruction emulation and use cmpxchg"), remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210816205107.2051495-3-f4bug@amsat.org> --- target/mips/tcg/translate.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index c0f8a04b47..4b689a54ab 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1243,12 +1243,6 @@ TCGv_i64 fpu_f64[32]; tcg_temp_free_i32(helper_tmp); \ } while (0) -#define gen_helper_1e2i(name, ret, arg1, arg2, arg3) do { \ - TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ - gen_helper_##name(ret, cpu_env, arg1, arg2, helper_tmp); \ - tcg_temp_free_i32(helper_tmp); \ - } while (0) - #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 -- cgit v1.2.3-55-g7522 From 78bdd3886577ce4f3e573685b155622e19bcca38 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sun, 15 Aug 2021 15:51:49 +0200 Subject: target/mips: Use tcg_constant_i32() in gen_helper_0e2i() $rt register is used read-only, so we can replace tcg_const_i32() temporary by tcg_constant_i32(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210816205107.2051495-4-f4bug@amsat.org> --- target/mips/tcg/translate.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4b689a54ab..a6df9beb67 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -9072,12 +9072,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, break; case 3: /* XXX: For now we support only a single FPU context. */ - { - TCGv_i32 fs_tmp = tcg_const_i32(rd); - - gen_helper_0e2i(ctc1, t0, fs_tmp, rt); - tcg_temp_free_i32(fs_tmp); - } + gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt); /* Stop translation as we may have changed hflags */ ctx->base.is_jmp = DISAS_STOP; break; @@ -9694,12 +9689,7 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) case OPC_CTC1: gen_load_gpr(t0, rt); save_cpu_state(ctx, 0); - { - TCGv_i32 fs_tmp = tcg_const_i32(fs); - - gen_helper_0e2i(ctc1, t0, fs_tmp, rt); - tcg_temp_free_i32(fs_tmp); - } + gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt); /* Stop translation as we may have changed hflags */ ctx->base.is_jmp = DISAS_STOP; break; -- cgit v1.2.3-55-g7522 From 26fe92763aaf3b0d704fbdb32daf434147dc6ca7 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sun, 15 Aug 2021 15:07:40 +0200 Subject: target/mips: Simplify gen_helper() macros by using tcg_constant_i32() In all call sites the last argument is always used as a read-only value, so we can replace tcg_const_i32() temporary by tcg_constant_i32(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210816205107.2051495-5-f4bug@amsat.org> --- target/mips/tcg/translate.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index a6df9beb67..3417fc433f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1214,33 +1214,23 @@ TCGv_i64 fpu_f64[32]; #include "exec/gen-icount.h" #define gen_helper_0e0i(name, arg) do { \ - TCGv_i32 helper_tmp = tcg_const_i32(arg); \ - gen_helper_##name(cpu_env, helper_tmp); \ - tcg_temp_free_i32(helper_tmp); \ + gen_helper_##name(cpu_env, tcg_constant_i32(arg)); \ } while (0) #define gen_helper_0e1i(name, arg1, arg2) do { \ - TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ - gen_helper_##name(cpu_env, arg1, helper_tmp); \ - tcg_temp_free_i32(helper_tmp); \ + gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \ } while (0) #define gen_helper_1e0i(name, ret, arg1) do { \ - TCGv_i32 helper_tmp = tcg_const_i32(arg1); \ - gen_helper_##name(ret, cpu_env, helper_tmp); \ - tcg_temp_free_i32(helper_tmp); \ + gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \ } while (0) #define gen_helper_1e1i(name, ret, arg1, arg2) do { \ - TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ - gen_helper_##name(ret, cpu_env, arg1, helper_tmp); \ - tcg_temp_free_i32(helper_tmp); \ + gen_helper_##name(ret, cpu_env, arg1, tcg_constant_i32(arg2));\ } while (0) #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \ - TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ - gen_helper_##name(cpu_env, arg1, arg2, helper_tmp); \ - tcg_temp_free_i32(helper_tmp); \ + gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\ } while (0) #define DISAS_STOP DISAS_TARGET_0 -- cgit v1.2.3-55-g7522 From a1b4b060d756dbc2d221d340b7adbc3e694e06d6 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sun, 15 Aug 2021 15:46:09 +0200 Subject: target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros gen_helper_1e1i() is one-line long and is used in one place: simply inline it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210816205107.2051495-6-f4bug@amsat.org> --- target/mips/tcg/translate.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 3417fc433f..db7fc75d93 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1225,10 +1225,6 @@ TCGv_i64 fpu_f64[32]; gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \ } while (0) -#define gen_helper_1e1i(name, ret, arg1, arg2) do { \ - gen_helper_##name(ret, cpu_env, arg1, tcg_constant_i32(arg2));\ - } while (0) - #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \ gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\ } while (0) @@ -1991,7 +1987,7 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ DisasContext *ctx) \ { \ - gen_helper_1e1i(insn, ret, arg1, mem_idx); \ + gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \ } #endif OP_LD_ATOMIC(ll, ld32s); -- cgit v1.2.3-55-g7522 From ae71abadd58037dd457f021f9be381e32f1815ec Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sun, 15 Aug 2021 15:48:58 +0200 Subject: target/mips: Inline gen_helper_0e0i() gen_helper_0e0i() is one-line long and is only used twice: simply inline it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210816205107.2051495-7-f4bug@amsat.org> --- target/mips/tcg/translate.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index db7fc75d93..c515a337eb 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1213,10 +1213,6 @@ TCGv_i64 fpu_f64[32]; #include "exec/gen-icount.h" -#define gen_helper_0e0i(name, arg) do { \ - gen_helper_##name(cpu_env, tcg_constant_i32(arg)); \ - } while (0) - #define gen_helper_0e1i(name, arg1, arg2) do { \ gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \ } while (0) @@ -1378,7 +1374,7 @@ void generate_exception_err(DisasContext *ctx, int excp, int err) void generate_exception(DisasContext *ctx, int excp) { - gen_helper_0e0i(raise_exception, excp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); } void generate_exception_end(DisasContext *ctx, int excp) @@ -14188,7 +14184,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) MIPS_INVAL("PMON / selsl"); gen_reserved_instruction(ctx); #else - gen_helper_0e0i(pmon, sa); + gen_helper_pmon(cpu_env, tcg_constant_i32(sa)); #endif break; case OPC_SYSCALL: -- cgit v1.2.3-55-g7522 From a8b18de7f5f8283633e5fc3378fbd6d0c9f4a1ae Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sun, 15 Aug 2021 15:56:13 +0200 Subject: target/mips: Use tcg_constant_i32() in generate_exception_err() excp/err are temporaries input, so we can replace tcg_const_i32() calls by tcg_constant_i32() equivalent. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210816205107.2051495-8-f4bug@amsat.org> --- target/mips/tcg/translate.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index c515a337eb..93b72c994f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1363,12 +1363,9 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx) void generate_exception_err(DisasContext *ctx, int excp, int err) { - TCGv_i32 texcp = tcg_const_i32(excp); - TCGv_i32 terr = tcg_const_i32(err); save_cpu_state(ctx, 1); - gen_helper_raise_exception_err(cpu_env, texcp, terr); - tcg_temp_free_i32(terr); - tcg_temp_free_i32(texcp); + gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(err)); ctx->base.is_jmp = DISAS_NORETURN; } -- cgit v1.2.3-55-g7522 From 761533fc9a8df2e7d276b7e1fc22cad7d0fd0352 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sun, 15 Aug 2021 16:02:41 +0200 Subject: target/mips: Define gen_helper() macros in translate.h To be able to split some code calling the gen_helper() macros out of the huge translate.c, we need to define them in the 'translate.h' local header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210816205107.2051495-9-f4bug@amsat.org> --- target/mips/tcg/translate.c | 12 ------------ target/mips/tcg/translate.h | 12 ++++++++++++ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 93b72c994f..40cb1fc950 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1213,18 +1213,6 @@ TCGv_i64 fpu_f64[32]; #include "exec/gen-icount.h" -#define gen_helper_0e1i(name, arg1, arg2) do { \ - gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \ - } while (0) - -#define gen_helper_1e0i(name, ret, arg1) do { \ - gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \ - } while (0) - -#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \ - gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\ - } while (0) - #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index bb0a6b8d74..eac01a8118 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -113,6 +113,18 @@ enum { OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4, }; +#define gen_helper_0e1i(name, arg1, arg2) do { \ + gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \ + } while (0) + +#define gen_helper_1e0i(name, ret, arg1) do { \ + gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \ + } while (0) + +#define gen_helper_0e2i(name, arg1, arg2, arg3) do { \ + gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\ + } while (0) + void generate_exception(DisasContext *ctx, int excp); void generate_exception_err(DisasContext *ctx, int excp, int err); void generate_exception_end(DisasContext *ctx, int excp); -- cgit v1.2.3-55-g7522 From 5b3cc34c346e216c81f0750f586a016c33f2e08f Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 18 Aug 2021 12:10:53 +0200 Subject: target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. As a first step, inline the GET_OFFSET() macro, calling cpu_is_bigendian() to get the 'direction' of the offset. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210818215517.2560994-2-f4bug@amsat.org> --- target/mips/tcg/ldst_helper.c | 55 ++++++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 22 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index d42812b8a6..8d1dfea676 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -52,31 +52,36 @@ HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) #endif /* !CONFIG_USER_ONLY */ +static inline bool cpu_is_bigendian(CPUMIPSState *env) +{ + return extract32(env->CP0_Config0, CP0C0_BE, 1); +} + #ifdef TARGET_WORDS_BIGENDIAN #define GET_LMASK(v) ((v) & 3) -#define GET_OFFSET(addr, offset) (addr + (offset)) #else #define GET_LMASK(v) (((v) & 3) ^ 3) -#define GET_OFFSET(addr, offset) (addr - (offset)) #endif void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { + int dir = cpu_is_bigendian(env) ? 1 : -1; + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); if (GET_LMASK(arg2) <= 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), + cpu_stb_mmuidx_ra(env, arg2 + 1 * dir, (uint8_t)(arg1 >> 16), mem_idx, GETPC()); } if (GET_LMASK(arg2) <= 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), + cpu_stb_mmuidx_ra(env, arg2 + 2 * dir, (uint8_t)(arg1 >> 8), mem_idx, GETPC()); } if (GET_LMASK(arg2) == 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, + cpu_stb_mmuidx_ra(env, arg2 + 3 * dir, (uint8_t)arg1, mem_idx, GETPC()); } } @@ -84,20 +89,22 @@ void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { + int dir = cpu_is_bigendian(env) ? 1 : -1; + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); if (GET_LMASK(arg2) >= 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + cpu_stb_mmuidx_ra(env, arg2 - 1 * dir, (uint8_t)(arg1 >> 8), mem_idx, GETPC()); } if (GET_LMASK(arg2) >= 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + cpu_stb_mmuidx_ra(env, arg2 - 2 * dir, (uint8_t)(arg1 >> 16), mem_idx, GETPC()); } if (GET_LMASK(arg2) == 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + cpu_stb_mmuidx_ra(env, arg2 - 3 * dir, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); } } @@ -116,40 +123,42 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { + int dir = cpu_is_bigendian(env) ? 1 : -1; + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); if (GET_LMASK64(arg2) <= 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), + cpu_stb_mmuidx_ra(env, arg2 + 1 * dir, (uint8_t)(arg1 >> 48), mem_idx, GETPC()); } if (GET_LMASK64(arg2) <= 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), + cpu_stb_mmuidx_ra(env, arg2 + 2 * dir, (uint8_t)(arg1 >> 40), mem_idx, GETPC()); } if (GET_LMASK64(arg2) <= 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), + cpu_stb_mmuidx_ra(env, arg2 + 3 * dir, (uint8_t)(arg1 >> 32), mem_idx, GETPC()); } if (GET_LMASK64(arg2) <= 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), + cpu_stb_mmuidx_ra(env, arg2 + 4 * dir, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); } if (GET_LMASK64(arg2) <= 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), + cpu_stb_mmuidx_ra(env, arg2 + 5 * dir, (uint8_t)(arg1 >> 16), mem_idx, GETPC()); } if (GET_LMASK64(arg2) <= 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), + cpu_stb_mmuidx_ra(env, arg2 + 6 * dir, (uint8_t)(arg1 >> 8), mem_idx, GETPC()); } if (GET_LMASK64(arg2) <= 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, + cpu_stb_mmuidx_ra(env, arg2 + 7 * dir, (uint8_t)arg1, mem_idx, GETPC()); } } @@ -157,40 +166,42 @@ void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { + int dir = cpu_is_bigendian(env) ? 1 : -1; + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); if (GET_LMASK64(arg2) >= 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + cpu_stb_mmuidx_ra(env, arg2 - 1 * dir, (uint8_t)(arg1 >> 8), mem_idx, GETPC()); } if (GET_LMASK64(arg2) >= 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + cpu_stb_mmuidx_ra(env, arg2 - 2 * dir, (uint8_t)(arg1 >> 16), mem_idx, GETPC()); } if (GET_LMASK64(arg2) >= 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + cpu_stb_mmuidx_ra(env, arg2 - 3 * dir, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); } if (GET_LMASK64(arg2) >= 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), + cpu_stb_mmuidx_ra(env, arg2 - 4 * dir, (uint8_t)(arg1 >> 32), mem_idx, GETPC()); } if (GET_LMASK64(arg2) >= 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), + cpu_stb_mmuidx_ra(env, arg2 - 5 * dir, (uint8_t)(arg1 >> 40), mem_idx, GETPC()); } if (GET_LMASK64(arg2) >= 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), + cpu_stb_mmuidx_ra(env, arg2 - 6 * dir, (uint8_t)(arg1 >> 48), mem_idx, GETPC()); } if (GET_LMASK64(arg2) == 7) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), + cpu_stb_mmuidx_ra(env, arg2 - 7 * dir, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); } } -- cgit v1.2.3-55-g7522 From 4885b99a6e05d16f40af18a062a5cb45fa92ec27 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 18 Aug 2021 12:11:30 +0200 Subject: target/mips: Replace GET_LMASK() macro by get_lmask(32) function The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. Replace the GET_LMASK() macro by an inlined get_lmask() function, passing CPUMIPSState and the word size as argument. We can remove one use of the TARGET_WORDS_BIGENDIAN definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210818215517.2560994-3-f4bug@amsat.org> --- target/mips/tcg/ldst_helper.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index 8d1dfea676..054459703a 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -57,30 +57,39 @@ static inline bool cpu_is_bigendian(CPUMIPSState *env) return extract32(env->CP0_Config0, CP0C0_BE, 1); } -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK(v) ((v) & 3) -#else -#define GET_LMASK(v) (((v) & 3) ^ 3) -#endif +static inline target_ulong get_lmask(CPUMIPSState *env, + target_ulong value, unsigned bits) +{ + unsigned mask = (bits / BITS_PER_BYTE) - 1; + + value &= mask; + + if (!cpu_is_bigendian(env)) { + value ^= mask; + } + + return value; +} void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { + target_ulong lmask = get_lmask(env, arg2, 32); int dir = cpu_is_bigendian(env) ? 1 : -1; cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); - if (GET_LMASK(arg2) <= 2) { + if (lmask <= 2) { cpu_stb_mmuidx_ra(env, arg2 + 1 * dir, (uint8_t)(arg1 >> 16), mem_idx, GETPC()); } - if (GET_LMASK(arg2) <= 1) { + if (lmask <= 1) { cpu_stb_mmuidx_ra(env, arg2 + 2 * dir, (uint8_t)(arg1 >> 8), mem_idx, GETPC()); } - if (GET_LMASK(arg2) == 0) { + if (lmask == 0) { cpu_stb_mmuidx_ra(env, arg2 + 3 * dir, (uint8_t)arg1, mem_idx, GETPC()); } @@ -89,21 +98,22 @@ void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { + target_ulong lmask = get_lmask(env, arg2, 32); int dir = cpu_is_bigendian(env) ? 1 : -1; cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - if (GET_LMASK(arg2) >= 1) { + if (lmask >= 1) { cpu_stb_mmuidx_ra(env, arg2 - 1 * dir, (uint8_t)(arg1 >> 8), mem_idx, GETPC()); } - if (GET_LMASK(arg2) >= 2) { + if (lmask >= 2) { cpu_stb_mmuidx_ra(env, arg2 - 2 * dir, (uint8_t)(arg1 >> 16), mem_idx, GETPC()); } - if (GET_LMASK(arg2) == 3) { + if (lmask == 3) { cpu_stb_mmuidx_ra(env, arg2 - 3 * dir, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); } -- cgit v1.2.3-55-g7522 From 23a04dcdf6fa6b34933778b16ee8200027dc6e68 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 18 Aug 2021 12:11:41 +0200 Subject: target/mips: Replace GET_LMASK64() macro by get_lmask(64) function The target endianess information is stored in the BigEndian bit of the Config0 register in CP0. Replace the GET_LMASK() macro by an inlined get_lmask() function, passing CPUMIPSState and the word size as argument. We can remove another use of the TARGET_WORDS_BIGENDIAN definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210818215517.2560994-4-f4bug@amsat.org> --- target/mips/tcg/ldst_helper.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index 054459703a..d0bd0267b2 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -124,50 +124,46 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, * "half" load and stores. We must do the memory access inline, * or fault handling won't work. */ -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK64(v) ((v) & 7) -#else -#define GET_LMASK64(v) (((v) & 7) ^ 7) -#endif void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { + target_ulong lmask = get_lmask(env, arg2, 64); int dir = cpu_is_bigendian(env) ? 1 : -1; cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); - if (GET_LMASK64(arg2) <= 6) { + if (lmask <= 6) { cpu_stb_mmuidx_ra(env, arg2 + 1 * dir, (uint8_t)(arg1 >> 48), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) <= 5) { + if (lmask <= 5) { cpu_stb_mmuidx_ra(env, arg2 + 2 * dir, (uint8_t)(arg1 >> 40), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) <= 4) { + if (lmask <= 4) { cpu_stb_mmuidx_ra(env, arg2 + 3 * dir, (uint8_t)(arg1 >> 32), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) <= 3) { + if (lmask <= 3) { cpu_stb_mmuidx_ra(env, arg2 + 4 * dir, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) <= 2) { + if (lmask <= 2) { cpu_stb_mmuidx_ra(env, arg2 + 5 * dir, (uint8_t)(arg1 >> 16), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) <= 1) { + if (lmask <= 1) { cpu_stb_mmuidx_ra(env, arg2 + 6 * dir, (uint8_t)(arg1 >> 8), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) <= 0) { + if (lmask <= 0) { cpu_stb_mmuidx_ra(env, arg2 + 7 * dir, (uint8_t)arg1, mem_idx, GETPC()); } @@ -176,41 +172,42 @@ void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { + target_ulong lmask = get_lmask(env, arg2, 64); int dir = cpu_is_bigendian(env) ? 1 : -1; cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - if (GET_LMASK64(arg2) >= 1) { + if (lmask >= 1) { cpu_stb_mmuidx_ra(env, arg2 - 1 * dir, (uint8_t)(arg1 >> 8), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) >= 2) { + if (lmask >= 2) { cpu_stb_mmuidx_ra(env, arg2 - 2 * dir, (uint8_t)(arg1 >> 16), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) >= 3) { + if (lmask >= 3) { cpu_stb_mmuidx_ra(env, arg2 - 3 * dir, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) >= 4) { + if (lmask >= 4) { cpu_stb_mmuidx_ra(env, arg2 - 4 * dir, (uint8_t)(arg1 >> 32), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) >= 5) { + if (lmask >= 5) { cpu_stb_mmuidx_ra(env, arg2 - 5 * dir, (uint8_t)(arg1 >> 40), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) >= 6) { + if (lmask >= 6) { cpu_stb_mmuidx_ra(env, arg2 - 6 * dir, (uint8_t)(arg1 >> 48), mem_idx, GETPC()); } - if (GET_LMASK64(arg2) == 7) { + if (lmask == 7) { cpu_stb_mmuidx_ra(env, arg2 - 7 * dir, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); } -- cgit v1.2.3-55-g7522 From 0cfd392d7b419cdbe5284b8227d95ab3daaea860 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 18 Aug 2021 12:12:12 +0200 Subject: target/mips: Store CP0_Config0 in DisasContext Most TCG helpers only have access to a DisasContext pointer, not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0 in DisasContext so we can access it from TCG helpers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210818164321.2474534-5-f4bug@amsat.org> --- target/mips/tcg/translate.c | 1 + target/mips/tcg/translate.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 40cb1fc950..ac97f5f6f0 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15979,6 +15979,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; ctx->saved_pc = -1; ctx->insn_flags = env->insn_flags; + ctx->CP0_Config0 = env->CP0_Config0; ctx->CP0_Config1 = env->CP0_Config1; ctx->CP0_Config2 = env->CP0_Config2; ctx->CP0_Config3 = env->CP0_Config3; diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index eac01a8118..4b4fa2c207 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -18,6 +18,7 @@ typedef struct DisasContext { target_ulong page_start; uint32_t opcode; uint64_t insn_flags; + int32_t CP0_Config0; int32_t CP0_Config1; int32_t CP0_Config2; int32_t CP0_Config3; -- cgit v1.2.3-55-g7522 From bf78469cc8ddb117b6db4a353e59fb4664a96de4 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 18 Aug 2021 12:13:02 +0200 Subject: target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() Add the inlined cpu_is_bigendian() function in "translate.h". Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to cpu_is_bigendian(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210818164321.2474534-6-f4bug@amsat.org> --- target/mips/tcg/nanomips_translate.c.inc | 20 ++++----- target/mips/tcg/translate.c | 70 ++++++++++++++++---------------- target/mips/tcg/translate.h | 5 +++ 3 files changed, 50 insertions(+), 45 deletions(-) diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 09e64a6948..a66ae26796 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -999,11 +999,11 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, gen_base_offset_addr(ctx, taddr, base, offset); tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx); -#ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_extr_i64_tl(tmp2, tmp1, tval); -#else - tcg_gen_extr_i64_tl(tmp1, tmp2, tval); -#endif + if (cpu_is_bigendian(ctx)) { + tcg_gen_extr_i64_tl(tmp2, tmp1, tval); + } else { + tcg_gen_extr_i64_tl(tmp1, tmp2, tval); + } gen_store_gpr(tmp1, reg1); tcg_temp_free(tmp1); gen_store_gpr(tmp2, reg2); @@ -1035,11 +1035,11 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, gen_load_gpr(tmp1, reg1); gen_load_gpr(tmp2, reg2); -#ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_concat_tl_i64(tval, tmp2, tmp1); -#else - tcg_gen_concat_tl_i64(tval, tmp1, tmp2); -#endif + if (cpu_is_bigendian(ctx)) { + tcg_gen_concat_tl_i64(tval, tmp2, tmp1); + } else { + tcg_gen_concat_tl_i64(tval, tmp1, tmp2); + } tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index ac97f5f6f0..6f4a9a839c 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -2048,9 +2048,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, */ tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 7); -#ifndef TARGET_WORDS_BIGENDIAN - tcg_gen_xori_tl(t1, t1, 7); -#endif + if (!cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, 7); + } tcg_gen_shli_tl(t1, t1, 3); tcg_gen_andi_tl(t0, t0, ~7); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ); @@ -2072,9 +2072,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, */ tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 7); -#ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_xori_tl(t1, t1, 7); -#endif + if (cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, 7); + } tcg_gen_shli_tl(t1, t1, 3); tcg_gen_andi_tl(t0, t0, ~7); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEQ); @@ -2153,9 +2153,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, */ tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 3); -#ifndef TARGET_WORDS_BIGENDIAN - tcg_gen_xori_tl(t1, t1, 3); -#endif + if (!cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, 3); + } tcg_gen_shli_tl(t1, t1, 3); tcg_gen_andi_tl(t0, t0, ~3); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL); @@ -2181,9 +2181,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, */ tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 3); -#ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_xori_tl(t1, t1, 3); -#endif + if (cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, 3); + } tcg_gen_shli_tl(t1, t1, 3); tcg_gen_andi_tl(t0, t0, ~3); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL); @@ -4400,9 +4400,9 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, t1 = tcg_temp_new(); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 3); -#ifndef TARGET_WORDS_BIGENDIAN - tcg_gen_xori_tl(t1, t1, 3); -#endif + if (!cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, 3); + } tcg_gen_shli_tl(t1, t1, 3); tcg_gen_andi_tl(t0, t0, ~3); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); @@ -4430,9 +4430,9 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, t1 = tcg_temp_new(); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 3); -#ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_xori_tl(t1, t1, 3); -#endif + if (cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, 3); + } tcg_gen_shli_tl(t1, t1, 3); tcg_gen_andi_tl(t0, t0, ~3); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); @@ -4462,9 +4462,9 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, t1 = tcg_temp_new(); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 7); -#ifndef TARGET_WORDS_BIGENDIAN - tcg_gen_xori_tl(t1, t1, 7); -#endif + if (!cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, 7); + } tcg_gen_shli_tl(t1, t1, 3); tcg_gen_andi_tl(t0, t0, ~7); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); @@ -4484,9 +4484,9 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt, t1 = tcg_temp_new(); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); tcg_gen_andi_tl(t1, t0, 7); -#ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_xori_tl(t1, t1, 7); -#endif + if (cpu_is_bigendian(ctx)) { + tcg_gen_xori_tl(t1, t1, 7); + } tcg_gen_shli_tl(t1, t1, 3); tcg_gen_andi_tl(t0, t0, ~7); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); @@ -11409,17 +11409,17 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, gen_set_label(l1); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); tcg_temp_free(t0); -#ifdef TARGET_WORDS_BIGENDIAN - gen_load_fpr32(ctx, fp, fs); - gen_load_fpr32h(ctx, fph, ft); - gen_store_fpr32h(ctx, fp, fd); - gen_store_fpr32(ctx, fph, fd); -#else - gen_load_fpr32h(ctx, fph, fs); - gen_load_fpr32(ctx, fp, ft); - gen_store_fpr32(ctx, fph, fd); - gen_store_fpr32h(ctx, fp, fd); -#endif + if (cpu_is_bigendian(ctx)) { + gen_load_fpr32(ctx, fp, fs); + gen_load_fpr32h(ctx, fph, ft); + gen_store_fpr32h(ctx, fp, fd); + gen_store_fpr32(ctx, fph, fd); + } else { + gen_load_fpr32h(ctx, fph, fs); + gen_load_fpr32(ctx, fp, ft); + gen_store_fpr32(ctx, fph, fd); + gen_store_fpr32h(ctx, fp, fd); + } gen_set_label(l2); tcg_temp_free_i32(fp); tcg_temp_free_i32(fph); diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 4b4fa2c207..6111493651 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -224,4 +224,9 @@ bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn); static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { return FUNC(ctx, a, __VA_ARGS__); } +static inline bool cpu_is_bigendian(DisasContext *ctx) +{ + return extract32(ctx->CP0_Config0, CP0C0_BE, 1); +} + #endif -- cgit v1.2.3-55-g7522