From 513eb437aef7687ad1963d935ffb884fff3c4775 Mon Sep 17 00:00:00 2001 From: Rahul Pathak Date: Wed, 24 Aug 2022 20:22:55 +0530 Subject: target/riscv: Remove sideleg and sedeleg sideleg and sedeleg csrs are not part of riscv isa spec anymore, these csrs were part of N extension which is removed from the riscv isa specification. These commits removed all traces of these csrs from riscv spec (https://github.com/riscv/riscv-isa-manual) - commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)") commit b6cade07034d ("Remove N extension chapter for now") Signed-off-by: Rahul Pathak Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com> Signed-off-by: Alistair Francis --- disas/riscv.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'disas') diff --git a/disas/riscv.c b/disas/riscv.c index 489c2ae5e8..f107d94c4c 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1304,8 +1304,6 @@ static const char *csr_name(int csrno) case 0x0043: return "utval"; case 0x0044: return "uip"; case 0x0100: return "sstatus"; - case 0x0102: return "sedeleg"; - case 0x0103: return "sideleg"; case 0x0104: return "sie"; case 0x0105: return "stvec"; case 0x0106: return "scounteren"; -- cgit v1.2.3-55-g7522