From b14df228d7c4fe6e86e7f8a4998e9ccf4967b678 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Fri, 1 Jul 2022 08:29:17 +0900 Subject: docs/system: openrisc: Add OpenRISC documentation Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- docs/system/openrisc/cpu-features.rst | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 docs/system/openrisc/cpu-features.rst (limited to 'docs/system/openrisc/cpu-features.rst') diff --git a/docs/system/openrisc/cpu-features.rst b/docs/system/openrisc/cpu-features.rst new file mode 100644 index 0000000000..aeb65e22ff --- /dev/null +++ b/docs/system/openrisc/cpu-features.rst @@ -0,0 +1,15 @@ +CPU Features +============ + +The QEMU emulation of the OpenRISC architecture provides following built in +features. + +- Shadow GPRs +- MMU TLB with 128 entries, 1 way +- Power Management (PM) +- Programmable Interrupt Controller (PIC) +- Tick Timer + +These features are on by default and the presence can be confirmed by checking +the contents of the Unit Presence Register (``UPR``) and CPU Configuration +Register (``CPUCFGR``). -- cgit v1.2.3-55-g7522