From 2ecf17264debe1bc3399fe587690c78d03e8401b Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Tue, 9 Mar 2021 12:01:28 +0100 Subject: hw/misc: Add a basic Aspeed LPC controller model This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by: Cédric Le Goater --- docs/system/arm/aspeed.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs') diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 8972aa3f7b..d1fb8f25b3 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -48,6 +48,7 @@ Supported devices * UART * Ethernet controllers * Front LEDs (PCA9552 on I2C bus) + * LPC Peripheral Controller (a subset of subdevices are supported) Missing devices @@ -56,7 +57,6 @@ Missing devices * Coprocessor support * ADC (out of tree implementation) * PWM and Fan Controller - * LPC Bus Controller * Slave GPIO Controller * Super I/O Controller * Hash/Crypto Engine -- cgit v1.2.3-55-g7522