From 41c4fb94aa8a6a16bd107687cd3b5204c68a4042 Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Fri, 15 Mar 2019 11:12:28 +0000 Subject: hw/arm/virt-acpi-build: Fix SMMUv3 GSIV values The GSIV numbers of the SPI based interrupts is not correct as ARM_SPI_BASE was not added to the irqmap[VIRT_SMMU] value. So this may collide with VIRTIO_MMIO irq window. Signed-off-by: Eric Auger Message-id: 20190312091031.5185-1-eric.auger@redhat.com Reviewed-by: Shannon Zhao Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/arm') diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index d7e2e4885b..aa02d8d74e 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -405,7 +405,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) its->identifiers[0] = 0; /* MADT translation_id */ if (vms->iommu == VIRT_IOMMU_SMMUV3) { - int irq = vms->irqmap[VIRT_SMMU]; + int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; /* SMMUv3 node */ smmu_offset = iort_node_offset + node_size; -- cgit v1.2.3-55-g7522