From a8fb0a500a695104cda5837b7aba93dee3abddde Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 1 Sep 2020 09:39:00 +0800 Subject: hw/char: Add Microchip PolarFire SoC MMUART emulation Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing ns16550 model. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/char/Kconfig | 3 ++ hw/char/mchp_pfsoc_mmuart.c | 86 +++++++++++++++++++++++++++++++++++++++++++++ hw/char/meson.build | 1 + 3 files changed, 90 insertions(+) create mode 100644 hw/char/mchp_pfsoc_mmuart.c (limited to 'hw/char') diff --git a/hw/char/Kconfig b/hw/char/Kconfig index b7e0e4d5fa..1d645554c7 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -52,3 +52,6 @@ config RENESAS_SCI config AVR_USART bool + +config MCHP_PFSOC_MMUART + bool diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c new file mode 100644 index 0000000000..8a002b0a19 --- /dev/null +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -0,0 +1,86 @@ +/* + * Microchip PolarFire SoC MMUART emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "chardev/char.h" +#include "exec/address-spaces.h" +#include "hw/char/mchp_pfsoc_mmuart.h" + +static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size) +{ + MchpPfSoCMMUartState *s = opaque; + + if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n", + __func__, addr); + return 0; + } + + return s->reg[addr / sizeof(uint32_t)]; +} + +static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + MchpPfSoCMMUartState *s = opaque; + uint32_t val32 = (uint32_t)value; + + if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx + " v=0x%x\n", __func__, addr, val32); + return; + } + + s->reg[addr / sizeof(uint32_t)] = val32; +} + +static const MemoryRegionOps mchp_pfsoc_mmuart_ops = { + .read = mchp_pfsoc_mmuart_read, + .write = mchp_pfsoc_mmuart_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, + hwaddr base, qemu_irq irq, Chardev *chr) +{ + MchpPfSoCMMUartState *s; + + s = g_new0(MchpPfSoCMMUartState, 1); + + memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, + "mchp.pfsoc.mmuart", 0x1000); + + s->base = base; + s->irq = irq; + + s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr, + DEVICE_LITTLE_ENDIAN); + + memory_region_add_subregion(sysmem, base + 0x20, &s->iomem); + + return s; +} diff --git a/hw/char/meson.build b/hw/char/meson.build index e888215145..ae27932d00 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -32,6 +32,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c')) softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c')) softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c')) +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c')) specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c')) specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c')) -- cgit v1.2.3-55-g7522 From 70eb9f9cd1c0b519b31df8ab08ee2198b0e16176 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 3 Sep 2020 18:40:18 +0800 Subject: hw/riscv: Move riscv_htif model to hw/char This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move riscv_htif model to hw/char directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/char/Kconfig | 3 + hw/char/meson.build | 1 + hw/char/riscv_htif.c | 261 ++++++++++++++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 3 - hw/riscv/meson.build | 1 - hw/riscv/riscv_htif.c | 261 ------------------------------------------ hw/riscv/spike.c | 2 +- include/hw/char/riscv_htif.h | 59 ++++++++++ include/hw/riscv/riscv_htif.h | 59 ---------- 9 files changed, 325 insertions(+), 325 deletions(-) create mode 100644 hw/char/riscv_htif.c delete mode 100644 hw/riscv/riscv_htif.c create mode 100644 include/hw/char/riscv_htif.h delete mode 100644 include/hw/riscv/riscv_htif.h (limited to 'hw/char') diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 1d645554c7..91da92f617 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -1,6 +1,9 @@ config ESCC bool +config HTIF + bool + config PARALLEL bool default y diff --git a/hw/char/meson.build b/hw/char/meson.build index ae27932d00..3db623eeec 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -34,6 +34,7 @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c')) softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c')) +specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c')) specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c')) specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c')) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c new file mode 100644 index 0000000000..ba1af1cfc4 --- /dev/null +++ b/hw/char/riscv_htif.c @@ -0,0 +1,261 @@ +/* + * QEMU RISC-V Host Target Interface (HTIF) Emulation + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This provides HTIF device emulation for QEMU. At the moment this allows + * for identical copies of bbl/linux to run on both spike and QEMU. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/sysbus.h" +#include "hw/char/riscv_htif.h" +#include "hw/char/serial.h" +#include "chardev/char.h" +#include "chardev/char-fe.h" +#include "qemu/timer.h" +#include "qemu/error-report.h" + +#define RISCV_DEBUG_HTIF 0 +#define HTIF_DEBUG(fmt, ...) \ + do { \ + if (RISCV_DEBUG_HTIF) { \ + qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\ + } \ + } while (0) + +static uint64_t fromhost_addr, tohost_addr; +static int address_symbol_set; + +void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, + uint64_t st_size) +{ + if (strcmp("fromhost", st_name) == 0) { + address_symbol_set |= 1; + fromhost_addr = st_value; + if (st_size != 8) { + error_report("HTIF fromhost must be 8 bytes"); + exit(1); + } + } else if (strcmp("tohost", st_name) == 0) { + address_symbol_set |= 2; + tohost_addr = st_value; + if (st_size != 8) { + error_report("HTIF tohost must be 8 bytes"); + exit(1); + } + } +} + +/* + * Called by the char dev to see if HTIF is ready to accept input. + */ +static int htif_can_recv(void *opaque) +{ + return 1; +} + +/* + * Called by the char dev to supply input to HTIF console. + * We assume that we will receive one character at a time. + */ +static void htif_recv(void *opaque, const uint8_t *buf, int size) +{ + HTIFState *htifstate = opaque; + + if (size != 1) { + return; + } + + /* TODO - we need to check whether mfromhost is zero which indicates + the device is ready to receive. The current implementation + will drop characters */ + + uint64_t val_written = htifstate->pending_read; + uint64_t resp = 0x100 | *buf; + + htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); +} + +/* + * Called by the char dev to supply special events to the HTIF console. + * Not used for HTIF. + */ +static void htif_event(void *opaque, QEMUChrEvent event) +{ + +} + +static int htif_be_change(void *opaque) +{ + HTIFState *s = opaque; + + qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event, + htif_be_change, s, NULL, true); + + return 0; +} + +static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written) +{ + uint8_t device = val_written >> 56; + uint8_t cmd = val_written >> 48; + uint64_t payload = val_written & 0xFFFFFFFFFFFFULL; + int resp = 0; + + HTIF_DEBUG("mtohost write: device: %d cmd: %d what: %02" PRIx64 + " -payload: %016" PRIx64 "\n", device, cmd, payload & 0xFF, payload); + + /* + * Currently, there is a fixed mapping of devices: + * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy) + * 1: Console + */ + if (unlikely(device == 0x0)) { + /* frontend syscall handler, shutdown and exit code support */ + if (cmd == 0x0) { + if (payload & 0x1) { + /* exit code */ + int exit_code = payload >> 1; + exit(exit_code); + } else { + qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n"); + } + } else { + qemu_log("HTIF device %d: unknown command\n", device); + } + } else if (likely(device == 0x1)) { + /* HTIF Console */ + if (cmd == 0x0) { + /* this should be a queue, but not yet implemented as such */ + htifstate->pending_read = val_written; + htifstate->env->mtohost = 0; /* clear to indicate we read */ + return; + } else if (cmd == 0x1) { + qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1); + resp = 0x100 | (uint8_t)payload; + } else { + qemu_log("HTIF device %d: unknown command\n", device); + } + } else { + qemu_log("HTIF unknown device or command\n"); + HTIF_DEBUG("device: %d cmd: %d what: %02" PRIx64 + " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload); + } + /* + * - latest bbl does not set fromhost to 0 if there is a value in tohost + * - with this code enabled, qemu hangs waiting for fromhost to go to 0 + * - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10 + * - HTIF needs protocol documentation and a more complete state machine + + while (!htifstate->fromhost_inprogress && + htifstate->env->mfromhost != 0x0) { + } + */ + htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); + htifstate->env->mtohost = 0; /* clear to indicate we read */ +} + +#define TOHOST_OFFSET1 (htifstate->tohost_offset) +#define TOHOST_OFFSET2 (htifstate->tohost_offset + 4) +#define FROMHOST_OFFSET1 (htifstate->fromhost_offset) +#define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4) + +/* CPU wants to read an HTIF register */ +static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size) +{ + HTIFState *htifstate = opaque; + if (addr == TOHOST_OFFSET1) { + return htifstate->env->mtohost & 0xFFFFFFFF; + } else if (addr == TOHOST_OFFSET2) { + return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF; + } else if (addr == FROMHOST_OFFSET1) { + return htifstate->env->mfromhost & 0xFFFFFFFF; + } else if (addr == FROMHOST_OFFSET2) { + return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF; + } else { + qemu_log("Invalid htif read: address %016" PRIx64 "\n", + (uint64_t)addr); + return 0; + } +} + +/* CPU wrote to an HTIF register */ +static void htif_mm_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + HTIFState *htifstate = opaque; + if (addr == TOHOST_OFFSET1) { + if (htifstate->env->mtohost == 0x0) { + htifstate->allow_tohost = 1; + htifstate->env->mtohost = value & 0xFFFFFFFF; + } else { + htifstate->allow_tohost = 0; + } + } else if (addr == TOHOST_OFFSET2) { + if (htifstate->allow_tohost) { + htifstate->env->mtohost |= value << 32; + htif_handle_tohost_write(htifstate, htifstate->env->mtohost); + } + } else if (addr == FROMHOST_OFFSET1) { + htifstate->fromhost_inprogress = 1; + htifstate->env->mfromhost = value & 0xFFFFFFFF; + } else if (addr == FROMHOST_OFFSET2) { + htifstate->env->mfromhost |= value << 32; + htifstate->fromhost_inprogress = 0; + } else { + qemu_log("Invalid htif write: address %016" PRIx64 "\n", + (uint64_t)addr); + } +} + +static const MemoryRegionOps htif_mm_ops = { + .read = htif_mm_read, + .write = htif_mm_write, +}; + +HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem, + CPURISCVState *env, Chardev *chr) +{ + uint64_t base = MIN(tohost_addr, fromhost_addr); + uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base; + uint64_t tohost_offset = tohost_addr - base; + uint64_t fromhost_offset = fromhost_addr - base; + + HTIFState *s = g_malloc0(sizeof(HTIFState)); + s->address_space = address_space; + s->main_mem = main_mem; + s->main_mem_ram_ptr = memory_region_get_ram_ptr(main_mem); + s->env = env; + s->tohost_offset = tohost_offset; + s->fromhost_offset = fromhost_offset; + s->pending_read = 0; + s->allow_tohost = 0; + s->fromhost_inprogress = 0; + qemu_chr_fe_init(&s->chr, chr, &error_abort); + qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event, + htif_be_change, s, NULL, true); + if (address_symbol_set == 3) { + memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s, + TYPE_HTIF_UART, size); + memory_region_add_subregion_overlap(address_space, base, + &s->mmio, 1); + } + + return s; +} diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 23b7027e11..a0e256c344 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -1,6 +1,3 @@ -config HTIF - bool - config HART bool diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index df3f89d062..90df67acc7 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -8,7 +8,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) diff --git a/hw/riscv/riscv_htif.c b/hw/riscv/riscv_htif.c deleted file mode 100644 index ca87a5cf9f..0000000000 --- a/hw/riscv/riscv_htif.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * QEMU RISC-V Host Target Interface (HTIF) Emulation - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2017-2018 SiFive, Inc. - * - * This provides HTIF device emulation for QEMU. At the moment this allows - * for identical copies of bbl/linux to run on both spike and QEMU. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "qemu/log.h" -#include "hw/sysbus.h" -#include "hw/char/serial.h" -#include "chardev/char.h" -#include "chardev/char-fe.h" -#include "hw/riscv/riscv_htif.h" -#include "qemu/timer.h" -#include "qemu/error-report.h" - -#define RISCV_DEBUG_HTIF 0 -#define HTIF_DEBUG(fmt, ...) \ - do { \ - if (RISCV_DEBUG_HTIF) { \ - qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\ - } \ - } while (0) - -static uint64_t fromhost_addr, tohost_addr; -static int address_symbol_set; - -void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, - uint64_t st_size) -{ - if (strcmp("fromhost", st_name) == 0) { - address_symbol_set |= 1; - fromhost_addr = st_value; - if (st_size != 8) { - error_report("HTIF fromhost must be 8 bytes"); - exit(1); - } - } else if (strcmp("tohost", st_name) == 0) { - address_symbol_set |= 2; - tohost_addr = st_value; - if (st_size != 8) { - error_report("HTIF tohost must be 8 bytes"); - exit(1); - } - } -} - -/* - * Called by the char dev to see if HTIF is ready to accept input. - */ -static int htif_can_recv(void *opaque) -{ - return 1; -} - -/* - * Called by the char dev to supply input to HTIF console. - * We assume that we will receive one character at a time. - */ -static void htif_recv(void *opaque, const uint8_t *buf, int size) -{ - HTIFState *htifstate = opaque; - - if (size != 1) { - return; - } - - /* TODO - we need to check whether mfromhost is zero which indicates - the device is ready to receive. The current implementation - will drop characters */ - - uint64_t val_written = htifstate->pending_read; - uint64_t resp = 0x100 | *buf; - - htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); -} - -/* - * Called by the char dev to supply special events to the HTIF console. - * Not used for HTIF. - */ -static void htif_event(void *opaque, QEMUChrEvent event) -{ - -} - -static int htif_be_change(void *opaque) -{ - HTIFState *s = opaque; - - qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event, - htif_be_change, s, NULL, true); - - return 0; -} - -static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written) -{ - uint8_t device = val_written >> 56; - uint8_t cmd = val_written >> 48; - uint64_t payload = val_written & 0xFFFFFFFFFFFFULL; - int resp = 0; - - HTIF_DEBUG("mtohost write: device: %d cmd: %d what: %02" PRIx64 - " -payload: %016" PRIx64 "\n", device, cmd, payload & 0xFF, payload); - - /* - * Currently, there is a fixed mapping of devices: - * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy) - * 1: Console - */ - if (unlikely(device == 0x0)) { - /* frontend syscall handler, shutdown and exit code support */ - if (cmd == 0x0) { - if (payload & 0x1) { - /* exit code */ - int exit_code = payload >> 1; - exit(exit_code); - } else { - qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n"); - } - } else { - qemu_log("HTIF device %d: unknown command\n", device); - } - } else if (likely(device == 0x1)) { - /* HTIF Console */ - if (cmd == 0x0) { - /* this should be a queue, but not yet implemented as such */ - htifstate->pending_read = val_written; - htifstate->env->mtohost = 0; /* clear to indicate we read */ - return; - } else if (cmd == 0x1) { - qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1); - resp = 0x100 | (uint8_t)payload; - } else { - qemu_log("HTIF device %d: unknown command\n", device); - } - } else { - qemu_log("HTIF unknown device or command\n"); - HTIF_DEBUG("device: %d cmd: %d what: %02" PRIx64 - " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload); - } - /* - * - latest bbl does not set fromhost to 0 if there is a value in tohost - * - with this code enabled, qemu hangs waiting for fromhost to go to 0 - * - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10 - * - HTIF needs protocol documentation and a more complete state machine - - while (!htifstate->fromhost_inprogress && - htifstate->env->mfromhost != 0x0) { - } - */ - htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16); - htifstate->env->mtohost = 0; /* clear to indicate we read */ -} - -#define TOHOST_OFFSET1 (htifstate->tohost_offset) -#define TOHOST_OFFSET2 (htifstate->tohost_offset + 4) -#define FROMHOST_OFFSET1 (htifstate->fromhost_offset) -#define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4) - -/* CPU wants to read an HTIF register */ -static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size) -{ - HTIFState *htifstate = opaque; - if (addr == TOHOST_OFFSET1) { - return htifstate->env->mtohost & 0xFFFFFFFF; - } else if (addr == TOHOST_OFFSET2) { - return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF; - } else if (addr == FROMHOST_OFFSET1) { - return htifstate->env->mfromhost & 0xFFFFFFFF; - } else if (addr == FROMHOST_OFFSET2) { - return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF; - } else { - qemu_log("Invalid htif read: address %016" PRIx64 "\n", - (uint64_t)addr); - return 0; - } -} - -/* CPU wrote to an HTIF register */ -static void htif_mm_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) -{ - HTIFState *htifstate = opaque; - if (addr == TOHOST_OFFSET1) { - if (htifstate->env->mtohost == 0x0) { - htifstate->allow_tohost = 1; - htifstate->env->mtohost = value & 0xFFFFFFFF; - } else { - htifstate->allow_tohost = 0; - } - } else if (addr == TOHOST_OFFSET2) { - if (htifstate->allow_tohost) { - htifstate->env->mtohost |= value << 32; - htif_handle_tohost_write(htifstate, htifstate->env->mtohost); - } - } else if (addr == FROMHOST_OFFSET1) { - htifstate->fromhost_inprogress = 1; - htifstate->env->mfromhost = value & 0xFFFFFFFF; - } else if (addr == FROMHOST_OFFSET2) { - htifstate->env->mfromhost |= value << 32; - htifstate->fromhost_inprogress = 0; - } else { - qemu_log("Invalid htif write: address %016" PRIx64 "\n", - (uint64_t)addr); - } -} - -static const MemoryRegionOps htif_mm_ops = { - .read = htif_mm_read, - .write = htif_mm_write, -}; - -HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem, - CPURISCVState *env, Chardev *chr) -{ - uint64_t base = MIN(tohost_addr, fromhost_addr); - uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base; - uint64_t tohost_offset = tohost_addr - base; - uint64_t fromhost_offset = fromhost_addr - base; - - HTIFState *s = g_malloc0(sizeof(HTIFState)); - s->address_space = address_space; - s->main_mem = main_mem; - s->main_mem_ram_ptr = memory_region_get_ram_ptr(main_mem); - s->env = env; - s->tohost_offset = tohost_offset; - s->fromhost_offset = fromhost_offset; - s->pending_read = 0; - s->allow_tohost = 0; - s->fromhost_inprogress = 0; - qemu_chr_fe_init(&s->chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event, - htif_be_change, s, NULL, true); - if (address_symbol_set == 3) { - memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s, - TYPE_HTIF_UART, size); - memory_region_add_subregion_overlap(address_space, base, - &s->mmio, 1); - } - - return s; -} diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 59d9d87c56..3fd152a035 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -31,11 +31,11 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" -#include "hw/riscv/riscv_htif.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/char/riscv_htif.h" #include "hw/intc/sifive_clint.h" #include "chardev/char.h" #include "sysemu/arch_init.h" diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h new file mode 100644 index 0000000000..fb9452cf51 --- /dev/null +++ b/include/hw/char/riscv_htif.h @@ -0,0 +1,59 @@ +/* + * QEMU RISCV Host Target Interface (HTIF) Emulation + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_RISCV_HTIF_H +#define HW_RISCV_HTIF_H + +#include "chardev/char.h" +#include "chardev/char-fe.h" +#include "exec/memory.h" +#include "target/riscv/cpu.h" + +#define TYPE_HTIF_UART "riscv.htif.uart" + +typedef struct HTIFState { + int allow_tohost; + int fromhost_inprogress; + + hwaddr tohost_offset; + hwaddr fromhost_offset; + uint64_t tohost_size; + uint64_t fromhost_size; + MemoryRegion mmio; + MemoryRegion *address_space; + MemoryRegion *main_mem; + void *main_mem_ram_ptr; + + CPURISCVState *env; + CharBackend chr; + uint64_t pending_read; +} HTIFState; + +extern const VMStateDescription vmstate_htif; +extern const MemoryRegionOps htif_io_ops; + +/* HTIF symbol callback */ +void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, + uint64_t st_size); + +/* legacy pre qom */ +HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem, + CPURISCVState *env, Chardev *chr); + +#endif diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/riscv/riscv_htif.h deleted file mode 100644 index fb9452cf51..0000000000 --- a/include/hw/riscv/riscv_htif.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * QEMU RISCV Host Target Interface (HTIF) Emulation - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2017-2018 SiFive, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#ifndef HW_RISCV_HTIF_H -#define HW_RISCV_HTIF_H - -#include "chardev/char.h" -#include "chardev/char-fe.h" -#include "exec/memory.h" -#include "target/riscv/cpu.h" - -#define TYPE_HTIF_UART "riscv.htif.uart" - -typedef struct HTIFState { - int allow_tohost; - int fromhost_inprogress; - - hwaddr tohost_offset; - hwaddr fromhost_offset; - uint64_t tohost_size; - uint64_t fromhost_size; - MemoryRegion mmio; - MemoryRegion *address_space; - MemoryRegion *main_mem; - void *main_mem_ram_ptr; - - CPURISCVState *env; - CharBackend chr; - uint64_t pending_read; -} HTIFState; - -extern const VMStateDescription vmstate_htif; -extern const MemoryRegionOps htif_io_ops; - -/* HTIF symbol callback */ -void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, - uint64_t st_size); - -/* legacy pre qom */ -HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem, - CPURISCVState *env, Chardev *chr); - -#endif -- cgit v1.2.3-55-g7522 From b609b7e3199912e16ef3b0447823f21fed73597e Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 3 Sep 2020 18:40:19 +0800 Subject: hw/riscv: Move sifive_uart model to hw/char This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_uart model to hw/char directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/char/Kconfig | 3 + hw/char/meson.build | 1 + hw/char/sifive_uart.c | 194 +++++++++++++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 2 + hw/riscv/meson.build | 1 - hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/sifive_uart.c | 194 ----------------------------------------- include/hw/char/sifive_uart.h | 77 ++++++++++++++++ include/hw/riscv/sifive_uart.h | 77 ---------------- 10 files changed, 279 insertions(+), 274 deletions(-) create mode 100644 hw/char/sifive_uart.c delete mode 100644 hw/riscv/sifive_uart.c create mode 100644 include/hw/char/sifive_uart.h delete mode 100644 include/hw/riscv/sifive_uart.h (limited to 'hw/char') diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 91da92f617..939bc44758 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -58,3 +58,6 @@ config AVR_USART config MCHP_PFSOC_MMUART bool + +config SIFIVE_UART + bool diff --git a/hw/char/meson.build b/hw/char/meson.build index 3db623eeec..196ac91fa2 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c')) softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c')) softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c')) softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c')) diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c new file mode 100644 index 0000000000..3a00ba7f00 --- /dev/null +++ b/hw/char/sifive_uart.c @@ -0,0 +1,194 @@ +/* + * QEMU model of the UART on the SiFive E300 and U500 series SOCs. + * + * Copyright (c) 2016 Stefan O'Rear + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/sysbus.h" +#include "chardev/char.h" +#include "chardev/char-fe.h" +#include "hw/hw.h" +#include "hw/irq.h" +#include "hw/char/sifive_uart.h" + +/* + * Not yet implemented: + * + * Transmit FIFO using "qemu/fifo8.h" + */ + +/* Returns the state of the IP (interrupt pending) register */ +static uint64_t uart_ip(SiFiveUARTState *s) +{ + uint64_t ret = 0; + + uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl); + uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl); + + if (txcnt != 0) { + ret |= SIFIVE_UART_IP_TXWM; + } + if (s->rx_fifo_len > rxcnt) { + ret |= SIFIVE_UART_IP_RXWM; + } + + return ret; +} + +static void update_irq(SiFiveUARTState *s) +{ + int cond = 0; + if ((s->ie & SIFIVE_UART_IE_TXWM) || + ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) { + cond = 1; + } + if (cond) { + qemu_irq_raise(s->irq); + } else { + qemu_irq_lower(s->irq); + } +} + +static uint64_t +uart_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveUARTState *s = opaque; + unsigned char r; + switch (addr) { + case SIFIVE_UART_RXFIFO: + if (s->rx_fifo_len) { + r = s->rx_fifo[0]; + memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); + s->rx_fifo_len--; + qemu_chr_fe_accept_input(&s->chr); + update_irq(s); + return r; + } + return 0x80000000; + + case SIFIVE_UART_TXFIFO: + return 0; /* Should check tx fifo */ + case SIFIVE_UART_IE: + return s->ie; + case SIFIVE_UART_IP: + return uart_ip(s); + case SIFIVE_UART_TXCTRL: + return s->txctrl; + case SIFIVE_UART_RXCTRL: + return s->rxctrl; + case SIFIVE_UART_DIV: + return s->div; + } + + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", + __func__, (int)addr); + return 0; +} + +static void +uart_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveUARTState *s = opaque; + uint32_t value = val64; + unsigned char ch = value; + + switch (addr) { + case SIFIVE_UART_TXFIFO: + qemu_chr_fe_write(&s->chr, &ch, 1); + update_irq(s); + return; + case SIFIVE_UART_IE: + s->ie = val64; + update_irq(s); + return; + case SIFIVE_UART_TXCTRL: + s->txctrl = val64; + return; + case SIFIVE_UART_RXCTRL: + s->rxctrl = val64; + return; + case SIFIVE_UART_DIV: + s->div = val64; + return; + } + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)value); +} + +static const MemoryRegionOps uart_ops = { + .read = uart_read, + .write = uart_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static void uart_rx(void *opaque, const uint8_t *buf, int size) +{ + SiFiveUARTState *s = opaque; + + /* Got a byte. */ + if (s->rx_fifo_len >= sizeof(s->rx_fifo)) { + printf("WARNING: UART dropped char.\n"); + return; + } + s->rx_fifo[s->rx_fifo_len++] = *buf; + + update_irq(s); +} + +static int uart_can_rx(void *opaque) +{ + SiFiveUARTState *s = opaque; + + return s->rx_fifo_len < sizeof(s->rx_fifo); +} + +static void uart_event(void *opaque, QEMUChrEvent event) +{ +} + +static int uart_be_change(void *opaque) +{ + SiFiveUARTState *s = opaque; + + qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, + uart_be_change, s, NULL, true); + + return 0; +} + +/* + * Create UART device. + */ +SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, + Chardev *chr, qemu_irq irq) +{ + SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState)); + s->irq = irq; + qemu_chr_fe_init(&s->chr, chr, &error_abort); + qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, + uart_be_change, s, NULL, true); + memory_region_init_io(&s->mmio, NULL, &uart_ops, s, + TYPE_SIFIVE_UART, SIFIVE_UART_MAX); + memory_region_add_subregion(address_space, base, &s->mmio); + return s; +} diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index a0e256c344..a0461578a6 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -15,6 +15,7 @@ config SIFIVE_E select SIFIVE_CLINT select SIFIVE_GPIO select SIFIVE_PLIC + select SIFIVE_UART select SIFIVE_E_PRCI select UNIMP @@ -27,6 +28,7 @@ config SIFIVE_U select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_PLIC + select SIFIVE_UART select SIFIVE_U_OTP select SIFIVE_U_PRCI select UNIMP diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 90df67acc7..967572d4f6 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 0ddcf1508d..40bbf530d4 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -39,9 +39,9 @@ #include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" +#include "hw/char/sifive_uart.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_e_prci.h" diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index faca2e829e..4f12a93188 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -46,9 +46,9 @@ #include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" +#include "hw/char/sifive_uart.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" #include "chardev/char.h" diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c deleted file mode 100644 index 9350482662..0000000000 --- a/hw/riscv/sifive_uart.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * QEMU model of the UART on the SiFive E300 and U500 series SOCs. - * - * Copyright (c) 2016 Stefan O'Rear - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "qemu/log.h" -#include "hw/sysbus.h" -#include "chardev/char.h" -#include "chardev/char-fe.h" -#include "hw/hw.h" -#include "hw/irq.h" -#include "hw/riscv/sifive_uart.h" - -/* - * Not yet implemented: - * - * Transmit FIFO using "qemu/fifo8.h" - */ - -/* Returns the state of the IP (interrupt pending) register */ -static uint64_t uart_ip(SiFiveUARTState *s) -{ - uint64_t ret = 0; - - uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl); - uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl); - - if (txcnt != 0) { - ret |= SIFIVE_UART_IP_TXWM; - } - if (s->rx_fifo_len > rxcnt) { - ret |= SIFIVE_UART_IP_RXWM; - } - - return ret; -} - -static void update_irq(SiFiveUARTState *s) -{ - int cond = 0; - if ((s->ie & SIFIVE_UART_IE_TXWM) || - ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) { - cond = 1; - } - if (cond) { - qemu_irq_raise(s->irq); - } else { - qemu_irq_lower(s->irq); - } -} - -static uint64_t -uart_read(void *opaque, hwaddr addr, unsigned int size) -{ - SiFiveUARTState *s = opaque; - unsigned char r; - switch (addr) { - case SIFIVE_UART_RXFIFO: - if (s->rx_fifo_len) { - r = s->rx_fifo[0]; - memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); - s->rx_fifo_len--; - qemu_chr_fe_accept_input(&s->chr); - update_irq(s); - return r; - } - return 0x80000000; - - case SIFIVE_UART_TXFIFO: - return 0; /* Should check tx fifo */ - case SIFIVE_UART_IE: - return s->ie; - case SIFIVE_UART_IP: - return uart_ip(s); - case SIFIVE_UART_TXCTRL: - return s->txctrl; - case SIFIVE_UART_RXCTRL: - return s->rxctrl; - case SIFIVE_UART_DIV: - return s->div; - } - - qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", - __func__, (int)addr); - return 0; -} - -static void -uart_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) -{ - SiFiveUARTState *s = opaque; - uint32_t value = val64; - unsigned char ch = value; - - switch (addr) { - case SIFIVE_UART_TXFIFO: - qemu_chr_fe_write(&s->chr, &ch, 1); - update_irq(s); - return; - case SIFIVE_UART_IE: - s->ie = val64; - update_irq(s); - return; - case SIFIVE_UART_TXCTRL: - s->txctrl = val64; - return; - case SIFIVE_UART_RXCTRL: - s->rxctrl = val64; - return; - case SIFIVE_UART_DIV: - s->div = val64; - return; - } - qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", - __func__, (int)addr, (int)value); -} - -static const MemoryRegionOps uart_ops = { - .read = uart_read, - .write = uart_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } -}; - -static void uart_rx(void *opaque, const uint8_t *buf, int size) -{ - SiFiveUARTState *s = opaque; - - /* Got a byte. */ - if (s->rx_fifo_len >= sizeof(s->rx_fifo)) { - printf("WARNING: UART dropped char.\n"); - return; - } - s->rx_fifo[s->rx_fifo_len++] = *buf; - - update_irq(s); -} - -static int uart_can_rx(void *opaque) -{ - SiFiveUARTState *s = opaque; - - return s->rx_fifo_len < sizeof(s->rx_fifo); -} - -static void uart_event(void *opaque, QEMUChrEvent event) -{ -} - -static int uart_be_change(void *opaque) -{ - SiFiveUARTState *s = opaque; - - qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, - uart_be_change, s, NULL, true); - - return 0; -} - -/* - * Create UART device. - */ -SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, - Chardev *chr, qemu_irq irq) -{ - SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState)); - s->irq = irq; - qemu_chr_fe_init(&s->chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, - uart_be_change, s, NULL, true); - memory_region_init_io(&s->mmio, NULL, &uart_ops, s, - TYPE_SIFIVE_UART, SIFIVE_UART_MAX); - memory_region_add_subregion(address_space, base, &s->mmio); - return s; -} diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h new file mode 100644 index 0000000000..65668825a3 --- /dev/null +++ b/include/hw/char/sifive_uart.h @@ -0,0 +1,77 @@ +/* + * SiFive UART interface + * + * Copyright (c) 2016 Stefan O'Rear + * Copyright (c) 2017 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_UART_H +#define HW_SIFIVE_UART_H + +#include "chardev/char-fe.h" +#include "hw/sysbus.h" + +enum { + SIFIVE_UART_TXFIFO = 0, + SIFIVE_UART_RXFIFO = 4, + SIFIVE_UART_TXCTRL = 8, + SIFIVE_UART_TXMARK = 10, + SIFIVE_UART_RXCTRL = 12, + SIFIVE_UART_RXMARK = 14, + SIFIVE_UART_IE = 16, + SIFIVE_UART_IP = 20, + SIFIVE_UART_DIV = 24, + SIFIVE_UART_MAX = 32 +}; + +enum { + SIFIVE_UART_IE_TXWM = 1, /* Transmit watermark interrupt enable */ + SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */ +}; + +enum { + SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */ + SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ +}; + +#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) +#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) + +#define TYPE_SIFIVE_UART "riscv.sifive.uart" + +#define SIFIVE_UART(obj) \ + OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART) + +typedef struct SiFiveUARTState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq irq; + MemoryRegion mmio; + CharBackend chr; + uint8_t rx_fifo[8]; + unsigned int rx_fifo_len; + uint32_t ie; + uint32_t ip; + uint32_t txctrl; + uint32_t rxctrl; + uint32_t div; +} SiFiveUARTState; + +SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, + Chardev *chr, qemu_irq irq); + +#endif diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/riscv/sifive_uart.h deleted file mode 100644 index 65668825a3..0000000000 --- a/include/hw/riscv/sifive_uart.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * SiFive UART interface - * - * Copyright (c) 2016 Stefan O'Rear - * Copyright (c) 2017 SiFive, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#ifndef HW_SIFIVE_UART_H -#define HW_SIFIVE_UART_H - -#include "chardev/char-fe.h" -#include "hw/sysbus.h" - -enum { - SIFIVE_UART_TXFIFO = 0, - SIFIVE_UART_RXFIFO = 4, - SIFIVE_UART_TXCTRL = 8, - SIFIVE_UART_TXMARK = 10, - SIFIVE_UART_RXCTRL = 12, - SIFIVE_UART_RXMARK = 14, - SIFIVE_UART_IE = 16, - SIFIVE_UART_IP = 20, - SIFIVE_UART_DIV = 24, - SIFIVE_UART_MAX = 32 -}; - -enum { - SIFIVE_UART_IE_TXWM = 1, /* Transmit watermark interrupt enable */ - SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */ -}; - -enum { - SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */ - SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ -}; - -#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) -#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) - -#define TYPE_SIFIVE_UART "riscv.sifive.uart" - -#define SIFIVE_UART(obj) \ - OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART) - -typedef struct SiFiveUARTState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - qemu_irq irq; - MemoryRegion mmio; - CharBackend chr; - uint8_t rx_fifo[8]; - unsigned int rx_fifo_len; - uint32_t ie; - uint32_t ip; - uint32_t txctrl; - uint32_t rxctrl; - uint32_t div; -} SiFiveUARTState; - -SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, - Chardev *chr, qemu_irq irq); - -#endif -- cgit v1.2.3-55-g7522