From ac70f9767cba3a5966f7eefc102fcda8b3c7d09e Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Mon, 7 Dec 2020 22:32:49 +0100 Subject: target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT() As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type' name argument, rename them cpu_type_supports_FEAT(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207215257.4004222-2-f4bug@amsat.org> --- hw/mips/boston.c | 4 ++-- hw/mips/malta.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'hw/mips') diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 3d40867dc4..16467ea475 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -459,12 +459,12 @@ static void boston_mach_init(MachineState *machine) s = BOSTON(dev); s->mach = machine; - if (!cpu_supports_cps_smp(machine->cpu_type)) { + if (!cpu_type_supports_cps_smp(machine->cpu_type)) { error_report("Boston requires CPUs which support CPS"); exit(1); } - is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); + is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64); object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 5c11eecec1..4651a1055c 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1205,7 +1205,7 @@ static void create_cps(MachineState *ms, MaltaState *s, static void mips_create_cpu(MachineState *ms, MaltaState *s, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { - if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { + if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { create_cps(ms, s, cbus_irq, i8259_irq); } else { create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); @@ -1309,7 +1309,7 @@ void mips_malta_init(MachineState *machine) loaderparams.initrd_filename = initrd_filename; kernel_entry = load_kernel(); - if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { + if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { write_bootloader(memory_region_get_ram_ptr(bios), bootloader_run_addr, kernel_entry); } else { -- cgit v1.2.3-55-g7522 From 2fd9c5ad4449c862932b21e8f6b4573cc50b9ae8 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Sun, 6 Dec 2020 20:29:00 +0100 Subject: hw/mips: Move address translation helpers to target/mips/ Address translation is an architectural thing (not hardware related). Move the helpers from hw/ to target/. As physical address and KVM are specific to system mode emulation, restrict this file to softmmu, so it doesn't get compiled for user-mode emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-2-f4bug@amsat.org> --- hw/mips/addr.c | 51 ----------------------------------------------- hw/mips/boston.c | 1 - hw/mips/meson.build | 2 +- include/hw/mips/cpudevs.h | 7 ------- target/mips/addr.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++ target/mips/cpu.h | 8 ++++++++ target/mips/meson.build | 1 + target/mips/translate.c | 2 -- 8 files changed, 61 insertions(+), 62 deletions(-) delete mode 100644 hw/mips/addr.c create mode 100644 target/mips/addr.c (limited to 'hw/mips') diff --git a/hw/mips/addr.c b/hw/mips/addr.c deleted file mode 100644 index 2f138fe1ea..0000000000 --- a/hw/mips/addr.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * QEMU MIPS address translation support - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "hw/mips/cpudevs.h" - -static int mips_um_ksegs; - -uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr) -{ - return addr & 0x1fffffffll; -} - -uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr) -{ - return addr | ~0x7fffffffll; -} - -uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr) -{ - return addr | 0x40000000ll; -} - -bool mips_um_ksegs_enabled(void) -{ - return mips_um_ksegs; -} - -void mips_um_ksegs_enable(void) -{ - mips_um_ksegs = 1; -} diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 16467ea475..c3b94c68e1 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -28,7 +28,6 @@ #include "hw/loader.h" #include "hw/loader-fit.h" #include "hw/mips/cps.h" -#include "hw/mips/cpudevs.h" #include "hw/pci-host/xilinx-pcie.h" #include "hw/qdev-clock.h" #include "hw/qdev-properties.h" diff --git a/hw/mips/meson.build b/hw/mips/meson.build index bcdf96be69..77b4d8f365 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,5 +1,5 @@ mips_ss = ss.source_set() -mips_ss.add(files('addr.c', 'mips_int.c')) +mips_ss.add(files('mips_int.c')) mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c')) diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h index 291f59281a..f7c9728fa9 100644 --- a/include/hw/mips/cpudevs.h +++ b/include/hw/mips/cpudevs.h @@ -5,13 +5,6 @@ /* Definitions for MIPS CPU internal devices. */ -/* addr.c */ -uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); -uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); -uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); -bool mips_um_ksegs_enabled(void); -void mips_um_ksegs_enable(void); - /* mips_int.c */ void cpu_mips_irq_init_cpu(MIPSCPU *cpu); diff --git a/target/mips/addr.c b/target/mips/addr.c new file mode 100644 index 0000000000..27a6036c45 --- /dev/null +++ b/target/mips/addr.c @@ -0,0 +1,51 @@ +/* + * QEMU MIPS address translation support + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "cpu.h" + +static int mips_um_ksegs; + +uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr) +{ + return addr & 0x1fffffffll; +} + +uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr) +{ + return addr | ~0x7fffffffll; +} + +uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr) +{ + return addr | 0x40000000ll; +} + +bool mips_um_ksegs_enabled(void) +{ + return mips_um_ksegs; +} + +void mips_um_ksegs_enable(void) +{ + mips_um_ksegs = 1; +} diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e8bca75f23..5d3b2a01c0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1291,6 +1291,14 @@ bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); +/* addr.c */ +uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); +uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); + +uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); +bool mips_um_ksegs_enabled(void); +void mips_um_ksegs_enable(void); + /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); diff --git a/target/mips/meson.build b/target/mips/meson.build index 681a5524c0..4179395a8e 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -14,6 +14,7 @@ mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) mips_softmmu_ss = ss.source_set() mips_softmmu_ss.add(files( + 'addr.c', 'cp0_helper.c', 'cp0_timer.c', 'machine.c', diff --git a/target/mips/translate.c b/target/mips/translate.c index b8ed16bb77..4a1ae73f9d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28,8 +28,6 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" -#include "hw/mips/cpudevs.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "hw/semihosting/semihost.h" -- cgit v1.2.3-55-g7522 From 17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 2 Dec 2020 18:49:00 +0100 Subject: target/mips: Introduce ase_mt_available() helper Instead of accessing CP0_Config3 directly and checking the 'Multi-Threading Present' bit, introduce an helper to simplify code review. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201204222622.2743175-3-f4bug@amsat.org> --- hw/mips/cps.c | 3 +-- target/mips/cp0_helper.c | 2 +- target/mips/cpu.c | 2 +- target/mips/cpu.h | 7 +++++++ target/mips/helper.c | 2 +- target/mips/translate.c | 2 +- 6 files changed, 12 insertions(+), 6 deletions(-) (limited to 'hw/mips') diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 962b1b0b87..7a0d289efa 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -58,8 +58,7 @@ static void main_cpu_reset(void *opaque) static bool cpu_mips_itu_supported(CPUMIPSState *env) { - bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || - (env->CP0_Config3 & (1 << CP0C3_MT)); + bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); return is_mt && !kvm_enabled(); } diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index cb899fe3d7..36a92857bf 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -1164,7 +1164,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) old = env->CP0_EntryHi; val = (arg1 & mask) | (old & ~mask); env->CP0_EntryHi = val; - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_entryhi(env, env->current_tc); } /* If the ASID changes, flush qemu's TLB. */ diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 687e2680dd..9d7edc1ca2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -74,7 +74,7 @@ static bool mips_cpu_has_work(CPUState *cs) } /* MIPS-MT has the ability to halt the CPU. */ - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { /* * The QEMU model will issue an _WAKE request whenever the CPUs * should be woken up. diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5d3b2a01c0..3ac21d0e9c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1289,6 +1289,13 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); + +/* Check presence of multi-threading ASE implementation */ +static inline bool ase_mt_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MT); +} + void cpu_set_exception_base(int vp_index, target_ulong address); /* addr.c */ diff --git a/target/mips/helper.c b/target/mips/helper.c index 59de58fcbc..0c65786579 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -419,7 +419,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) tlb_flush(env_cpu(env)); } #endif - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_status(env, env, env->current_tc); } else { compute_hflags(env); diff --git a/target/mips/translate.c b/target/mips/translate.c index f218997f04..ccc82abce0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31917,7 +31917,7 @@ void cpu_state_reset(CPUMIPSState *env) cpu_mips_store_count(env, 1); - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { int i; /* Only TC0 on VPE 0 starts as active. */ -- cgit v1.2.3-55-g7522 From 8de0f2804676decfa82ce51ef18293523e67af32 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 2 Dec 2020 18:53:09 +0100 Subject: hw/mips/malta: Do not initialize MT registers if MT ASE absent Do not initialize MT-related config register if the MT ASE is not present. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201204222622.2743175-5-f4bug@amsat.org> --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'hw/mips') diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4651a1055c..f06cb90a44 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1135,8 +1135,10 @@ static void malta_mips_config(MIPSCPU *cpu) CPUMIPSState *env = &cpu->env; CPUState *cs = CPU(cpu); - env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | + if (ase_mt_available(env)) { + env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC); + } } static void main_cpu_reset(void *opaque) -- cgit v1.2.3-55-g7522 From 07741e67542d061b45628a5de60637b006ca2de5 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Fri, 4 Dec 2020 23:16:45 +0100 Subject: hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit() PTC field has 8 bits, PVPE has 4. We plan to use the "hw/registerfields.h" API with MIPS CPU definitions (target/mips/cpu.h). Meanwhile we use magic 8 and 4. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201204222622.2743175-6-f4bug@amsat.org> --- hw/mips/malta.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'hw/mips') diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f06cb90a44..366f4fdfcd 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/bitops.h" #include "qemu-common.h" #include "qemu/datadir.h" #include "cpu.h" @@ -1136,8 +1137,11 @@ static void malta_mips_config(MIPSCPU *cpu) CPUState *cs = CPU(cpu); if (ase_mt_available(env)) { - env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | - ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC); + env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, + CP0MVPC0_PTC, 8, + smp_cpus * cs->nr_threads - 1); + env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, + CP0MVPC0_PVPE, 4, smp_cpus - 1); } } -- cgit v1.2.3-55-g7522