From f663faac3e2e9d9134415f75d429ae30432e6038 Mon Sep 17 00:00:00 2001
From: Nathan Rossi
Date: Tue, 8 Apr 2014 18:52:39 -0700
Subject: net: xilinx_axienet.c: Add phy soft reset bit clearing

Clear the BMCR Reset when writing to registers.

Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
[ PC:
 * Trivial style fixes to commit message
]
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
---
 hw/net/xilinx_axienet.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'hw/net')

diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 839d97ca86..0f485a0283 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
             phy->regs[regnum] = data;
             break;
     }
+
+    /* Unconditionally clear regs[BMCR][BMCR_RESET] */
+    phy->regs[0] &= ~0x8000;
 }
 
 static void
-- 
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