From a8170e5e97ad17ca169c64ba87ae2f53850dab4c Mon Sep 17 00:00:00 2001 From: Avi Kivity Date: Tue, 23 Oct 2012 12:30:10 +0200 Subject: Rename target_phys_addr_t to hwaddr target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity Signed-off-by: Anthony Liguori --- hw/ppc405_uc.c | 64 +++++++++++++++++++++++++++++----------------------------- 1 file changed, 32 insertions(+), 32 deletions(-) (limited to 'hw/ppc405_uc.c') diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index e81409dc0f..0f458ef772 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -271,7 +271,7 @@ struct ppc4xx_opba_t { uint8_t pr; }; -static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) +static uint32_t opba_readb (void *opaque, hwaddr addr) { ppc4xx_opba_t *opba; uint32_t ret; @@ -296,7 +296,7 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) } static void opba_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { ppc4xx_opba_t *opba; @@ -317,7 +317,7 @@ static void opba_writeb (void *opaque, } } -static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) +static uint32_t opba_readw (void *opaque, hwaddr addr) { uint32_t ret; @@ -331,7 +331,7 @@ static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) } static void opba_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { #ifdef DEBUG_OPBA printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -341,7 +341,7 @@ static void opba_writew (void *opaque, opba_writeb(opaque, addr + 1, value); } -static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) +static uint32_t opba_readl (void *opaque, hwaddr addr) { uint32_t ret; @@ -355,7 +355,7 @@ static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) } static void opba_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { #ifdef DEBUG_OPBA printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -382,7 +382,7 @@ static void ppc4xx_opba_reset (void *opaque) opba->pr = 0x11; } -static void ppc4xx_opba_init(target_phys_addr_t base) +static void ppc4xx_opba_init(hwaddr base) { ppc4xx_opba_t *opba; @@ -738,7 +738,7 @@ struct ppc405_gpio_t { uint32_t isr1l; }; -static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) +static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr) { #ifdef DEBUG_GPIO printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -748,7 +748,7 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) } static void ppc405_gpio_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { #ifdef DEBUG_GPIO printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -756,7 +756,7 @@ static void ppc405_gpio_writeb (void *opaque, #endif } -static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) +static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr) { #ifdef DEBUG_GPIO printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -766,7 +766,7 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) } static void ppc405_gpio_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { #ifdef DEBUG_GPIO printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -774,7 +774,7 @@ static void ppc405_gpio_writew (void *opaque, #endif } -static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) +static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr) { #ifdef DEBUG_GPIO printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -784,7 +784,7 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) } static void ppc405_gpio_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { #ifdef DEBUG_GPIO printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -804,7 +804,7 @@ static void ppc405_gpio_reset (void *opaque) { } -static void ppc405_gpio_init(target_phys_addr_t base) +static void ppc405_gpio_init(hwaddr base) { ppc405_gpio_t *gpio; @@ -1010,7 +1010,7 @@ struct ppc4xx_i2c_t { uint8_t directcntl; }; -static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr) { ppc4xx_i2c_t *i2c; uint32_t ret; @@ -1078,7 +1078,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) } static void ppc4xx_i2c_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { ppc4xx_i2c_t *i2c; @@ -1137,7 +1137,7 @@ static void ppc4xx_i2c_writeb (void *opaque, } } -static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr) { uint32_t ret; @@ -1151,7 +1151,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) } static void ppc4xx_i2c_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -1161,7 +1161,7 @@ static void ppc4xx_i2c_writew (void *opaque, ppc4xx_i2c_writeb(opaque, addr + 1, value); } -static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr) { uint32_t ret; @@ -1177,7 +1177,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) } static void ppc4xx_i2c_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -1213,7 +1213,7 @@ static void ppc4xx_i2c_reset (void *opaque) i2c->directcntl = 0x0F; } -static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) +static void ppc405_i2c_init(hwaddr base, qemu_irq irq) { ppc4xx_i2c_t *i2c; @@ -1245,7 +1245,7 @@ struct ppc4xx_gpt_t { uint32_t mask[5]; }; -static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr) { #ifdef DEBUG_GPT printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -1255,7 +1255,7 @@ static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) } static void ppc4xx_gpt_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -1264,7 +1264,7 @@ static void ppc4xx_gpt_writeb (void *opaque, /* XXX: generate a bus fault */ } -static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr) { #ifdef DEBUG_GPT printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); @@ -1274,7 +1274,7 @@ static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) } static void ppc4xx_gpt_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { #ifdef DEBUG_I2C printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, @@ -1335,7 +1335,7 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) /* XXX: TODO */ } -static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) +static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) { ppc4xx_gpt_t *gpt; uint32_t ret; @@ -1391,7 +1391,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) } static void ppc4xx_gpt_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) + hwaddr addr, uint32_t value) { ppc4xx_gpt_t *gpt; int idx; @@ -1488,7 +1488,7 @@ static void ppc4xx_gpt_reset (void *opaque) } } -static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5]) +static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) { ppc4xx_gpt_t *gpt; int i; @@ -2104,8 +2104,8 @@ static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[4], - target_phys_addr_t ram_bases[4], - target_phys_addr_t ram_sizes[4], + hwaddr ram_bases[4], + hwaddr ram_sizes[4], uint32_t sysclk, qemu_irq **picp, int do_init) { @@ -2453,8 +2453,8 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], - target_phys_addr_t ram_bases[2], - target_phys_addr_t ram_sizes[2], + hwaddr ram_bases[2], + hwaddr ram_sizes[2], uint32_t sysclk, qemu_irq **picp, int do_init) { -- cgit v1.2.3-55-g7522