From 93afeade09680c657e109bf192dbf70233e4ebbe Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 03:41:01 +0200 Subject: cpu: Move mem_io_{pc,vaddr} fields from CPU_COMMON to CPUState Reset them. Signed-off-by: Andreas Färber --- include/exec/cpu-defs.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 66a3d46938..bdcfefb3fb 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -146,13 +146,6 @@ typedef struct CPUWatchpoint { #define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ /* soft mmu support */ \ - /* in order to avoid passing too many arguments to the MMIO \ - helpers, we store some rarely used information in the CPU \ - context) */ \ - uintptr_t mem_io_pc; /* host pc at which the memory was \ - accessed */ \ - target_ulong mem_io_vaddr; /* target virtual addr at which the \ - memory was accessed */ \ CPU_COMMON_TLB \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ -- cgit v1.2.3-55-g7522 From 99df7dce8ae81e4a42dac98094ccca3a32dcf8f8 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 05:15:23 +0200 Subject: cpu: Move can_do_io field from CPU_COMMON to CPUState Rename can_do_io() to cpu_can_do_io() and change argument to CPUState. Signed-off-by: Andreas Färber --- cpus.c | 2 +- include/exec/cpu-defs.h | 1 - include/exec/exec-all.h | 21 +++++++++++++-------- include/exec/gen-icount.h | 4 ++-- include/exec/softmmu_template.h | 4 ++-- include/qom/cpu.h | 2 ++ qom/cpu.c | 1 + translate-all.c | 5 +++-- 8 files changed, 24 insertions(+), 16 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/cpus.c b/cpus.c index eda6d02bcc..05016dc9c7 100644 --- a/cpus.c +++ b/cpus.c @@ -140,7 +140,7 @@ static int64_t cpu_get_icount_locked(void) icount = qemu_icount; if (cpu) { CPUArchState *env = cpu->env_ptr; - if (!can_do_io(env)) { + if (!cpu_can_do_io(cpu)) { fprintf(stderr, "Bad clock read\n"); } icount -= (env->icount_decr.u16.low + env->icount_extra); diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bdcfefb3fb..068b6c168f 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -157,7 +157,6 @@ typedef struct CPUWatchpoint { uint32_t u32; \ icount_decr_u16 u16; \ } icount_decr; \ - uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ \ /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a387922df4..2179329916 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -380,20 +380,25 @@ extern int singlestep; /* cpu-exec.c */ extern volatile sig_atomic_t exit_request; -/* Deterministic execution requires that IO only be performed on the last - instruction of a TB so that interrupts take effect immediately. */ -static inline int can_do_io(CPUArchState *env) +/** + * cpu_can_do_io: + * @cpu: The CPU for which to check IO. + * + * Deterministic execution requires that IO only be performed on the last + * instruction of a TB so that interrupts take effect immediately. + * + * Returns: %true if memory-mapped IO is safe, %false otherwise. + */ +static inline bool cpu_can_do_io(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); - if (!use_icount) { - return 1; + return true; } /* If not executing code then assume we are ok. */ if (cpu->current_tb == NULL) { - return 1; + return true; } - return env->can_do_io != 0; + return cpu->can_do_io != 0; } #endif diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 39a6b61e4f..f0dace3034 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -51,14 +51,14 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns) static inline void gen_io_start(void) { TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } static inline void gen_io_end(void) { TCGv_i32 tmp = tcg_const_i32(0); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h index c7cd93774d..ac825d251c 100644 --- a/include/exec/softmmu_template.h +++ b/include/exec/softmmu_template.h @@ -127,7 +127,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, physaddr = (physaddr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc = retaddr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) { + if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { cpu_io_recompile(env, retaddr); } @@ -333,7 +333,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr); physaddr = (physaddr & TARGET_PAGE_MASK) + addr; - if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) { + if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) { cpu_io_recompile(env, retaddr); } diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 9d52cf3a34..f80036e99b 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -157,6 +157,7 @@ struct kvm_run; * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this * CPU and return to its top level loop. * @singlestep_enabled: Flags for single-stepping. + * @can_do_io: Nonzero if memory-mapped IO is safe. * @env_ptr: Pointer to subclass-specific CPUArchState field. * @current_tb: Currently executing TB. * @gdb_regs: Additional GDB registers. @@ -220,6 +221,7 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; /* used by alpha TCG */ uint32_t halted; /* used by alpha, cris, ppc TCG */ + uint32_t can_do_io; }; QTAILQ_HEAD(CPUTailQ, CPUState); diff --git a/qom/cpu.c b/qom/cpu.c index 4d60c03182..e7d59997ee 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -241,6 +241,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->halted = 0; cpu->mem_io_pc = 0; cpu->mem_io_vaddr = 0; + cpu->can_do_io = 0; } static bool cpu_common_has_work(CPUState *cs) diff --git a/translate-all.c b/translate-all.c index dc35caab8e..a1af5ef393 100644 --- a/translate-all.c +++ b/translate-all.c @@ -200,6 +200,7 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, uintptr_t searched_pc) { + CPUState *cpu = ENV_GET_CPU(env); TCGContext *s = &tcg_ctx; int j; uintptr_t tc_ptr; @@ -218,7 +219,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, /* Reset the cycle counter to the start of the block. */ env->icount_decr.u16.low += tb->icount; /* Clear the IO flag. */ - env->can_do_io = 0; + cpu->can_do_io = 0; } /* find opc index corresponding to search_pc */ @@ -1409,7 +1410,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) if (use_icount) { env->icount_decr.u16.high = 0xffff; - if (!can_do_io(env) + if (!cpu_can_do_io(cpu) && (mask & ~old_mask) != 0) { cpu_abort(env, "Raised interrupt while not in I/O function"); } -- cgit v1.2.3-55-g7522 From efee734004c42ba185098086e5185d8a85ed02af Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 05:39:29 +0200 Subject: cpu: Move icount_extra field from CPU_COMMON to CPUState Reset it. Signed-off-by: Andreas Färber --- cpu-exec.c | 10 +++++----- cpus.c | 14 +++++++------- include/exec/cpu-defs.h | 1 - include/qom/cpu.h | 2 ++ qom/cpu.c | 1 + 5 files changed, 15 insertions(+), 13 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/cpu-exec.c b/cpu-exec.c index 6559d5e922..4a03d83cba 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -650,15 +650,15 @@ int cpu_exec(CPUArchState *env) int insns_left; tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); insns_left = env->icount_decr.u32; - if (env->icount_extra && insns_left >= 0) { + if (cpu->icount_extra && insns_left >= 0) { /* Refill decrementer and continue execution. */ - env->icount_extra += insns_left; - if (env->icount_extra > 0xffff) { + cpu->icount_extra += insns_left; + if (cpu->icount_extra > 0xffff) { insns_left = 0xffff; } else { - insns_left = env->icount_extra; + insns_left = cpu->icount_extra; } - env->icount_extra -= insns_left; + cpu->icount_extra -= insns_left; env->icount_decr.u16.low = insns_left; } else { if (insns_left > 0) { diff --git a/cpus.c b/cpus.c index 05016dc9c7..e9c17ae942 100644 --- a/cpus.c +++ b/cpus.c @@ -143,7 +143,7 @@ static int64_t cpu_get_icount_locked(void) if (!cpu_can_do_io(cpu)) { fprintf(stderr, "Bad clock read\n"); } - icount -= (env->icount_decr.u16.low + env->icount_extra); + icount -= (env->icount_decr.u16.low + cpu->icount_extra); } return qemu_icount_bias + (icount << icount_time_shift); } @@ -1236,6 +1236,7 @@ int vm_stop_force_state(RunState state) static int tcg_cpu_exec(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); int ret; #ifdef CONFIG_PROFILER int64_t ti; @@ -1248,9 +1249,9 @@ static int tcg_cpu_exec(CPUArchState *env) int64_t count; int64_t deadline; int decr; - qemu_icount -= (env->icount_decr.u16.low + env->icount_extra); + qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra); env->icount_decr.u16.low = 0; - env->icount_extra = 0; + cpu->icount_extra = 0; deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL); /* Maintain prior (possibly buggy) behaviour where if no deadline @@ -1267,7 +1268,7 @@ static int tcg_cpu_exec(CPUArchState *env) decr = (count > 0xffff) ? 0xffff : count; count -= decr; env->icount_decr.u16.low = decr; - env->icount_extra = count; + cpu->icount_extra = count; } ret = cpu_exec(env); #ifdef CONFIG_PROFILER @@ -1276,10 +1277,9 @@ static int tcg_cpu_exec(CPUArchState *env) if (use_icount) { /* Fold pending instructions back into the instruction counter, and clear the interrupt flag. */ - qemu_icount -= (env->icount_decr.u16.low - + env->icount_extra); + qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra); env->icount_decr.u32 = 0; - env->icount_extra = 0; + cpu->icount_extra = 0; } return ret; } diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 068b6c168f..8f9871c40e 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -149,7 +149,6 @@ typedef struct CPUWatchpoint { CPU_COMMON_TLB \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ - int64_t icount_extra; /* Instructions until next timer event. */ \ /* Number of cycles left, with interrupt flag in high bit. \ This allows a single read-compare-cbranch-write sequence to test \ for both decrementer underflow and exceptions. */ \ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index f80036e99b..012a7e6e79 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -157,6 +157,7 @@ struct kvm_run; * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this * CPU and return to its top level loop. * @singlestep_enabled: Flags for single-stepping. + * @icount_extra: Instructions until next timer event. * @can_do_io: Nonzero if memory-mapped IO is safe. * @env_ptr: Pointer to subclass-specific CPUArchState field. * @current_tb: Currently executing TB. @@ -196,6 +197,7 @@ struct CPUState { volatile sig_atomic_t tcg_exit_req; uint32_t interrupt_request; int singlestep_enabled; + int64_t icount_extra; AddressSpace *as; MemoryListener *tcg_as_listener; diff --git a/qom/cpu.c b/qom/cpu.c index e7d59997ee..a4f6a784af 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -241,6 +241,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->halted = 0; cpu->mem_io_pc = 0; cpu->mem_io_vaddr = 0; + cpu->icount_extra = 0; cpu->can_do_io = 0; } -- cgit v1.2.3-55-g7522 From 28ecfd7a62fafe8f4f0b35a157005f4d13913043 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 05:51:49 +0200 Subject: cpu: Move icount_decr field from CPU_COMMON to CPUState Signed-off-by: Andreas Färber --- cpu-exec.c | 4 ++-- cpus.c | 13 ++++++------- include/exec/cpu-defs.h | 20 -------------------- include/exec/gen-icount.h | 6 ++++-- include/qom/cpu.h | 19 +++++++++++++++++++ qom/cpu.c | 1 + translate-all.c | 15 ++++++++------- 7 files changed, 40 insertions(+), 38 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/cpu-exec.c b/cpu-exec.c index 4a03d83cba..9d98f210a4 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -649,7 +649,7 @@ int cpu_exec(CPUArchState *env) /* Instruction counter expired. */ int insns_left; tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); - insns_left = env->icount_decr.u32; + insns_left = cpu->icount_decr.u32; if (cpu->icount_extra && insns_left >= 0) { /* Refill decrementer and continue execution. */ cpu->icount_extra += insns_left; @@ -659,7 +659,7 @@ int cpu_exec(CPUArchState *env) insns_left = cpu->icount_extra; } cpu->icount_extra -= insns_left; - env->icount_decr.u16.low = insns_left; + cpu->icount_decr.u16.low = insns_left; } else { if (insns_left > 0) { /* Execute remaining instructions. */ diff --git a/cpus.c b/cpus.c index e9c17ae942..1104d6175c 100644 --- a/cpus.c +++ b/cpus.c @@ -139,11 +139,10 @@ static int64_t cpu_get_icount_locked(void) icount = qemu_icount; if (cpu) { - CPUArchState *env = cpu->env_ptr; if (!cpu_can_do_io(cpu)) { fprintf(stderr, "Bad clock read\n"); } - icount -= (env->icount_decr.u16.low + cpu->icount_extra); + icount -= (cpu->icount_decr.u16.low + cpu->icount_extra); } return qemu_icount_bias + (icount << icount_time_shift); } @@ -1249,8 +1248,8 @@ static int tcg_cpu_exec(CPUArchState *env) int64_t count; int64_t deadline; int decr; - qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra); - env->icount_decr.u16.low = 0; + qemu_icount -= (cpu->icount_decr.u16.low + cpu->icount_extra); + cpu->icount_decr.u16.low = 0; cpu->icount_extra = 0; deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL); @@ -1267,7 +1266,7 @@ static int tcg_cpu_exec(CPUArchState *env) qemu_icount += count; decr = (count > 0xffff) ? 0xffff : count; count -= decr; - env->icount_decr.u16.low = decr; + cpu->icount_decr.u16.low = decr; cpu->icount_extra = count; } ret = cpu_exec(env); @@ -1277,8 +1276,8 @@ static int tcg_cpu_exec(CPUArchState *env) if (use_icount) { /* Fold pending instructions back into the instruction counter, and clear the interrupt flag. */ - qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra); - env->icount_decr.u32 = 0; + qemu_icount -= (cpu->icount_decr.u16.low + cpu->icount_extra); + cpu->icount_decr.u32 = 0; cpu->icount_extra = 0; } return ret; diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 8f9871c40e..d036e8e350 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -118,18 +118,6 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); #endif -#ifdef HOST_WORDS_BIGENDIAN -typedef struct icount_decr_u16 { - uint16_t high; - uint16_t low; -} icount_decr_u16; -#else -typedef struct icount_decr_u16 { - uint16_t low; - uint16_t high; -} icount_decr_u16; -#endif - typedef struct CPUBreakpoint { target_ulong pc; int flags; /* BP_* */ @@ -149,14 +137,6 @@ typedef struct CPUWatchpoint { CPU_COMMON_TLB \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ - /* Number of cycles left, with interrupt flag in high bit. \ - This allows a single read-compare-cbranch-write sequence to test \ - for both decrementer underflow and exceptions. */ \ - union { \ - uint32_t u32; \ - icount_decr_u16 u16; \ - } icount_decr; \ - \ /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index f0dace3034..da53395de6 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -26,13 +26,15 @@ static inline void gen_tb_start(void) icount_label = gen_new_label(); count = tcg_temp_local_new_i32(); - tcg_gen_ld_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u32)); + tcg_gen_ld_i32(count, cpu_env, + -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); /* This is a horrid hack to allow fixing up the value later. */ icount_arg = tcg_ctx.gen_opparam_ptr + 1; tcg_gen_subi_i32(count, count, 0xdeadbeef); tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label); - tcg_gen_st16_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u16.low)); + tcg_gen_st16_i32(count, cpu_env, + -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low)); tcg_temp_free_i32(count); } diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 012a7e6e79..3156b16ad1 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -138,6 +138,18 @@ typedef struct CPUClass { const char *gdb_core_xml_file; } CPUClass; +#ifdef HOST_WORDS_BIGENDIAN +typedef struct icount_decr_u16 { + uint16_t high; + uint16_t low; +} icount_decr_u16; +#else +typedef struct icount_decr_u16 { + uint16_t low; + uint16_t high; +} icount_decr_u16; +#endif + struct KVMState; struct kvm_run; @@ -158,6 +170,9 @@ struct kvm_run; * CPU and return to its top level loop. * @singlestep_enabled: Flags for single-stepping. * @icount_extra: Instructions until next timer event. + * @icount_decr: Number of cycles left, with interrupt flag in high bit. + * This allows a single read-compare-cbranch-write sequence to test + * for both decrementer underflow and exceptions. * @can_do_io: Nonzero if memory-mapped IO is safe. * @env_ptr: Pointer to subclass-specific CPUArchState field. * @current_tb: Currently executing TB. @@ -223,6 +238,10 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; /* used by alpha TCG */ uint32_t halted; /* used by alpha, cris, ppc TCG */ + union { + uint32_t u32; + icount_decr_u16 u16; + } icount_decr; uint32_t can_do_io; }; diff --git a/qom/cpu.c b/qom/cpu.c index a4f6a784af..a4c5073951 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -242,6 +242,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->mem_io_pc = 0; cpu->mem_io_vaddr = 0; cpu->icount_extra = 0; + cpu->icount_decr.u32 = 0; cpu->can_do_io = 0; } diff --git a/translate-all.c b/translate-all.c index a1af5ef393..6bb3933523 100644 --- a/translate-all.c +++ b/translate-all.c @@ -217,7 +217,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, if (use_icount) { /* Reset the cycle counter to the start of the block. */ - env->icount_decr.u16.low += tb->icount; + cpu->icount_decr.u16.low += tb->icount; /* Clear the IO flag. */ cpu->can_do_io = 0; } @@ -242,7 +242,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env, while (s->gen_opc_instr_start[j] == 0) { j--; } - env->icount_decr.u16.low -= s->gen_opc_icount[j]; + cpu->icount_decr.u16.low -= s->gen_opc_icount[j]; restore_state_to_opc(env, tb, j); @@ -1409,7 +1409,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) } if (use_icount) { - env->icount_decr.u16.high = 0xffff; + cpu->icount_decr.u16.high = 0xffff; if (!cpu_can_do_io(cpu) && (mask & ~old_mask) != 0) { cpu_abort(env, "Raised interrupt while not in I/O function"); @@ -1425,6 +1425,7 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; must be at the end of the TB */ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) { + CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb; uint32_t n, cflags; target_ulong pc, cs_base; @@ -1435,11 +1436,11 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", (void *)retaddr); } - n = env->icount_decr.u16.low + tb->icount; + n = cpu->icount_decr.u16.low + tb->icount; cpu_restore_state_from_tb(tb, env, retaddr); /* Calculate how many instructions had been executed before the fault occurred. */ - n = n - env->icount_decr.u16.low; + n = n - cpu->icount_decr.u16.low; /* Generate a new TB ending on the I/O insn. */ n++; /* On MIPS and SH, delay slot instructions can only be restarted if @@ -1449,14 +1450,14 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) #if defined(TARGET_MIPS) if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { env->active_tc.PC -= 4; - env->icount_decr.u16.low++; + cpu->icount_decr.u16.low++; env->hflags &= ~MIPS_HFLAG_BMASK; } #elif defined(TARGET_SH4) if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 && n > 1) { env->pc -= 2; - env->icount_decr.u16.low++; + cpu->icount_decr.u16.low++; env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); } #endif -- cgit v1.2.3-55-g7522 From 8cd70437f385fc53f34481d506cf4a18ebe75976 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 06:03:38 +0200 Subject: cpu: Move tb_jmp_cache field from CPU_COMMON to CPUState Clear it on reset. Signed-off-by: Andreas Färber --- cpu-exec.c | 6 ++++-- cputlb.c | 2 +- include/exec/cpu-defs.h | 4 ---- include/qom/cpu.h | 4 ++++ qom/cpu.c | 1 + translate-all.c | 15 ++++++--------- 6 files changed, 16 insertions(+), 16 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/cpu-exec.c b/cpu-exec.c index 9d98f210a4..dd8da531d0 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -118,6 +118,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, target_ulong cs_base, uint64_t flags) { + CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb, **ptb1; unsigned int h; tb_page_addr_t phys_pc, phys_page1; @@ -165,12 +166,13 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, tcg_ctx.tb_ctx.tb_phys_hash[h] = tb; } /* we add the TB in the virtual pc hash table */ - env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; + cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; return tb; } static inline TranslationBlock *tb_find_fast(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; int flags; @@ -179,7 +181,7 @@ static inline TranslationBlock *tb_find_fast(CPUArchState *env) always be the same before a given translated block is executed. */ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; + tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || tb->flags != flags)) { tb = tb_find_slow(env, pc, cs_base, flags); diff --git a/cputlb.c b/cputlb.c index 0fbaa39412..0eb1801cc2 100644 --- a/cputlb.c +++ b/cputlb.c @@ -58,7 +58,7 @@ void tlb_flush(CPUArchState *env, int flush_global) cpu->current_tb = NULL; memset(env->tlb_table, -1, sizeof(env->tlb_table)); - memset(env->tb_jmp_cache, 0, sizeof(env->tb_jmp_cache)); + memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); env->tlb_flush_addr = -1; env->tlb_flush_mask = 0; diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index d036e8e350..42720948a1 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -61,9 +61,6 @@ typedef uint64_t target_ulong; #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ -#define TB_JMP_CACHE_BITS 12 -#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) - /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for addresses on the same page. The top bits are the same. This allows TLB invalidation to quickly clear a subset of the hash table. */ @@ -135,7 +132,6 @@ typedef struct CPUWatchpoint { #define CPU_COMMON \ /* soft mmu support */ \ CPU_COMMON_TLB \ - struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ \ /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 3156b16ad1..ada8a5afbf 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -153,6 +153,9 @@ typedef struct icount_decr_u16 { struct KVMState; struct kvm_run; +#define TB_JMP_CACHE_BITS 12 +#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) + /** * CPUState: * @cpu_index: CPU index (informative). @@ -219,6 +222,7 @@ struct CPUState { void *env_ptr; /* CPUArchState */ struct TranslationBlock *current_tb; + struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; struct GDBRegisterState *gdb_regs; int gdb_num_regs; int gdb_num_g_regs; diff --git a/qom/cpu.c b/qom/cpu.c index a4c5073951..fada2d4b92 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -244,6 +244,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->icount_extra = 0; cpu->icount_decr.u32 = 0; cpu->can_do_io = 0; + memset(cpu->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *)); } static bool cpu_common_has_work(CPUState *cs) diff --git a/translate-all.c b/translate-all.c index 6bb3933523..c067011684 100644 --- a/translate-all.c +++ b/translate-all.c @@ -704,9 +704,7 @@ void tb_flush(CPUArchState *env1) tcg_ctx.tb_ctx.nb_tbs = 0; CPU_FOREACH(cpu) { - CPUArchState *env = cpu->env_ptr; - - memset(env->tb_jmp_cache, 0, sizeof(env->tb_jmp_cache)); + memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); } memset(tcg_ctx.tb_ctx.tb_phys_hash, 0, sizeof(tcg_ctx.tb_ctx.tb_phys_hash)); @@ -857,10 +855,8 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) /* remove the TB from the hash list */ h = tb_jmp_cache_hash_func(tb->pc); CPU_FOREACH(cpu) { - CPUArchState *env = cpu->env_ptr; - - if (env->tb_jmp_cache[h] == tb) { - env->tb_jmp_cache[h] = NULL; + if (cpu->tb_jmp_cache[h] == tb) { + cpu->tb_jmp_cache[h] = NULL; } } @@ -1484,16 +1480,17 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr) void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr) { + CPUState *cpu = ENV_GET_CPU(env); unsigned int i; /* Discard jump cache entries for any tb which might potentially overlap the flushed page. */ i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); - memset(&env->tb_jmp_cache[i], 0, + memset(&cpu->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); i = tb_jmp_cache_hash_page(addr); - memset(&env->tb_jmp_cache[i], 0, + memset(&cpu->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); } -- cgit v1.2.3-55-g7522 From 6f03bef0ffc5cd75ac5ffcca0383c489ae48108c Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 06:22:03 +0200 Subject: cpu: Move jmp_env field from CPU_COMMON to CPUState Signed-off-by: Andreas Färber --- cpu-exec.c | 8 +++++--- include/exec/cpu-defs.h | 2 -- include/qom/cpu.h | 2 ++ user-exec.c | 3 ++- 4 files changed, 9 insertions(+), 6 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/cpu-exec.c b/cpu-exec.c index dd8da531d0..3e17ff534d 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -28,7 +28,7 @@ void cpu_loop_exit(CPUArchState *env) CPUState *cpu = ENV_GET_CPU(env); cpu->current_tb = NULL; - siglongjmp(env->jmp_env, 1); + siglongjmp(cpu->jmp_env, 1); } /* exit the current TB from a signal handler. The host registers are @@ -37,10 +37,12 @@ void cpu_loop_exit(CPUArchState *env) #if defined(CONFIG_SOFTMMU) void cpu_resume_from_signal(CPUArchState *env, void *puc) { + CPUState *cpu = ENV_GET_CPU(env); + /* XXX: restore cpu registers saved in host registers */ env->exception_index = -1; - siglongjmp(env->jmp_env, 1); + siglongjmp(cpu->jmp_env, 1); } #endif @@ -284,7 +286,7 @@ int cpu_exec(CPUArchState *env) /* prepare setjmp context for exception handling */ for(;;) { - if (sigsetjmp(env->jmp_env, 0) == 0) { + if (sigsetjmp(cpu->jmp_env, 0) == 0) { /* if an exception is pending, we execute it here */ if (env->exception_index >= 0) { if (env->exception_index >= EXCP_INTERRUPT) { diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 42720948a1..5fbdc9c4a9 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -24,7 +24,6 @@ #endif #include "config.h" -#include #include #include "qemu/osdep.h" #include "qemu/queue.h" @@ -141,7 +140,6 @@ typedef struct CPUWatchpoint { CPUWatchpoint *watchpoint_hit; \ \ /* Core interrupt code */ \ - sigjmp_buf jmp_env; \ int exception_index; \ \ /* user data */ \ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index ada8a5afbf..04bfd72326 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -21,6 +21,7 @@ #define QEMU_CPU_H #include +#include #include "hw/qdev-core.h" #include "exec/hwaddr.h" #include "qemu/queue.h" @@ -216,6 +217,7 @@ struct CPUState { uint32_t interrupt_request; int singlestep_enabled; int64_t icount_extra; + sigjmp_buf jmp_env; AddressSpace *as; MemoryListener *tcg_as_listener; diff --git a/user-exec.c b/user-exec.c index d850d41d45..dec636eb1e 100644 --- a/user-exec.c +++ b/user-exec.c @@ -52,6 +52,7 @@ static void exception_action(CPUArchState *env1) */ void cpu_resume_from_signal(CPUArchState *env1, void *puc) { + CPUState *cpu = ENV_GET_CPU(env1); #ifdef __linux__ struct ucontext *uc = puc; #elif defined(__OpenBSD__) @@ -71,7 +72,7 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc) #endif } env1->exception_index = -1; - siglongjmp(env1->jmp_env, 1); + siglongjmp(cpu->jmp_env, 1); } /* 'pc' is the host PC at which the exception was raised. 'address' is -- cgit v1.2.3-55-g7522 From 27103424c40ce71053c07d8a54ef431365fa9b7f Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 08:31:06 +0200 Subject: cpu: Move exception_index field from CPU_COMMON to CPUState Signed-off-by: Andreas Färber --- cpu-exec.c | 50 +++++++++++++++++++++--------------------- exec.c | 2 +- hw/ppc/e500.c | 3 +-- hw/ppc/ppce500_spin.c | 2 +- hw/ppc/spapr_hcall.c | 2 +- hw/s390x/s390-virtio.c | 8 +++---- include/exec/cpu-defs.h | 3 --- include/qom/cpu.h | 1 + linux-user/signal.c | 7 +++--- target-alpha/helper.c | 18 ++++++++++----- target-alpha/mem_helper.c | 4 +++- target-arm/helper.c | 25 ++++++++++----------- target-arm/op_helper.c | 20 ++++++++++++----- target-cris/helper.c | 18 +++++++-------- target-cris/op_helper.c | 6 +++-- target-i386/excp_helper.c | 4 +++- target-i386/helper.c | 6 ++--- target-i386/mem_helper.c | 5 +++-- target-i386/misc_helper.c | 9 +++++--- target-i386/seg_helper.c | 8 ++++--- target-i386/svm_helper.c | 12 +++++----- target-lm32/helper.c | 12 +++++----- target-lm32/op_helper.c | 6 +++-- target-m68k/helper.c | 2 +- target-m68k/op_helper.c | 22 +++++++++---------- target-m68k/qregs.def | 1 - target-m68k/translate.c | 5 +++++ target-microblaze/helper.c | 16 ++++++-------- target-microblaze/op_helper.c | 4 +++- target-mips/helper.c | 31 ++++++++++++++------------ target-mips/op_helper.c | 9 +++++--- target-mips/translate.c | 4 +--- target-moxie/helper.c | 21 ++++++++++-------- target-openrisc/cpu.c | 2 +- target-openrisc/exception.c | 4 +++- target-openrisc/interrupt.c | 12 +++++----- target-openrisc/mmu.c | 3 ++- target-ppc/excp_helper.c | 19 +++++++++------- target-ppc/fpu_helper.c | 26 +++++++++++++++------- target-ppc/kvm.c | 2 +- target-ppc/mmu-hash32.c | 24 ++++++++++---------- target-ppc/mmu-hash64.c | 15 +++++++------ target-ppc/mmu_helper.c | 43 ++++++++++++++++++------------------ target-ppc/translate_init.c | 2 +- target-ppc/user_only_helper.c | 2 +- target-s390x/helper.c | 39 ++++++++++++++++----------------- target-s390x/mem_helper.c | 9 ++++---- target-s390x/misc_helper.c | 15 +++++++++---- target-sh4/helper.c | 51 +++++++++++++++++++++---------------------- target-sh4/op_helper.c | 4 +++- target-sparc/helper.c | 10 ++++++--- target-sparc/int32_helper.c | 8 +++---- target-sparc/int64_helper.c | 6 ++--- target-sparc/ldst_helper.c | 2 +- target-sparc/mmu_helper.c | 22 +++++++++---------- target-unicore32/op_helper.c | 4 +++- target-unicore32/softmmu.c | 8 +++---- target-xtensa/helper.c | 20 +++++++++-------- target-xtensa/op_helper.c | 4 +++- user-exec.c | 6 +++-- 60 files changed, 389 insertions(+), 319 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/cpu-exec.c b/cpu-exec.c index 3e17ff534d..798dc084d9 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -41,7 +41,7 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc) /* XXX: restore cpu registers saved in host registers */ - env->exception_index = -1; + cpu->exception_index = -1; siglongjmp(cpu->jmp_env, 1); } #endif @@ -282,16 +282,16 @@ int cpu_exec(CPUArchState *env) #else #error unsupported target CPU #endif - env->exception_index = -1; + cpu->exception_index = -1; /* prepare setjmp context for exception handling */ for(;;) { if (sigsetjmp(cpu->jmp_env, 0) == 0) { /* if an exception is pending, we execute it here */ - if (env->exception_index >= 0) { - if (env->exception_index >= EXCP_INTERRUPT) { + if (cpu->exception_index >= 0) { + if (cpu->exception_index >= EXCP_INTERRUPT) { /* exit request from the cpu execution loop */ - ret = env->exception_index; + ret = cpu->exception_index; if (ret == EXCP_DEBUG) { cpu_handle_debug_exception(env); } @@ -304,11 +304,11 @@ int cpu_exec(CPUArchState *env) #if defined(TARGET_I386) cc->do_interrupt(cpu); #endif - ret = env->exception_index; + ret = cpu->exception_index; break; #else cc->do_interrupt(cpu); - env->exception_index = -1; + cpu->exception_index = -1; #endif } } @@ -323,7 +323,7 @@ int cpu_exec(CPUArchState *env) } if (interrupt_request & CPU_INTERRUPT_DEBUG) { cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; - env->exception_index = EXCP_DEBUG; + cpu->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ @@ -332,7 +332,7 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_HALT) { cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; - env->exception_index = EXCP_HLT; + cpu->exception_index = EXCP_HLT; cpu_loop_exit(env); } #endif @@ -347,7 +347,7 @@ int cpu_exec(CPUArchState *env) cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0); do_cpu_init(x86_cpu); - env->exception_index = EXCP_HALTED; + cpu->exception_index = EXCP_HALTED; cpu_loop_exit(env); } else if (interrupt_request & CPU_INTERRUPT_SIPI) { do_cpu_sipi(x86_cpu); @@ -419,7 +419,7 @@ int cpu_exec(CPUArchState *env) #elif defined(TARGET_LM32) if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -428,7 +428,7 @@ int cpu_exec(CPUArchState *env) && (env->sregs[SR_MSR] & MSR_IE) && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) && !(env->iflags & (D_FLAG | IMM_FLAG))) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -436,7 +436,7 @@ int cpu_exec(CPUArchState *env) if ((interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { /* Raise it */ - env->exception_index = EXCP_EXT_INTERRUPT; + cpu->exception_index = EXCP_EXT_INTERRUPT; env->error_code = 0; cc->do_interrupt(cpu); next_tb = 0; @@ -453,7 +453,7 @@ int cpu_exec(CPUArchState *env) idx = EXCP_TICK; } if (idx >= 0) { - env->exception_index = idx; + cpu->exception_index = idx; cc->do_interrupt(cpu); next_tb = 0; } @@ -468,7 +468,7 @@ int cpu_exec(CPUArchState *env) if (((type == TT_EXTINT) && cpu_pil_allowed(env, pil)) || type != TT_EXTINT) { - env->exception_index = env->interrupt_index; + cpu->exception_index = env->interrupt_index; cc->do_interrupt(cpu); next_tb = 0; } @@ -477,7 +477,7 @@ int cpu_exec(CPUArchState *env) #elif defined(TARGET_ARM) if (interrupt_request & CPU_INTERRUPT_FIQ && !(env->daif & PSTATE_F)) { - env->exception_index = EXCP_FIQ; + cpu->exception_index = EXCP_FIQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -493,14 +493,14 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_HARD && ((IS_M(env) && env->regs[15] < 0xfffffff0) || !(env->daif & PSTATE_I))) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } #elif defined(TARGET_UNICORE32) if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_asr & ASR_I)) { - env->exception_index = UC32_EXCP_INTR; + cpu->exception_index = UC32_EXCP_INTR; cc->do_interrupt(cpu); next_tb = 0; } @@ -535,7 +535,7 @@ int cpu_exec(CPUArchState *env) } } if (idx >= 0) { - env->exception_index = idx; + cpu->exception_index = idx; env->error_code = 0; cc->do_interrupt(cpu); next_tb = 0; @@ -545,7 +545,7 @@ int cpu_exec(CPUArchState *env) if (interrupt_request & CPU_INTERRUPT_HARD && (env->pregs[PR_CCS] & I_FLAG) && !env->locked_irq) { - env->exception_index = EXCP_IRQ; + cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -557,7 +557,7 @@ int cpu_exec(CPUArchState *env) m_flag_archval = M_FLAG_V32; } if ((env->pregs[PR_CCS] & m_flag_archval)) { - env->exception_index = EXCP_NMI; + cpu->exception_index = EXCP_NMI; cc->do_interrupt(cpu); next_tb = 0; } @@ -571,7 +571,7 @@ int cpu_exec(CPUArchState *env) hardware doesn't rely on this, so we provide/save the vector when the interrupt is first signalled. */ - env->exception_index = env->pending_vector; + cpu->exception_index = env->pending_vector; do_interrupt_m68k_hardirq(env); next_tb = 0; } @@ -583,7 +583,7 @@ int cpu_exec(CPUArchState *env) } #elif defined(TARGET_XTENSA) if (interrupt_request & CPU_INTERRUPT_HARD) { - env->exception_index = EXC_IRQ; + cpu->exception_index = EXC_IRQ; cc->do_interrupt(cpu); next_tb = 0; } @@ -599,7 +599,7 @@ int cpu_exec(CPUArchState *env) } if (unlikely(cpu->exit_request)) { cpu->exit_request = 0; - env->exception_index = EXCP_INTERRUPT; + cpu->exception_index = EXCP_INTERRUPT; cpu_loop_exit(env); } spin_lock(&tcg_ctx.tb_ctx.tb_lock); @@ -669,7 +669,7 @@ int cpu_exec(CPUArchState *env) /* Execute remaining instructions. */ cpu_exec_nocache(env, insns_left, tb); } - env->exception_index = EXCP_INTERRUPT; + cpu->exception_index = EXCP_INTERRUPT; next_tb = 0; cpu_loop_exit(env); } diff --git a/exec.c b/exec.c index 6666f6d396..26ed9ccd0c 100644 --- a/exec.c +++ b/exec.c @@ -1595,7 +1595,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) env->watchpoint_hit = wp; tb_check_watchpoint(env); if (wp->flags & BP_STOP_BEFORE_ACCESS) { - env->exception_index = EXCP_DEBUG; + cpu->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 8a08752613..d7ba25f379 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -472,14 +472,13 @@ static void ppce500_cpu_reset_sec(void *opaque) { PowerPCCPU *cpu = opaque; CPUState *cs = CPU(cpu); - CPUPPCState *env = &cpu->env; cpu_reset(cs); /* Secondary CPU starts in halted state for now. Needs to change when implementing non-kernel boot. */ cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } static void ppce500_cpu_reset(void *opaque) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index 78b23fa597..f9fdc8c548 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -117,7 +117,7 @@ static void spin_kick(void *data) mmubooke_create_initial_mapping(env, 0, map_start, map_size); cpu->halted = 0; - env->exception_index = -1; + cpu->exception_index = -1; cpu->stopped = false; qemu_cpu_kick(cpu); } diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 1de82f831c..e999bbaea0 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -529,7 +529,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, hreg_compute_hflags(env); if (!cpu_has_work(cs)) { cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cs->exit_request = 1; } return H_SUCCESS; diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c index 0f03fd18b9..aef200310c 100644 --- a/hw/s390x/s390-virtio.c +++ b/hw/s390x/s390-virtio.c @@ -135,25 +135,23 @@ static unsigned s390_running_cpus; void s390_add_running_cpu(S390CPU *cpu) { CPUState *cs = CPU(cpu); - CPUS390XState *env = &cpu->env; if (cs->halted) { s390_running_cpus++; cs->halted = 0; - env->exception_index = -1; + cs->exception_index = -1; } } unsigned s390_del_running_cpu(S390CPU *cpu) { CPUState *cs = CPU(cpu); - CPUS390XState *env = &cpu->env; if (cs->halted == 0) { assert(s390_running_cpus >= 1); s390_running_cpus--; cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } return s390_running_cpus; } @@ -196,7 +194,7 @@ void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys) ipi_states[i] = cpu; cs->halted = 1; - cpu->env.exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cpu->env.storage_keys = storage_keys; } } diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 5fbdc9c4a9..bec06e8f99 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -139,9 +139,6 @@ typedef struct CPUWatchpoint { QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ CPUWatchpoint *watchpoint_hit; \ \ - /* Core interrupt code */ \ - int exception_index; \ - \ /* user data */ \ void *opaque; \ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 04bfd72326..a385b9f71d 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -249,6 +249,7 @@ struct CPUState { icount_decr_u16 u16; } icount_decr; uint32_t can_do_io; + int32_t exception_index; /* used by m68k TCG */ }; QTAILQ_HEAD(CPUTailQ, CPUState); diff --git a/linux-user/signal.c b/linux-user/signal.c index c8a1da0749..acf10328ee 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -774,8 +774,9 @@ static int setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr) { - int err = 0; - uint16_t magic; + CPUState *cs = CPU(x86_env_get_cpu(env)); + int err = 0; + uint16_t magic; /* already locked in setup_frame() */ err |= __put_user(env->segs[R_GS].selector, (unsigned int *)&sc->gs); @@ -790,7 +791,7 @@ setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate, err |= __put_user(env->regs[R_EDX], &sc->edx); err |= __put_user(env->regs[R_ECX], &sc->ecx); err |= __put_user(env->regs[R_EAX], &sc->eax); - err |= __put_user(env->exception_index, &sc->trapno); + err |= __put_user(cs->exception_index, &sc->trapno); err |= __put_user(env->error_code, &sc->err); err |= __put_user(env->eip, &sc->eip); err |= __put_user(env->segs[R_CS].selector, (unsigned int *)&sc->cs); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 9c94b4382c..14f59a27a8 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -173,7 +173,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, { AlphaCPU *cpu = ALPHA_CPU(cs); - cpu->env.exception_index = EXCP_MMFAULT; + cs->exception_index = EXCP_MMFAULT; cpu->env.trap_arg0 = address; return 1; } @@ -338,7 +338,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw, fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot); if (unlikely(fail >= 0)) { - env->exception_index = EXCP_MMFAULT; + cs->exception_index = EXCP_MMFAULT; env->trap_arg0 = addr; env->trap_arg1 = fail; env->trap_arg2 = (rw == 2 ? -1 : rw); @@ -355,7 +355,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) { AlphaCPU *cpu = ALPHA_CPU(cs); CPUAlphaState *env = &cpu->env; - int i = env->exception_index; + int i = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; @@ -406,7 +406,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) ++count, name, env->error_code, env->pc, env->ir[IR_SP]); } - env->exception_index = -1; + cs->exception_index = -1; #if !defined(CONFIG_USER_ONLY) switch (i) { @@ -508,7 +508,10 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, We expect that ENV->PC has already been updated. */ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) { - env->exception_index = excp; + AlphaCPU *cpu = alpha_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; env->error_code = error; cpu_loop_exit(env); } @@ -517,7 +520,10 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, int excp, int error) { - env->exception_index = excp; + AlphaCPU *cpu = alpha_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; env->error_code = error; if (retaddr) { cpu_restore_state(env, retaddr); diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index d195935a96..23878bad80 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -99,6 +99,8 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v) static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { + AlphaCPU *cpu = alpha_env_get_cpu(env); + CPUState *cs = CPU(cpu); uint64_t pc; uint32_t insn; @@ -112,7 +114,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr, env->trap_arg0 = addr; env->trap_arg1 = insn >> 26; /* opcode */ env->trap_arg2 = (insn >> 21) & 31; /* dest regno */ - env->exception_index = EXCP_UNALIGN; + cs->exception_index = EXCP_UNALIGN; env->error_code = 0; cpu_loop_exit(env); } diff --git a/target-arm/helper.c b/target-arm/helper.c index d3e68a6e24..0d173ebfcf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2649,10 +2649,7 @@ uint32_t HELPER(rbit)(uint32_t x) void arm_cpu_do_interrupt(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, @@ -2662,10 +2659,10 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, CPUARMState *env = &cpu->env; if (rw == 2) { - env->exception_index = EXCP_PREFETCH_ABORT; + cs->exception_index = EXCP_PREFETCH_ABORT; env->cp15.c6_insn = address; } else { - env->exception_index = EXCP_DATA_ABORT; + cs->exception_index = EXCP_DATA_ABORT; env->cp15.c6_data = address; } return 1; @@ -2851,7 +2848,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) uint32_t lr; uint32_t addr; - arm_log_exception(env->exception_index); + arm_log_exception(cs->exception_index); lr = 0xfffffff1; if (env->v7m.current_sp) @@ -2863,7 +2860,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) handle it. */ /* TODO: Need to escalate if the current priority is higher than the one we're raising. */ - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_UDEF: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); return; @@ -2895,7 +2892,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) do_v7m_exception_exit(env); return; default: - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } @@ -2936,10 +2933,10 @@ void arm_cpu_do_interrupt(CPUState *cs) assert(!IS_M(env)); - arm_log_exception(env->exception_index); + arm_log_exception(cs->exception_index); /* TODO: Vectored interrupt controller. */ - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_UDEF: new_mode = ARM_CPU_MODE_UND; addr = 0x04; @@ -3020,7 +3017,7 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } /* High vectors. */ @@ -3650,13 +3647,13 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, if (access_type == 2) { env->cp15.c5_insn = ret; env->cp15.c6_insn = address; - env->exception_index = EXCP_PREFETCH_ABORT; + cs->exception_index = EXCP_PREFETCH_ABORT; } else { env->cp15.c5_data = ret; if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) env->cp15.c5_data |= (1 << 11); env->cp15.c6_data = address; - env->exception_index = EXCP_DATA_ABORT; + cs->exception_index = EXCP_DATA_ABORT; } return 1; } diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index ced6a7b83c..931536ea4f 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -24,7 +24,10 @@ static void raise_exception(CPUARMState *env, int tt) { - env->exception_index = tt; + ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); + + cs->exception_index = tt; cpu_loop_exit(env); } @@ -75,15 +78,16 @@ void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); int ret; - ret = arm_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - raise_exception(env, env->exception_index); + raise_exception(env, cs->exception_index); } } #endif @@ -221,23 +225,27 @@ void HELPER(wfi)(CPUARMState *env) { CPUState *cs = CPU(arm_env_get_cpu(env)); - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cs->halted = 1; cpu_loop_exit(env); } void HELPER(wfe)(CPUARMState *env) { + CPUState *cs = CPU(arm_env_get_cpu(env)); + /* Don't actually halt the CPU, just yield back to top * level loop */ - env->exception_index = EXCP_YIELD; + cs->exception_index = EXCP_YIELD; cpu_loop_exit(env); } void HELPER(exception)(CPUARMState *env, uint32_t excp) { - env->exception_index = excp; + CPUState *cs = CPU(arm_env_get_cpu(env)); + + cs->exception_index = excp; cpu_loop_exit(env); } diff --git a/target-cris/helper.c b/target-cris/helper.c index 857cc99b29..d7fdc33647 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -41,7 +41,7 @@ void cris_cpu_do_interrupt(CPUState *cs) CRISCPU *cpu = CRIS_CPU(cs); CPUCRISState *env = &cpu->env; - env->exception_index = -1; + cs->exception_index = -1; env->pregs[PR_ERP] = env->pc; } @@ -55,7 +55,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, { CRISCPU *cpu = CRIS_CPU(cs); - cpu->env.exception_index = 0xaa; + cs->exception_index = 0xaa; cpu->env.pregs[PR_EDA] = address; cpu_dump_state(cs, stderr, fprintf, 0); return 1; @@ -88,7 +88,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, rw, mmu_idx, 0); if (miss) { - if (env->exception_index == EXCP_BUSFAULT) { + if (cs->exception_index == EXCP_BUSFAULT) { cpu_abort(env, "CRIS: Illegal recursive bus fault." "addr=%" VADDR_PRIx " rw=%d\n", @@ -96,7 +96,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, } env->pregs[PR_EDA] = address; - env->exception_index = EXCP_BUSFAULT; + cs->exception_index = EXCP_BUSFAULT; env->fault_vector = res.bf_vec; r = 1; } else { @@ -125,7 +125,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", - env->exception_index, + cs->exception_index, cs->interrupt_request); if (env->dslot) { @@ -134,7 +134,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) } assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_BREAK: /* These exceptions are genereated by the core itself. ERP should point to the insn following the brk. */ @@ -187,10 +187,10 @@ void cris_cpu_do_interrupt(CPUState *cs) int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", - env->exception_index, + cs->exception_index, cs->interrupt_request); - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_BREAK: /* These exceptions are genereated by the core itself. ERP should point to the insn following the brk. */ @@ -253,7 +253,7 @@ void cris_cpu_do_interrupt(CPUState *cs) /* Clear the excption_index to avoid spurios hw_aborts for recursive bus faults. */ - env->exception_index = -1; + cs->exception_index = -1; D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n", __func__, env->pc, ex_vec, diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c index 4a6215d5d6..9b20b94d9b 100644 --- a/target-cris/op_helper.c +++ b/target-cris/op_helper.c @@ -79,8 +79,10 @@ void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx, void helper_raise_exception(CPUCRISState *env, uint32_t index) { - env->exception_index = index; - cpu_loop_exit(env); + CPUState *cs = CPU(cris_env_get_cpu(env)); + + cs->exception_index = index; + cpu_loop_exit(env); } void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c index 5319aef7df..ec76eba760 100644 --- a/target-i386/excp_helper.c +++ b/target-i386/excp_helper.c @@ -94,6 +94,8 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, int is_int, int error_code, int next_eip_addend) { + CPUState *cs = CPU(x86_env_get_cpu(env)); + if (!is_int) { cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno, error_code); @@ -102,7 +104,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, cpu_svm_check_intercept_param(env, SVM_EXIT_SWINT, 0); } - env->exception_index = intno; + cs->exception_index = intno; env->error_code = error_code; env->exception_is_int = is_int; env->exception_next_eip = env->eip + next_eip_addend; diff --git a/target-i386/helper.c b/target-i386/helper.c index 4910e40c17..6d9bd71a3a 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -496,7 +496,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, env->cr[2] = addr; env->error_code = (is_write << PG_ERROR_W_BIT); env->error_code |= PG_ERROR_U_MASK; - env->exception_index = EXCP0E_PAGE; + cs->exception_index = EXCP0E_PAGE; return 1; } @@ -561,7 +561,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, sext = (int64_t)addr >> 47; if (sext != 0 && sext != -1) { env->error_code = 0; - env->exception_index = EXCP0D_GPF; + cs->exception_index = EXCP0D_GPF; return 1; } @@ -892,7 +892,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, env->cr[2] = addr; } env->error_code = error_code; - env->exception_index = EXCP0E_PAGE; + cs->exception_index = EXCP0E_PAGE; return 1; } diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index 5b25ccd605..c0d3b45552 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -136,15 +136,16 @@ void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { X86CPU *cpu = x86_env_get_cpu(env); + CPUState *cs = CPU(cpu); int ret; - ret = x86_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - raise_exception_err(env, env->exception_index, env->error_code); + raise_exception_err(env, cs->exception_index, env->error_code); } } #endif diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 47f6a2f7c1..582ad34ffe 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -568,10 +568,11 @@ void helper_rdmsr(CPUX86State *env) static void do_pause(X86CPU *cpu) { + CPUState *cs = CPU(cpu); CPUX86State *env = &cpu->env; /* Just let another CPU run. */ - env->exception_index = EXCP_INTERRUPT; + cs->exception_index = EXCP_INTERRUPT; cpu_loop_exit(env); } @@ -582,7 +583,7 @@ static void do_hlt(X86CPU *cpu) env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cpu_loop_exit(env); } @@ -638,6 +639,8 @@ void helper_pause(CPUX86State *env, int next_eip_addend) void helper_debug(CPUX86State *env) { - env->exception_index = EXCP_DEBUG; + CPUState *cs = CPU(x86_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index 9dda02d2f1..c8fd572d99 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -935,7 +935,9 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int, #if defined(CONFIG_USER_ONLY) void helper_syscall(CPUX86State *env, int next_eip_addend) { - env->exception_index = EXCP_SYSCALL; + CPUState *cs = CPU(x86_env_get_cpu(env)); + + cs->exception_index = EXCP_SYSCALL; env->exception_next_eip = env->eip + next_eip_addend; cpu_loop_exit(env); } @@ -1248,7 +1250,7 @@ void x86_cpu_do_interrupt(CPUState *cs) /* if user mode only, we simulate a fake exception which will be handled outside the cpu execution loop */ - do_interrupt_user(env, env->exception_index, + do_interrupt_user(env, cs->exception_index, env->exception_is_int, env->error_code, env->exception_next_eip); @@ -1258,7 +1260,7 @@ void x86_cpu_do_interrupt(CPUState *cs) /* simulate a real cpu exception. On i386, it can trigger new exceptions, but we do not handle double or triple faults yet. */ - do_interrupt_all(cpu, env->exception_index, + do_interrupt_all(cpu, cs->exception_index, env->exception_is_int, env->error_code, env->exception_next_eip, 0); diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index bc33e61672..5e0504d7f0 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -320,7 +320,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) /* FIXME: need to implement valid_err */ switch (event_inj & SVM_EVTINJ_TYPE_MASK) { case SVM_EVTINJ_TYPE_INTR: - env->exception_index = vector; + cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = -1; @@ -329,7 +329,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) do_interrupt_x86_hardirq(env, vector, 1); break; case SVM_EVTINJ_TYPE_NMI: - env->exception_index = EXCP02_NMI; + cs->exception_index = EXCP02_NMI; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = env->eip; @@ -337,7 +337,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) cpu_loop_exit(env); break; case SVM_EVTINJ_TYPE_EXEPT: - env->exception_index = vector; + cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 0; env->exception_next_eip = -1; @@ -345,7 +345,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) cpu_loop_exit(env); break; case SVM_EVTINJ_TYPE_SOFT: - env->exception_index = vector; + cs->exception_index = vector; env->error_code = event_inj_err; env->exception_is_int = 1; env->exception_next_eip = env->eip; @@ -353,7 +353,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) cpu_loop_exit(env); break; } - qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", env->exception_index, + qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index, env->error_code); } } @@ -768,7 +768,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) #GP fault is delivered inside the host. */ /* remove any pending exception */ - env->exception_index = -1; + cs->exception_index = -1; env->error_code = 0; env->old_exception = -1; diff --git a/target-lm32/helper.c b/target-lm32/helper.c index ce6dd45552..e5536c0ecb 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -147,9 +147,9 @@ void lm32_cpu_do_interrupt(CPUState *cs) CPULM32State *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, - "exception at pc=%x type=%x\n", env->pc, env->exception_index); + "exception at pc=%x type=%x\n", env->pc, cs->exception_index); - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_INSN_BUS_ERROR: case EXCP_DATA_BUS_ERROR: case EXCP_DIVIDE_BY_ZERO: @@ -160,9 +160,9 @@ void lm32_cpu_do_interrupt(CPUState *cs) env->ie |= (env->ie & IE_IE) ? IE_EIE : 0; env->ie &= ~IE_IE; if (env->dc & DC_RE) { - env->pc = env->deba + (env->exception_index * 32); + env->pc = env->deba + (cs->exception_index * 32); } else { - env->pc = env->eba + (env->exception_index * 32); + env->pc = env->eba + (cs->exception_index * 32); } log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; @@ -172,12 +172,12 @@ void lm32_cpu_do_interrupt(CPUState *cs) env->regs[R_BA] = env->pc; env->ie |= (env->ie & IE_IE) ? IE_BIE : 0; env->ie &= ~IE_IE; - env->pc = env->deba + (env->exception_index * 32); + env->pc = env->deba + (cs->exception_index * 32); log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; default: cpu_abort(env, "unhandled exception type=%d\n", - env->exception_index); + cs->exception_index); break; } } diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c index 774dc65cf2..3b513a7edb 100644 --- a/target-lm32/op_helper.c +++ b/target-lm32/op_helper.c @@ -25,7 +25,9 @@ void raise_exception(CPULM32State *env, int index) { - env->exception_index = index; + CPUState *cs = CPU(lm32_env_get_cpu(env)); + + cs->exception_index = index; cpu_loop_exit(env); } @@ -39,7 +41,7 @@ void HELPER(hlt)(CPULM32State *env) CPUState *cs = CPU(lm32_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cpu_loop_exit(env); } diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 0ffb861d08..fb43b81505 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -282,7 +282,7 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, { M68kCPU *cpu = M68K_CPU(cs); - cpu->env.exception_index = EXCP_ACCESS; + cs->exception_index = EXCP_ACCESS; cpu->env.mmu.ar = address; return 1; } diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index 539d1d6724..930d7c8d04 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -23,10 +23,7 @@ void m68k_cpu_do_interrupt(CPUState *cs) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } void do_interrupt_m68k_hardirq(CPUM68KState *env) @@ -88,7 +85,7 @@ static void do_rte(CPUM68KState *env) static void do_interrupt_all(CPUM68KState *env, int is_hw) { - CPUState *cs; + CPUState *cs = CPU(m68k_env_get_cpu(env)); uint32_t sp; uint32_t fmt; uint32_t retaddr; @@ -98,7 +95,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) retaddr = env->pc; if (!is_hw) { - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_RTE: /* Return from an exception. */ do_rte(env); @@ -113,20 +110,19 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) do_m68k_semihosting(env, env->dregs[0]); return; } - cs = CPU(m68k_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; cpu_loop_exit(env); return; } - if (env->exception_index >= EXCP_TRAP0 - && env->exception_index <= EXCP_TRAP15) { + if (cs->exception_index >= EXCP_TRAP0 + && cs->exception_index <= EXCP_TRAP15) { /* Move the PC after the trap instruction. */ retaddr += 2; } } - vector = env->exception_index << 2; + vector = cs->exception_index << 2; sp = env->aregs[7]; @@ -169,7 +165,9 @@ void do_interrupt_m68k_hardirq(CPUM68KState *env) static void raise_exception(CPUM68KState *env, int tt) { - env->exception_index = tt; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + + cs->exception_index = tt; cpu_loop_exit(env); } diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def index 4235b02764..204663e1aa 100644 --- a/target-m68k/qregs.def +++ b/target-m68k/qregs.def @@ -7,6 +7,5 @@ DEFO32(CC_SRC, cc_src) DEFO32(CC_X, cc_x) DEFO32(DIV1, div1) DEFO32(DIV2, div2) -DEFO32(EXCEPTION, exception_index) DEFO32(MACSR, macsr) DEFO32(MAC_MASK, mac_mask) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index f747c13d5f..4f06443532 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -43,6 +43,7 @@ #undef DEFF64 static TCGv_i32 cpu_halted; +static TCGv_i32 cpu_exception_index; static TCGv_ptr cpu_env; @@ -81,6 +82,10 @@ void m68k_tcg_init(void) cpu_halted = tcg_global_mem_new_i32(TCG_AREG0, -offsetof(M68kCPU, env) + offsetof(CPUState, halted), "HALTED"); + cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0, + -offsetof(M68kCPU, env) + + offsetof(CPUState, exception_index), + "EXCEPTION"); cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index d03f3690bb..48254154d3 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -31,7 +31,7 @@ void mb_cpu_do_interrupt(CPUState *cs) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; - env->exception_index = -1; + cs->exception_index = -1; env->res_addr = RES_ADDR_NONE; env->regs[14] = env->sregs[SR_PC]; } @@ -39,9 +39,7 @@ void mb_cpu_do_interrupt(CPUState *cs) int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - - cpu->env.exception_index = 0xaa; + cs->exception_index = 0xaa; cpu_dump_state(cs, stderr, fprintf, 0); return 1; } @@ -99,12 +97,12 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, break; } - if (env->exception_index == EXCP_MMU) { + if (cs->exception_index == EXCP_MMU) { cpu_abort(env, "recursive faults\n"); } /* TLB miss. */ - env->exception_index = EXCP_MMU; + cs->exception_index = EXCP_MMU; } } else { /* MMU disabled or not available. */ @@ -127,7 +125,7 @@ void mb_cpu_do_interrupt(CPUState *cs) assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ env->res_addr = RES_ADDR_NONE; - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_HW_EXCP: if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { qemu_log("Exception raised on system without exceptions!\n"); @@ -253,7 +251,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; - if (env->exception_index == EXCP_HW_BREAK) { + if (cs->exception_index == EXCP_HW_BREAK) { env->regs[16] = env->sregs[SR_PC]; env->sregs[SR_MSR] |= MSR_BIP; env->sregs[SR_PC] = cpu->base_vectors + 0x18; @@ -262,7 +260,7 @@ void mb_cpu_do_interrupt(CPUState *cs) break; default: cpu_abort(env, "unhandled exception type=%d\n", - env->exception_index); + cs->exception_index); break; } } diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index b70b2ea99c..318185a5df 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -95,7 +95,9 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl) void helper_raise_exception(CPUMBState *env, uint32_t index) { - env->exception_index = index; + CPUState *cs = CPU(mb_env_get_cpu(env)); + + cs->exception_index = index; cpu_loop_exit(env); } diff --git a/target-mips/helper.c b/target-mips/helper.c index d8e9166c2c..698c3d1adb 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -204,6 +204,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) { + CPUState *cs = CPU(mips_env_get_cpu(env)); int exception = 0, error_code = 0; switch (tlb_error) { @@ -249,7 +250,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); #endif - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; } @@ -404,27 +405,29 @@ static void set_hflags_for_handler (CPUMIPSState *env) void mips_cpu_do_interrupt(CPUState *cs) { +#if !defined(CONFIG_USER_ONLY) MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) target_ulong offset; int cause = -1; const char *name; - if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { - if (env->exception_index < 0 || env->exception_index > EXCP_LAST) + if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) { + if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) { name = "unknown"; - else - name = excp_names[env->exception_index]; + } else { + name = excp_names[cs->exception_index]; + } qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", __func__, env->active_tc.PC, env->CP0_EPC, name); } - if (env->exception_index == EXCP_EXT_INTERRUPT && - (env->hflags & MIPS_HFLAG_DM)) - env->exception_index = EXCP_DINT; + if (cs->exception_index == EXCP_EXT_INTERRUPT && + (env->hflags & MIPS_HFLAG_DM)) { + cs->exception_index = EXCP_DINT; + } offset = 0x180; - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_DSS: env->CP0_Debug |= 1 << CP0DB_DSS; /* Debug single step cannot be raised inside a delay slot and @@ -632,11 +635,11 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); break; default: - qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index); - printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); + qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index); + printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index); exit(1); } - if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { + if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) { qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", __func__, env->active_tc.PC, env->CP0_EPC, cause, @@ -644,7 +647,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_DEPC); } #endif - env->exception_index = EXCP_NONE; + cs->exception_index = EXCP_NONE; } #if !defined(CONFIG_USER_ONLY) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index a62496cc3b..5a4a656f3d 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -38,10 +38,12 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, int error_code, uintptr_t pc) { + CPUState *cs = CPU(mips_env_get_cpu(env)); + if (exception < EXCP_SC) { qemu_log("%s: %d %d\n", __func__, exception, error_code); } - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; if (pc) { @@ -2147,11 +2149,12 @@ void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { MIPSCPU *cpu = mips_env_get_cpu(env); + CPUState *cs = CPU(cpu); int ret; - ret = mips_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx); + ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); if (ret) { - do_raise_exception_err(env, env->exception_index, + do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); } } diff --git a/target-mips/translate.c b/target-mips/translate.c index 083f6ab283..d1c25d2b22 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15929,10 +15929,8 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) void cpu_state_reset(CPUMIPSState *env) { -#ifndef CONFIG_USER_ONLY MIPSCPU *cpu = mips_env_get_cpu(env); CPUState *cs = CPU(cpu); -#endif /* Reset registers to their default values */ env->CP0_PRid = env->cpu_model->CP0_PRid; @@ -16063,7 +16061,7 @@ void cpu_state_reset(CPUMIPSState *env) } #endif compute_hflags(env); - env->exception_index = EXCP_NONE; + cs->exception_index = EXCP_NONE; } void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos) diff --git a/target-moxie/helper.c b/target-moxie/helper.c index 8160475414..3b14f3735e 100644 --- a/target-moxie/helper.c +++ b/target-moxie/helper.c @@ -63,7 +63,9 @@ void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx, void helper_raise_exception(CPUMoxieState *env, int ex) { - env->exception_index = ex; + CPUState *cs = CPU(moxie_env_get_cpu(env)); + + cs->exception_index = ex; /* Stash the exception type. */ env->sregs[2] = ex; /* Stash the address where the exception occurred. */ @@ -98,7 +100,9 @@ uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b) void helper_debug(CPUMoxieState *env) { - env->exception_index = EXCP_DEBUG; + CPUState *cs = CPU(moxie_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } @@ -106,7 +110,9 @@ void helper_debug(CPUMoxieState *env) void moxie_cpu_do_interrupt(CPUState *cs) { - env->exception_index = -1; + CPUState *cs = CPU(moxie_env_get_cpu(env)); + + cs->exception_index = -1; } int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, @@ -114,7 +120,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, { MoxieCPU *cpu = MOXIE_CPU(cs); - cpu->env.exception_index = 0xaa; + cs->exception_index = 0xaa; cpu->env.debug1 = address; cpu_dump_state(cs, stderr, fprintf, 0); return 1; @@ -138,7 +144,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, if (miss) { /* handle the miss. */ phy = 0; - env->exception_index = MOXIE_EX_MMU_MISS; + cs->exception_index = MOXIE_EX_MMU_MISS; } else { phy = res.phy; r = 0; @@ -150,10 +156,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, void moxie_cpu_do_interrupt(CPUState *cs) { - MoxieCPU *cpu = MOXIE_CPU(cs); - CPUMoxieState *env = &cpu->env; - - switch (env->exception_index) { + switch (cs->exception_index) { case MOXIE_EX_BREAK: break; default: diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 99e4aa7c67..b601de009c 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -48,7 +48,7 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.pc = 0x100; cpu->env.sr = SR_FO | SR_SM; - cpu->env.exception_index = -1; + s->exception_index = -1; cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c index 58e53c6c98..b96f3f8963 100644 --- a/target-openrisc/exception.c +++ b/target-openrisc/exception.c @@ -22,6 +22,8 @@ void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp) { - cpu->env.exception_index = excp; + CPUState *cs = CPU(cpu); + + cs->exception_index = excp; cpu_loop_exit(&cpu->env); } diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 2153e7ea7e..087e2f1351 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -27,9 +27,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs) { +#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; -#ifndef CONFIG_USER_ONLY env->epcr = env->pc; if (env->flags & D_FLAG) { @@ -37,7 +37,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr |= SR_DSX; env->epcr -= 4; } - if (env->exception_index == EXCP_SYSCALL) { + if (cs->exception_index == EXCP_SYSCALL) { env->epcr += 4; } @@ -54,12 +54,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; - if (env->exception_index > 0 && env->exception_index < EXCP_NR) { - env->pc = (env->exception_index << 8); + if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { + env->pc = (cs->exception_index << 8); } else { - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); } #endif - env->exception_index = -1; + cs->exception_index = -1; } diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c index 1fd0a0a3fa..4222219acd 100644 --- a/target-openrisc/mmu.c +++ b/target-openrisc/mmu.c @@ -139,6 +139,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, int rw, int tlb_error) { + CPUState *cs = CPU(cpu); int exception = 0; switch (tlb_error) { @@ -169,7 +170,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, #endif } - cpu->env.exception_index = exception; + cs->exception_index = exception; cpu->env.eear = address; } diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index d541929743..a58655b5c7 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -43,13 +43,15 @@ void ppc_cpu_do_interrupt(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - env->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; } void ppc_hw_interrupt(CPUPPCState *env) { - env->exception_index = POWERPC_EXCP_NONE; + CPUState *cs = CPU(ppc_env_get_cpu(env)); + + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; } #else /* defined(CONFIG_USER_ONLY) */ @@ -68,8 +70,8 @@ static inline void dump_syscall(CPUPPCState *env) */ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) { + CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; - CPUState *cs; target_ulong msr, new_msr, vector; int srr0, srr1, asrr0, asrr1; int lpes0, lpes1, lev; @@ -135,7 +137,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) fprintf(stderr, "Machine check while not allowed. " "Entering checkstop state\n"); } - cs = CPU(cpu); cs->halted = 1; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } @@ -204,7 +205,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_FP: if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { LOG_EXCP("Ignore floating point exception\n"); - env->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; return; } @@ -662,7 +663,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) hreg_compute_hflags(env); env->nip = vector; /* Reset exception state */ - env->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; if ((env->mmu_model == POWERPC_MMU_BOOKE) || @@ -679,7 +680,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - powerpc_excp(cpu, env->excp_model, env->exception_index); + powerpc_excp(cpu, env->excp_model, cs->exception_index); } void ppc_hw_interrupt(CPUPPCState *env) @@ -815,10 +816,12 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr) void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, uint32_t error_code) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + #if 0 printf("Raise exception %3x code : %d\n", exception, error_code); #endif - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; cpu_loop_exit(env); } diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index e7f329566d..fd91239d37 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -119,6 +119,7 @@ uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf) static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); uint64_t ret = 0; int ve; @@ -155,7 +156,7 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op, } /* We must update the target FPR before raising the exception */ if (ve != 0) { - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; @@ -224,6 +225,8 @@ static inline void float_zero_divide_excp(CPUPPCState *env) static inline void float_overflow_excp(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + env->fpscr |= 1 << FPSCR_OX; /* Update the floating-point exception summary */ env->fpscr |= 1 << FPSCR_FX; @@ -232,7 +235,7 @@ static inline void float_overflow_excp(CPUPPCState *env) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We must update the target FPR before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; } else { env->fpscr |= 1 << FPSCR_XX; @@ -242,6 +245,8 @@ static inline void float_overflow_excp(CPUPPCState *env) static inline void float_underflow_excp(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + env->fpscr |= 1 << FPSCR_UX; /* Update the floating-point exception summary */ env->fpscr |= 1 << FPSCR_FX; @@ -250,13 +255,15 @@ static inline void float_underflow_excp(CPUPPCState *env) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We must update the target FPR before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX; } } static inline void float_inexact_excp(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); + env->fpscr |= 1 << FPSCR_XX; /* Update the floating-point exception summary */ env->fpscr |= 1 << FPSCR_FX; @@ -264,7 +271,7 @@ static inline void float_inexact_excp(CPUPPCState *env) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We must update the target FPR before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; } } @@ -316,6 +323,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); int prev; prev = (env->fpscr >> bit) & 1; @@ -439,7 +447,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; /* We have to update Rc1 before raising the exception */ - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; break; } } @@ -447,6 +455,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); target_ulong prev, new; int i; @@ -468,7 +477,7 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) } if ((fpscr_ex & fpscr_eex) != 0) { env->fpscr |= 1 << FPSCR_FEX; - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; /* XXX: we should compute it properly */ env->error_code = POWERPC_EXCP_FP; } else { @@ -484,6 +493,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) void helper_float_check_status(CPUPPCState *env) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); int status = get_float_exception_flags(&env->fp_status); if (status & float_flag_divbyzero) { @@ -496,11 +506,11 @@ void helper_float_check_status(CPUPPCState *env) float_inexact_excp(env); } - if (env->exception_index == POWERPC_EXCP_PROGRAM && + if (cs->exception_index == POWERPC_EXCP_PROGRAM && (env->error_code & POWERPC_EXCP_FP)) { /* Differred floating-point exception after target FPR update */ if (msr_fe0 != 0 || msr_fe1 != 0) { - helper_raise_exception_err(env, env->exception_index, + helper_raise_exception_err(env, cs->exception_index, env->error_code); } } diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 32e7a8c0a7..81ec959b23 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -1178,7 +1178,7 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu) if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } return 0; diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 6a77dc4f97..aa87084238 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -222,6 +222,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, target_ulong eaddr, int rwx, hwaddr *raddr, int *prot) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS)); LOG_MMU("direct store...\n"); @@ -238,7 +239,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, if (rwx == 2) { /* No code fetch is allowed in direct-store areas */ - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; } @@ -249,7 +250,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, break; case ACCESS_FLOAT: /* Floating point load/store */ - env->exception_index = POWERPC_EXCP_ALIGN; + cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] = eaddr; return 1; @@ -272,7 +273,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, return 0; case ACCESS_EXT: /* eciwx or ecowx */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -290,7 +291,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, *raddr = eaddr; return 0; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -383,6 +384,7 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte, int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, int mmu_idx) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); target_ulong sr; hwaddr pte_offset; ppc_hash_pte32_t pte; @@ -409,10 +411,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, if (raddr != -1) { if (need_prot[rwx] & ~prot) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -449,7 +451,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, /* 5. Check for segment level no-execute violation */ if ((rwx == 2) && (sr & SR32_NX)) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; } @@ -458,10 +460,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte); if (pte_offset == -1) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x40000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -483,10 +485,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, /* Access right violation */ LOG_MMU("PTE access rejected\n"); if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 438d0b732f..7186c0dbb4 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -457,6 +457,7 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte, int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx, int mmu_idx) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); ppc_slb_t *slb; hwaddr pte_offset; ppc_hash_pte64_t pte; @@ -483,10 +484,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, if (!slb) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISEG; + cs->exception_index = POWERPC_EXCP_ISEG; env->error_code = 0; } else { - env->exception_index = POWERPC_EXCP_DSEG; + cs->exception_index = POWERPC_EXCP_DSEG; env->error_code = 0; env->spr[SPR_DAR] = eaddr; } @@ -495,7 +496,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, /* 3. Check for segment level no-execute violation */ if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; return 1; } @@ -504,10 +505,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte); if (pte_offset == -1) { if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x40000000; } else { - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (rwx == 1) { @@ -530,12 +531,12 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, /* Access right violation */ LOG_MMU("PTE access rejected\n"); if (rwx == 2) { - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; } else { target_ulong dsisr = 0; - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = eaddr; if (need_prot[rwx] & ~pp_prot) { diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 8e2f8e736a..b6abd974e3 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1491,6 +1491,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address, static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx) { + CPUState *cs = CPU(ppc_env_get_cpu(env)); mmu_ctx_t ctx; int access_type; int ret = 0; @@ -1510,24 +1511,24 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, mmu_idx, TARGET_PAGE_SIZE); ret = 0; } else if (ret < 0) { - LOG_MMU_STATE(CPU(ppc_env_get_cpu(env))); + LOG_MMU_STATE(cs); if (access_type == ACCESS_CODE) { switch (ret) { case -1: /* No matches in page tables or TLB */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - env->exception_index = POWERPC_EXCP_IFTLB; + cs->exception_index = POWERPC_EXCP_IFTLB; env->error_code = 1 << 18; env->spr[SPR_IMISS] = address; env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; goto tlb_miss; case POWERPC_MMU_SOFT_74xx: - env->exception_index = POWERPC_EXCP_IFTLB; + cs->exception_index = POWERPC_EXCP_IFTLB; goto tlb_miss_74xx; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: - env->exception_index = POWERPC_EXCP_ITLB; + cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = address; env->spr[SPR_40x_ESR] = 0x00000000; @@ -1536,7 +1537,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, booke206_update_mas_tlb_miss(env, address, rw); /* fall through */ case POWERPC_MMU_BOOKE: - env->exception_index = POWERPC_EXCP_ITLB; + cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_BOOKE_DEAR] = address; return -1; @@ -1555,7 +1556,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case -2: /* Access rights violation */ - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; break; case -3: @@ -1564,13 +1565,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, (env->mmu_model == POWERPC_MMU_BOOKE206)) { env->spr[SPR_BOOKE_ESR] = 0x00000000; } - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; break; case -4: /* Direct store exception */ /* No code fetch is allowed in direct-store areas */ - env->exception_index = POWERPC_EXCP_ISI; + cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x10000000; break; } @@ -1581,10 +1582,10 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: if (rw == 1) { - env->exception_index = POWERPC_EXCP_DSTLB; + cs->exception_index = POWERPC_EXCP_DSTLB; env->error_code = 1 << 16; } else { - env->exception_index = POWERPC_EXCP_DLTLB; + cs->exception_index = POWERPC_EXCP_DLTLB; env->error_code = 0; } env->spr[SPR_DMISS] = address; @@ -1598,9 +1599,9 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case POWERPC_MMU_SOFT_74xx: if (rw == 1) { - env->exception_index = POWERPC_EXCP_DSTLB; + cs->exception_index = POWERPC_EXCP_DSTLB; } else { - env->exception_index = POWERPC_EXCP_DLTLB; + cs->exception_index = POWERPC_EXCP_DLTLB; } tlb_miss_74xx: /* Implement LRU algorithm */ @@ -1611,7 +1612,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: - env->exception_index = POWERPC_EXCP_DTLB; + cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = address; if (rw) { @@ -1628,7 +1629,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, booke206_update_mas_tlb_miss(env, address, rw); /* fall through */ case POWERPC_MMU_BOOKE: - env->exception_index = POWERPC_EXCP_DTLB; + cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_BOOKE_DEAR] = address; env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0; @@ -1644,7 +1645,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case -2: /* Access rights violation */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; if (env->mmu_model == POWERPC_MMU_SOFT_4xx || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) { @@ -1670,13 +1671,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, switch (access_type) { case ACCESS_FLOAT: /* Floating point load/store */ - env->exception_index = POWERPC_EXCP_ALIGN; + cs->exception_index = POWERPC_EXCP_ALIGN; env->error_code = POWERPC_EXCP_ALIGN_FP; env->spr[SPR_DAR] = address; break; case ACCESS_RES: /* lwarx, ldarx or stwcx. */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) { @@ -1687,7 +1688,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case ACCESS_EXT: /* eciwx or ecowx */ - env->exception_index = POWERPC_EXCP_DSI; + cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; env->spr[SPR_DAR] = address; if (rw == 1) { @@ -1698,7 +1699,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; default: printf("DSI: invalid exception (%d)\n", ret); - env->exception_index = POWERPC_EXCP_PROGRAM; + cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; env->spr[SPR_DAR] = address; @@ -1709,7 +1710,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, } #if 0 printf("%s: set exception to %d %02x\n", __func__, - env->exception, env->error_code); + cs->exception, env->error_code); #endif ret = 1; } @@ -2909,6 +2910,6 @@ void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, /* now we have a real cpu fault */ cpu_restore_state(env, retaddr); } - helper_raise_exception_err(env, env->exception_index, env->error_code); + helper_raise_exception_err(env, cpu->exception_index, env->error_code); } } diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 703b3d8797..e22d82f604 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8422,7 +8422,7 @@ static void ppc_cpu_reset(CPUState *s) env->reserve_addr = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ env->pending_interrupts = 0; - env->exception_index = POWERPC_EXCP_NONE; + s->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) diff --git a/target-ppc/user_only_helper.c b/target-ppc/user_only_helper.c index a7c99e032b..829f66f504 100644 --- a/target-ppc/user_only_helper.c +++ b/target-ppc/user_only_helper.c @@ -39,7 +39,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, env->spr[SPR_DAR] = address; env->spr[SPR_DSISR] = error_code; } - env->exception_index = exception; + cs->exception_index = exception; env->error_code = error_code; return 1; diff --git a/target-s390x/helper.c b/target-s390x/helper.c index e71e5fd563..6262f42762 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -85,10 +85,7 @@ S390CPU *cpu_s390x_init(const char *cpu_model) void s390_cpu_do_interrupt(CPUState *cs) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, @@ -96,7 +93,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, { S390CPU *cpu = S390_CPU(cs); - cpu->env.exception_index = EXCP_PGM; + cs->exception_index = EXCP_PGM; cpu->env.int_pgm_code = PGM_ADDRESSING; /* On real machines this value is dropped into LowMem. Since this is userland, simply put this someplace that cpu_loop can find it. */ @@ -110,7 +107,9 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address, static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen) { - env->exception_index = EXCP_PGM; + CPUState *cs = CPU(s390_env_get_cpu(env)); + + cs->exception_index = EXCP_PGM; env->int_pgm_code = code; env->int_pgm_ilen = ilen; } @@ -429,7 +428,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) CPUS390XState *env = &cpu->env; target_ulong raddr; int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - int old_exc = env->exception_index; + int old_exc = cs->exception_index; uint64_t asc = env->psw.mask & PSW_MASK_ASC; /* 31-Bit mode */ @@ -438,7 +437,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) } mmu_translate(env, vaddr, 2, asc, &raddr, &prot); - env->exception_index = old_exc; + cs->exception_index = old_exc; return raddr; } @@ -456,7 +455,7 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) } } cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; } env->psw.addr = addr; @@ -753,43 +752,43 @@ void s390_cpu_do_interrupt(CPUState *cs) CPUS390XState *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n", - __func__, env->exception_index, env->psw.addr); + __func__, cs->exception_index, env->psw.addr); s390_add_running_cpu(cpu); /* handle machine checks */ if ((env->psw.mask & PSW_MASK_MCHECK) && - (env->exception_index == -1)) { + (cs->exception_index == -1)) { if (env->pending_int & INTERRUPT_MCHK) { - env->exception_index = EXCP_MCHK; + cs->exception_index = EXCP_MCHK; } } /* handle external interrupts */ if ((env->psw.mask & PSW_MASK_EXT) && - env->exception_index == -1) { + cs->exception_index == -1) { if (env->pending_int & INTERRUPT_EXT) { /* code is already in env */ - env->exception_index = EXCP_EXT; + cs->exception_index = EXCP_EXT; } else if (env->pending_int & INTERRUPT_TOD) { cpu_inject_ext(cpu, 0x1004, 0, 0); - env->exception_index = EXCP_EXT; + cs->exception_index = EXCP_EXT; env->pending_int &= ~INTERRUPT_EXT; env->pending_int &= ~INTERRUPT_TOD; } else if (env->pending_int & INTERRUPT_CPUTIMER) { cpu_inject_ext(cpu, 0x1005, 0, 0); - env->exception_index = EXCP_EXT; + cs->exception_index = EXCP_EXT; env->pending_int &= ~INTERRUPT_EXT; env->pending_int &= ~INTERRUPT_TOD; } } /* handle I/O interrupts */ if ((env->psw.mask & PSW_MASK_IO) && - (env->exception_index == -1)) { + (cs->exception_index == -1)) { if (env->pending_int & INTERRUPT_IO) { - env->exception_index = EXCP_IO; + cs->exception_index = EXCP_IO; } } - switch (env->exception_index) { + switch (cs->exception_index) { case EXCP_PGM: do_program_interrupt(env); break; @@ -806,7 +805,7 @@ void s390_cpu_do_interrupt(CPUState *cs) do_mchk_interrupt(env); break; } - env->exception_index = -1; + cs->exception_index = -1; if (!env->pending_int) { cs->interrupt_request &= ~CPU_INTERRUPT_HARD; diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index d9dc8ae3df..411c32692a 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -1052,8 +1052,9 @@ void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint64_t v1) /* load real address */ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) { + CPUState *cs = CPU(s390_env_get_cpu(env)); uint32_t cc = 0; - int old_exc = env->exception_index; + int old_exc = cs->exception_index; uint64_t asc = env->psw.mask & PSW_MASK_ASC; uint64_t ret; int flags; @@ -1063,16 +1064,16 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) program_interrupt(env, PGM_SPECIAL_OP, 2); } - env->exception_index = old_exc; + cs->exception_index = old_exc; if (mmu_translate(env, addr, 0, asc, &ret, &flags)) { cc = 3; } - if (env->exception_index == EXCP_PGM) { + if (cs->exception_index == EXCP_PGM) { ret = env->int_pgm_code | 0x80000000; } else { ret |= addr & ~TARGET_PAGE_MASK; } - env->exception_index = old_exc; + cs->exception_index = old_exc; env->cc_op = cc; return ret; diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c index 728456f295..69da9e56a9 100644 --- a/target-s390x/misc_helper.c +++ b/target-s390x/misc_helper.c @@ -47,9 +47,10 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, uintptr_t retaddr) { + CPUState *cs = CPU(s390_env_get_cpu(env)); int t; - env->exception_index = EXCP_PGM; + cs->exception_index = EXCP_PGM; env->int_pgm_code = excp; /* Use the (ultimate) callers address to find the insn that trapped. */ @@ -66,8 +67,10 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp, /* Raise an exception statically from a TB. */ void HELPER(exception)(CPUS390XState *env, uint32_t excp) { + CPUState *cs = CPU(s390_env_get_cpu(env)); + HELPER_LOG("%s: exception %d\n", __func__, excp); - env->exception_index = excp; + cs->exception_index = excp; cpu_loop_exit(env); } @@ -75,17 +78,21 @@ void HELPER(exception)(CPUS390XState *env, uint32_t excp) void program_interrupt(CPUS390XState *env, uint32_t code, int ilen) { + S390CPU *cpu = s390_env_get_cpu(env); + qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n", env->psw.addr); if (kvm_enabled()) { #ifdef CONFIG_KVM - kvm_s390_interrupt(s390_env_get_cpu(env), KVM_S390_PROGRAM_INT, code); + kvm_s390_interrupt(cpu, KVM_S390_PROGRAM_INT, code); #endif } else { + CPUState *cs = CPU(cpu); + env->int_pgm_code = code; env->int_pgm_ilen = ilen; - env->exception_index = EXCP_PGM; + cs->exception_index = EXCP_PGM; cpu_loop_exit(env); } } diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 3f8f1fa296..0357cebb81 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -33,10 +33,7 @@ void superh_cpu_do_interrupt(CPUState *cs) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - - env->exception_index = -1; + cs->exception_index = -1; } int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, @@ -46,16 +43,16 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, CPUSH4State *env = &cpu->env; env->tea = address; - env->exception_index = -1; + cs->exception_index = -1; switch (rw) { case 0: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; case 1: - env->exception_index = 0x0c0; + cs->exception_index = 0x0c0; break; case 2: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; } return 1; @@ -89,16 +86,16 @@ void superh_cpu_do_interrupt(CPUState *cs) SuperHCPU *cpu = SUPERH_CPU(cs); CPUSH4State *env = &cpu->env; int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD; - int do_exp, irq_vector = env->exception_index; + int do_exp, irq_vector = cs->exception_index; /* prioritize exceptions over interrupts */ - do_exp = env->exception_index != -1; - do_irq = do_irq && (env->exception_index == -1); + do_exp = cs->exception_index != -1; + do_irq = do_irq && (cs->exception_index == -1); if (env->sr & SR_BL) { - if (do_exp && env->exception_index != 0x1e0) { - env->exception_index = 0x000; /* masked exception -> reset */ + if (do_exp && cs->exception_index != 0x1e0) { + cs->exception_index = 0x000; /* masked exception -> reset */ } if (do_irq && !env->in_sleep) { return; /* masked */ @@ -116,7 +113,7 @@ void superh_cpu_do_interrupt(CPUState *cs) if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *expname; - switch (env->exception_index) { + switch (cs->exception_index) { case 0x0e0: expname = "addr_error"; break; @@ -180,8 +177,8 @@ void superh_cpu_do_interrupt(CPUState *cs) env->flags = 0; if (do_exp) { - env->expevt = env->exception_index; - switch (env->exception_index) { + env->expevt = cs->exception_index; + switch (cs->exception_index) { case 0x000: case 0x020: case 0x140: @@ -472,33 +469,33 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, switch (ret) { case MMU_ITLB_MISS: case MMU_DTLB_MISS_READ: - env->exception_index = 0x040; + cs->exception_index = 0x040; break; case MMU_DTLB_MULTIPLE: case MMU_ITLB_MULTIPLE: - env->exception_index = 0x140; + cs->exception_index = 0x140; break; case MMU_ITLB_VIOLATION: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; case MMU_DTLB_MISS_WRITE: - env->exception_index = 0x060; + cs->exception_index = 0x060; break; case MMU_DTLB_INITIAL_WRITE: - env->exception_index = 0x080; + cs->exception_index = 0x080; break; case MMU_DTLB_VIOLATION_READ: - env->exception_index = 0x0a0; + cs->exception_index = 0x0a0; break; case MMU_DTLB_VIOLATION_WRITE: - env->exception_index = 0x0c0; + cs->exception_index = 0x0c0; break; case MMU_IADDR_ERROR: case MMU_DADDR_ERROR_READ: - env->exception_index = 0x0e0; + cs->exception_index = 0x0e0; break; case MMU_DADDR_ERROR_WRITE: - env->exception_index = 0x100; + cs->exception_index = 0x100; break; default: cpu_abort(env, "Unhandled MMU fault"); @@ -702,8 +699,10 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, if (entry->vpn == vpn && (!use_asid || entry->asid == asid || entry->sh)) { if (utlb_match_entry) { + CPUState *cs = CPU(sh_env_get_cpu(s)); + /* Multiple TLB Exception */ - s->exception_index = 0x140; + cs->exception_index = 0x140; s->tea = addr; break; } diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 35f906788a..03633f0ee8 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -69,7 +69,9 @@ void helper_ldtlb(CPUSH4State *env) static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, uintptr_t retaddr) { - env->exception_index = index; + CPUState *cs = CPU(sh_env_get_cpu(env)); + + cs->exception_index = index; if (retaddr) { cpu_restore_state(env, retaddr); } diff --git a/target-sparc/helper.c b/target-sparc/helper.c index 57c20af478..a393ef0a48 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -24,13 +24,17 @@ void helper_raise_exception(CPUSPARCState *env, int tt) { - env->exception_index = tt; + CPUState *cs = CPU(sparc_env_get_cpu(env)); + + cs->exception_index = tt; cpu_loop_exit(env); } void helper_debug(CPUSPARCState *env) { - env->exception_index = EXCP_DEBUG; + CPUState *cs = CPU(sparc_env_get_cpu(env)); + + cs->exception_index = EXCP_DEBUG; cpu_loop_exit(env); } @@ -232,7 +236,7 @@ void helper_power_down(CPUSPARCState *env) CPUState *cs = CPU(sparc_env_get_cpu(env)); cs->halted = 1; - env->exception_index = EXCP_HLT; + cs->exception_index = EXCP_HLT; env->pc = env->npc; env->npc = env->pc + 4; cpu_loop_exit(env); diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c index d5322380cd..f350a903e0 100644 --- a/target-sparc/int32_helper.c +++ b/target-sparc/int32_helper.c @@ -62,7 +62,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - int cwp, intno = env->exception_index; + int cwp, intno = cs->exception_index; /* Compute PSR before exposing state. */ if (env->cc_op != CC_OP_FLAGS) { @@ -105,12 +105,12 @@ void sparc_cpu_do_interrupt(CPUState *cs) #endif #if !defined(CONFIG_USER_ONLY) if (env->psret == 0) { - if (env->exception_index == 0x80 && + if (cs->exception_index == 0x80 && env->def->features & CPU_FEATURE_TA0_SHUTDOWN) { qemu_system_shutdown_request(); } else { cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", - env->exception_index); + cs->exception_index); } return; } @@ -125,7 +125,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); env->pc = env->tbr; env->npc = env->pc + 4; - env->exception_index = -1; + cs->exception_index = -1; #if !defined(CONFIG_USER_ONLY) /* IRQ acknowledgment */ diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c index bf7dd86ab8..1744245f70 100644 --- a/target-sparc/int64_helper.c +++ b/target-sparc/int64_helper.c @@ -63,7 +63,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - int intno = env->exception_index; + int intno = cs->exception_index; trap_state *tsptr; /* Compute PSR before exposing state. */ @@ -112,7 +112,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) #if !defined(CONFIG_USER_ONLY) if (env->tl >= env->maxtl) { cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," - " Error state", env->exception_index, env->tl, env->maxtl); + " Error state", cs->exception_index, env->tl, env->maxtl); return; } #endif @@ -160,7 +160,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); env->pc = env->tbr; env->npc = env->pc + 4; - env->exception_index = -1; + cs->exception_index = -1; } trap_state *cpu_tsptr(CPUSPARCState* env) diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index c2482454ac..e1475d0b0f 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -1325,7 +1325,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, dump_asi("read ", last_addr, asi, size, ret); #endif /* env->exception_index is set in get_physical_address_data(). */ - helper_raise_exception(env, env->exception_index); + helper_raise_exception(env, cs->exception_index); } /* convert nonfaulting load ASIs to normal load ASIs */ diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 5a9748e347..1571c6a026 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -28,12 +28,10 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) { - SPARCCPU *cpu = SPARC_CPU(cs); - if (rw & 2) { - cpu->env.exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; } else { - cpu->env.exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } return 1; } @@ -239,9 +237,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, return 0; } else { if (rw & 2) { - env->exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; } else { - env->exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } return 1; } @@ -491,6 +489,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int mmu_idx) { + CPUState *cs = CPU(sparc_env_get_cpu(env)); unsigned int i; uint64_t context; uint64_t sfsr = 0; @@ -555,10 +554,10 @@ static int get_physical_address_data(CPUSPARCState *env, if (do_fault) { /* faults above are reported with TT_DFAULT. */ - env->exception_index = TT_DFAULT; + cs->exception_index = TT_DFAULT; } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { do_fault = 1; - env->exception_index = TT_DPROT; + cs->exception_index = TT_DPROT; trace_mmu_helper_dprot(address, context, mmu_idx, env->tl); } @@ -602,7 +601,7 @@ static int get_physical_address_data(CPUSPARCState *env, * - JPS1: SFAR updated and some fields of SFSR updated */ env->dmmu.tag_access = (address & ~0x1fffULL) | context; - env->exception_index = TT_DMISS; + cs->exception_index = TT_DMISS; return 1; } @@ -610,6 +609,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int mmu_idx) { + CPUState *cs = CPU(sparc_env_get_cpu(env)); unsigned int i; uint64_t context; @@ -653,7 +653,7 @@ static int get_physical_address_code(CPUSPARCState *env, /* FIXME: ASI field in SFSR must be set */ env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT; - env->exception_index = TT_TFAULT; + cs->exception_index = TT_TFAULT; env->immu.tag_access = (address & ~0x1fffULL) | context; @@ -671,7 +671,7 @@ static int get_physical_address_code(CPUSPARCState *env, /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */ env->immu.tag_access = (address & ~0x1fffULL) | context; - env->exception_index = TT_TMISS; + cs->exception_index = TT_TMISS; return 1; } diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index 5cd2378c6d..cd2cbef34f 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -16,7 +16,9 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t excp) { - env->exception_index = excp; + CPUState *cs = CPU(uc32_env_get_cpu(env)); + + cs->exception_index = excp; cpu_loop_exit(env); } diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c index 75f73865f1..a55355ebe8 100644 --- a/target-unicore32/softmmu.c +++ b/target-unicore32/softmmu.c @@ -79,7 +79,7 @@ void uc32_cpu_do_interrupt(CPUState *cs) uint32_t addr; int new_mode; - switch (env->exception_index) { + switch (cs->exception_index) { case UC32_EXCP_PRIV: new_mode = ASR_MODE_PRIV; addr = 0x08; @@ -99,7 +99,7 @@ void uc32_cpu_do_interrupt(CPUState *cs) addr = 0x18; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); return; } /* High vectors. */ @@ -257,9 +257,9 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, env->cp0.c3_faultstatus = ret; env->cp0.c4_faultaddr = address; if (access_type == 2) { - env->exception_index = UC32_EXCP_ITRAP; + cs->exception_index = UC32_EXCP_ITRAP; } else { - env->exception_index = UC32_EXCP_DTRAP; + cs->exception_index = UC32_EXCP_DTRAP; } return ret; } diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 3cb0bbd972..259878837f 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -169,6 +169,8 @@ static void handle_interrupt(CPUXtensaState *env) (env->config->level_mask[level] & env->sregs[INTSET] & env->sregs[INTENABLE])) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + if (level > 1) { env->sregs[EPC1 + level - 1] = env->pc; env->sregs[EPS2 + level - 2] = env->sregs[PS]; @@ -185,10 +187,10 @@ static void handle_interrupt(CPUXtensaState *env) } else { env->sregs[EPC1] = env->pc; } - env->exception_index = EXC_DOUBLE; + cs->exception_index = EXC_DOUBLE; } else { env->sregs[EPC1] = env->pc; - env->exception_index = + cs->exception_index = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; } env->sregs[PS] |= PS_EXCM; @@ -202,7 +204,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs) XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; - if (env->exception_index == EXC_IRQ) { + if (cs->exception_index == EXC_IRQ) { qemu_log_mask(CPU_LOG_INT, "%s(EXC_IRQ) level = %d, cintlevel = %d, " "pc = %08x, a0 = %08x, ps = %08x, " @@ -215,7 +217,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs) handle_interrupt(env); } - switch (env->exception_index) { + switch (cs->exception_index) { case EXC_WINDOW_OVERFLOW4: case EXC_WINDOW_UNDERFLOW4: case EXC_WINDOW_OVERFLOW8: @@ -228,15 +230,15 @@ void xtensa_cpu_do_interrupt(CPUState *cs) case EXC_DEBUG: qemu_log_mask(CPU_LOG_INT, "%s(%d) " "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n", - __func__, env->exception_index, + __func__, cs->exception_index, env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]); - if (env->config->exception_vector[env->exception_index]) { + if (env->config->exception_vector[cs->exception_index]) { env->pc = relocated_vector(env, - env->config->exception_vector[env->exception_index]); + env->config->exception_vector[cs->exception_index]); env->exception_taken = 1; } else { qemu_log("%s(pc = %08x) bad exception_index: %d\n", - __func__, env->pc, env->exception_index); + __func__, env->pc, cs->exception_index); } break; @@ -245,7 +247,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs) default: qemu_log("%s(pc = %08x) unknown exception_index: %d\n", - __func__, env->pc, env->exception_index); + __func__, env->pc, cs->exception_index); break; } check_interrupts(env); diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 509ba49d60..a314ed0b9d 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -97,7 +97,9 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) void HELPER(exception)(CPUXtensaState *env, uint32_t excp) { - env->exception_index = excp; + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + cs->exception_index = excp; if (excp == EXCP_DEBUG) { env->exception_taken = 0; } diff --git a/user-exec.c b/user-exec.c index dec636eb1e..dbb9c8d0a7 100644 --- a/user-exec.c +++ b/user-exec.c @@ -41,7 +41,9 @@ static void exception_action(CPUArchState *env1) { #if defined(TARGET_I386) - raise_exception_err(env1, env1->exception_index, env1->error_code); + CPUState *cpu = ENV_GET_CPU(env1); + + raise_exception_err(env1, cpu->exception_index, env1->error_code); #else cpu_loop_exit(env1); #endif @@ -71,7 +73,7 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc) sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL); #endif } - env1->exception_index = -1; + cpu->exception_index = -1; siglongjmp(cpu->jmp_env, 1); } -- cgit v1.2.3-55-g7522 From 0429a9719551a4aa794051aeb8c7b42658902c27 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 18:14:44 +0200 Subject: cpu: Move opaque field from CPU_COMMON to CPUState Signed-off-by: Andreas Färber --- bsd-user/main.c | 2 +- gdbstub.c | 3 +-- include/exec/cpu-defs.h | 3 --- include/qom/cpu.h | 3 +++ linux-user/elfload.c | 10 ++++++---- linux-user/linuxload.c | 3 +-- linux-user/m68k/target_cpu.h | 4 +++- linux-user/main.c | 6 +++--- linux-user/signal.c | 17 +++++++++++------ linux-user/syscall.c | 30 ++++++++++++++++++------------ linux-user/vm86.c | 27 ++++++++++++++++++--------- target-arm/arm-semi.c | 9 +++++---- target-m68k/m68k-semi.c | 3 ++- 13 files changed, 72 insertions(+), 48 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/bsd-user/main.c b/bsd-user/main.c index f9246aa102..f81ba55af8 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -1000,7 +1000,7 @@ int main(int argc, char **argv) memset(ts, 0, sizeof(TaskState)); init_task_state(ts); ts->info = info; - env->opaque = ts; + cpu->opaque = ts; #if defined(TARGET_I386) cpu_x86_set_cpl(env, 3); diff --git a/gdbstub.c b/gdbstub.c index e8ab0b2992..c5ab73fb1d 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1086,8 +1086,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) } #ifdef CONFIG_USER_ONLY else if (strncmp(p, "Offsets", 7) == 0) { - CPUArchState *env = s->c_cpu->env_ptr; - TaskState *ts = env->opaque; + TaskState *ts = s->c_cpu->opaque; snprintf(buf, sizeof(buf), "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bec06e8f99..8af85476fc 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -138,8 +138,5 @@ typedef struct CPUWatchpoint { \ QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ CPUWatchpoint *watchpoint_hit; \ - \ - /* user data */ \ - void *opaque; \ #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index a385b9f71d..4d1ea35ca4 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -184,6 +184,7 @@ struct kvm_run; * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. * @next_cpu: Next CPU sharing TB cache. + * @opaque: User data. * @mem_io_pc: Host Program Counter at which the memory was accessed. * @mem_io_vaddr: Target virtual address at which the memory was accessed. * @kvm_fd: vCPU file descriptor for KVM. @@ -230,6 +231,8 @@ struct CPUState { int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + void *opaque; + /* In order to avoid passing too many arguments to the MMIO helpers, * we store some rarely used information in the CPU context. */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c0687e3b38..6bc799957b 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2621,7 +2621,8 @@ static int write_note(struct memelfnote *men, int fd) static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env) { - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + TaskState *ts = (TaskState *)cpu->opaque; struct elf_thread_status *ets; ets = g_malloc0(sizeof (*ets)); @@ -2650,8 +2651,8 @@ static int fill_note_info(struct elf_note_info *info, long signr, const CPUArchState *env) { #define NUMNOTES 3 - CPUState *cpu = NULL; - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + TaskState *ts = (TaskState *)cpu->opaque; int i; info->notes = g_malloc0(NUMNOTES * sizeof (struct memelfnote)); @@ -2775,7 +2776,8 @@ static int write_note_info(struct elf_note_info *info, int fd) */ static int elf_core_dump(int signr, const CPUArchState *env) { - const TaskState *ts = (const TaskState *)env->opaque; + const CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + const TaskState *ts = (const TaskState *)cpu->opaque; struct vm_area_struct *vma = NULL; char corefile[PATH_MAX]; struct elf_note_info info; diff --git a/linux-user/linuxload.c b/linux-user/linuxload.c index f2997c2f4b..506e837ae1 100644 --- a/linux-user/linuxload.c +++ b/linux-user/linuxload.c @@ -89,8 +89,7 @@ static int prepare_binprm(struct linux_binprm *bprm) abi_ulong loader_build_argptr(int envc, int argc, abi_ulong sp, abi_ulong stringp, int push_ptr) { - CPUArchState *env = thread_cpu->env_ptr; - TaskState *ts = (TaskState *)env->opaque; + TaskState *ts = (TaskState *)thread_cpu->opaque; int n = sizeof(abi_ulong); abi_ulong envp; abi_ulong argv; diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h index cad9c90dd0..bb4d3fabe1 100644 --- a/linux-user/m68k/target_cpu.h +++ b/linux-user/m68k/target_cpu.h @@ -31,7 +31,9 @@ static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp) static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + TaskState *ts = cs->opaque; + ts->tp_value = newtls; } diff --git a/linux-user/main.c b/linux-user/main.c index dee10841c3..6e62b8babd 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -685,7 +685,7 @@ void cpu_loop(CPUARMState *env) switch(trapnr) { case EXCP_UDEF: { - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; uint32_t opcode; int rc; @@ -2965,7 +2965,7 @@ void cpu_loop(CPUM68KState *env) int trapnr; unsigned int n; target_siginfo_t info; - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; for(;;) { trapnr = cpu_m68k_exec(env); @@ -4001,7 +4001,7 @@ int main(int argc, char **argv, char **envp) /* build Task State */ ts->info = info; ts->bprm = &bprm; - env->opaque = ts; + cpu->opaque = ts; task_settid(ts); execfd = qemu_getauxval(AT_EXECFD); diff --git a/linux-user/signal.c b/linux-user/signal.c index acf10328ee..24c91f37d9 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -370,7 +370,8 @@ void signal_init(void) static inline struct sigqueue *alloc_sigqueue(CPUArchState *env) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; struct sigqueue *q = ts->first_free; if (!q) return NULL; @@ -380,7 +381,9 @@ static inline struct sigqueue *alloc_sigqueue(CPUArchState *env) static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; + q->next = ts->first_free; ts->first_free = q; } @@ -388,8 +391,9 @@ static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q) /* abort execution with signal */ static void QEMU_NORETURN force_sig(int target_sig) { - CPUArchState *env = thread_cpu->env_ptr; - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = thread_cpu; + CPUArchState *env = cpu->env_ptr; + TaskState *ts = (TaskState *)cpu->opaque; int host_sig, core_dumped = 0; struct sigaction act; host_sig = target_to_host_signal(target_sig); @@ -440,7 +444,8 @@ static void QEMU_NORETURN force_sig(int target_sig) as possible */ int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; struct emulated_sigtable *k; struct sigqueue *q, **pq; abi_ulong handler; @@ -5676,7 +5681,7 @@ void process_pending_signals(CPUArchState *cpu_env) struct emulated_sigtable *k; struct target_sigaction *sa; struct sigqueue *q; - TaskState *ts = cpu_env->opaque; + TaskState *ts = cpu->opaque; if (!ts->signal_pending) return; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e2c10cc0bd..ffc11de4b7 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4243,7 +4243,7 @@ static void *clone_func(void *arg) env = info->env; cpu = ENV_GET_CPU(env); thread_cpu = cpu; - ts = (TaskState *)env->opaque; + ts = (TaskState *)cpu->opaque; info->tid = gettid(); cpu->host_tid = info->tid; task_settid(ts); @@ -4271,8 +4271,10 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, abi_ulong parent_tidptr, target_ulong newtls, abi_ulong child_tidptr) { + CPUState *cpu = ENV_GET_CPU(env); int ret; TaskState *ts; + CPUState *new_cpu; CPUArchState *new_env; unsigned int nptl_flags; sigset_t sigmask; @@ -4282,7 +4284,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, flags &= ~(CLONE_VFORK | CLONE_VM); if (flags & CLONE_VM) { - TaskState *parent_ts = (TaskState *)env->opaque; + TaskState *parent_ts = (TaskState *)cpu->opaque; new_thread_info info; pthread_attr_t attr; @@ -4292,7 +4294,8 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, new_env = cpu_copy(env); /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); - new_env->opaque = ts; + new_cpu = ENV_GET_CPU(new_env); + new_cpu->opaque = ts; ts->bprm = parent_ts->bprm; ts->info = parent_ts->info; nptl_flags = flags; @@ -4364,7 +4367,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, put_user_u32(gettid(), child_tidptr); if (flags & CLONE_PARENT_SETTID) put_user_u32(gettid(), parent_tidptr); - ts = (TaskState *)env->opaque; + ts = (TaskState *)cpu->opaque; if (flags & CLONE_SETTLS) cpu_set_tls (env, newtls); if (flags & CLONE_CHILD_CLEARTID) @@ -4974,7 +4977,8 @@ void init_qemu_uname_release(void) static int open_self_maps(void *cpu_env, int fd) { #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; #endif FILE *fp; char *line = NULL; @@ -5026,7 +5030,8 @@ static int open_self_maps(void *cpu_env, int fd) static int open_self_stat(void *cpu_env, int fd) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; abi_ulong start_stack = ts->info->start_stack; int i; @@ -5062,7 +5067,8 @@ static int open_self_stat(void *cpu_env, int fd) static int open_self_auxv(void *cpu_env, int fd) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; abi_ulong auxv = ts->info->saved_auxv; abi_ulong len = ts->info->auxv_len; char *ptr; @@ -5244,14 +5250,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, /* Remove the CPU from the list. */ QTAILQ_REMOVE(&cpus, cpu, node); cpu_list_unlock(); - ts = ((CPUArchState *)cpu_env)->opaque; + ts = cpu->opaque; if (ts->child_tidptr) { put_user_u32(0, ts->child_tidptr); sys_futex(g2h(ts->child_tidptr), FUTEX_WAKE, INT_MAX, NULL, NULL, 0); } thread_cpu = NULL; - object_unref(OBJECT(ENV_GET_CPU(cpu_env))); + object_unref(OBJECT(cpu)); g_free(ts); pthread_exit(NULL); } @@ -6555,7 +6561,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; case TARGET_NR_mprotect: { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; /* Special hack to detect libc making the stack executable. */ if ((arg3 & PROT_GROWSDOWN) && arg1 >= ts->info->stack_limit @@ -8647,7 +8653,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; #elif defined(TARGET_M68K) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; ts->tp_value = arg1; ret = 0; break; @@ -8663,7 +8669,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; #elif defined(TARGET_M68K) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; ret = ts->tp_value; break; } diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 2c4ffeb551..45ef559ec6 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -72,7 +72,8 @@ static inline unsigned int vm_getl(uint32_t segptr, unsigned int reg16) void save_v86_state(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0)) @@ -131,7 +132,8 @@ static inline void return_to_32bit(CPUX86State *env, int retval) static inline int set_IF(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; ts->v86flags |= VIF_MASK; if (ts->v86flags & VIP_MASK) { @@ -143,7 +145,8 @@ static inline int set_IF(CPUX86State *env) static inline void clear_IF(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; ts->v86flags &= ~VIF_MASK; } @@ -160,7 +163,8 @@ static inline void clear_AC(CPUX86State *env) static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; set_flags(ts->v86flags, eflags, ts->v86mask); set_flags(env->eflags, eflags, SAFE_MASK); @@ -173,7 +177,8 @@ static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) static inline int set_vflags_short(unsigned short flags, CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; set_flags(ts->v86flags, flags, ts->v86mask & 0xffff); set_flags(env->eflags, flags, SAFE_MASK); @@ -186,7 +191,8 @@ static inline int set_vflags_short(unsigned short flags, CPUX86State *env) static inline unsigned int get_vflags(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; unsigned int flags; flags = env->eflags & RETURN_MASK; @@ -202,7 +208,8 @@ static inline unsigned int get_vflags(CPUX86State *env) support TSS interrupt revectoring, so this code is always executed) */ static void do_int(CPUX86State *env, int intno) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; uint32_t int_addr, segoffs, ssp; unsigned int sp; @@ -260,7 +267,8 @@ void handle_vm86_trap(CPUX86State *env, int trapno) void handle_vm86_fault(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; uint32_t csp, ssp; unsigned int ip, sp, newflags, newip, newcs, opcode, intno; int data32, pref_done; @@ -384,7 +392,8 @@ void handle_vm86_fault(CPUX86State *env) int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; int ret; diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c index ee469c49c5..ebb5235521 100644 --- a/target-arm/arm-semi.c +++ b/target-arm/arm-semi.c @@ -127,7 +127,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; #ifdef CONFIG_USER_ONLY - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; #endif if (ret == (target_ulong)-1) { @@ -164,7 +164,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0); env->regs[0] = be32_to_cpu(size); #ifdef CONFIG_USER_ONLY - ((TaskState *)env->opaque)->swi_errno = err; + ((TaskState *)cs->opaque)->swi_errno = err; #else syscall_err = err; #endif @@ -183,6 +183,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) uint32_t do_arm_semihosting(CPUARMState *env) { ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; @@ -190,7 +191,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) uint32_t ret; uint32_t len; #ifdef CONFIG_USER_ONLY - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; #else CPUARMState *ts = env; #endif @@ -554,7 +555,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) exit(0); default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); - cpu_dump_state(CPU(cpu), stderr, fprintf, 0); + cpu_dump_state(cs, stderr, fprintf, 0); abort(); } } diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index 94c4983813..2dea3cac90 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -428,7 +428,8 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) case HOSTED_INIT_SIM: #if defined(CONFIG_USER_ONLY) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + TaskState *ts = cs->opaque; /* Allocate the heap using sbrk. */ if (!ts->heap_limit) { abi_ulong ret; -- cgit v1.2.3-55-g7522 From ff4700b05cfb305a880762c288b88ca01c782352 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 18:23:18 +0200 Subject: cpu: Move watchpoint fields from CPU_COMMON to CPUState Signed-off-by: Andreas Färber --- cpu-exec.c | 5 +++-- exec.c | 33 ++++++++++++++++++++------------- gdbstub.c | 8 ++++---- include/exec/cpu-defs.h | 10 ---------- include/qom/cpu.h | 10 ++++++++++ linux-user/main.c | 5 +++-- target-i386/cpu.h | 2 +- target-i386/helper.c | 7 ++++--- target-i386/kvm.c | 8 ++++---- target-lm32/cpu.h | 2 +- target-lm32/helper.c | 7 ++++--- target-xtensa/cpu.h | 2 +- target-xtensa/helper.c | 8 +++++--- 13 files changed, 60 insertions(+), 47 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/cpu-exec.c b/cpu-exec.c index 798dc084d9..d7c21d35e5 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -200,10 +200,11 @@ void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler) static void cpu_handle_debug_exception(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); CPUWatchpoint *wp; - if (!env->watchpoint_hit) { - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + if (!cpu->watchpoint_hit) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { wp->flags &= ~BP_WATCHPOINT_HIT; } } diff --git a/exec.c b/exec.c index 26ed9ccd0c..ee5eff7734 100644 --- a/exec.c +++ b/exec.c @@ -485,7 +485,7 @@ void cpu_exec_init(CPUArchState *env) cpu->cpu_index = cpu_index; cpu->numa_node = 0; QTAILQ_INIT(&env->breakpoints); - QTAILQ_INIT(&env->watchpoints); + QTAILQ_INIT(&cpu->watchpoints); #ifndef CONFIG_USER_ONLY cpu->as = &address_space_memory; cpu->thread_id = qemu_get_thread_id(); @@ -542,6 +542,7 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, int flags, CPUWatchpoint **watchpoint) { + CPUState *cpu = ENV_GET_CPU(env); target_ulong len_mask = ~(len - 1); CPUWatchpoint *wp; @@ -559,10 +560,11 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len wp->flags = flags; /* keep all GDB-injected watchpoints in front */ - if (flags & BP_GDB) - QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); - else - QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); + if (flags & BP_GDB) { + QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); + } else { + QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); + } tlb_flush_page(env, addr); @@ -575,10 +577,11 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len, int flags) { + CPUState *cpu = ENV_GET_CPU(env); target_ulong len_mask = ~(len - 1); CPUWatchpoint *wp; - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (addr == wp->vaddr && len_mask == wp->len_mask && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { cpu_watchpoint_remove_by_ref(env, wp); @@ -591,7 +594,9 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len /* Remove a specific watchpoint by reference. */ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) { - QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); + CPUState *cpu = ENV_GET_CPU(env); + + QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); tlb_flush_page(env, watchpoint->vaddr); @@ -601,9 +606,10 @@ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) /* Remove all matching watchpoints. */ void cpu_watchpoint_remove_all(CPUArchState *env, int mask) { + CPUState *cpu = ENV_GET_CPU(env); CPUWatchpoint *wp, *next; - QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { + QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { if (wp->flags & mask) cpu_watchpoint_remove_by_ref(env, wp); } @@ -799,6 +805,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env, int prot, target_ulong *address) { + CPUState *cpu = ENV_GET_CPU(env); hwaddr iotlb; CPUWatchpoint *wp; @@ -818,7 +825,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env, /* Make accesses to pages with watchpoints go via the watchpoint trap routines. */ - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { /* Avoid trapping reads of pages with a write breakpoint. */ if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { @@ -1579,7 +1586,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) CPUWatchpoint *wp; int cpu_flags; - if (env->watchpoint_hit) { + if (cpu->watchpoint_hit) { /* We re-entered the check after replacing the TB. Now raise * the debug interrupt so that is will trigger after the * current instruction. */ @@ -1587,12 +1594,12 @@ static void check_watchpoint(int offset, int len_mask, int flags) return; } vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if ((vaddr == (wp->vaddr & len_mask) || (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { wp->flags |= BP_WATCHPOINT_HIT; - if (!env->watchpoint_hit) { - env->watchpoint_hit = wp; + if (!cpu->watchpoint_hit) { + cpu->watchpoint_hit = wp; tb_check_watchpoint(env); if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index = EXCP_DEBUG; diff --git a/gdbstub.c b/gdbstub.c index c5ab73fb1d..0176b3f80e 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1204,8 +1204,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) } switch (state) { case RUN_STATE_DEBUG: - if (env->watchpoint_hit) { - switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) { + if (cpu->watchpoint_hit) { + switch (cpu->watchpoint_hit->flags & BP_MEM_ACCESS) { case BP_MEM_READ: type = "r"; break; @@ -1219,8 +1219,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) snprintf(buf, sizeof(buf), "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";", GDB_SIGNAL_TRAP, cpu_index(cpu), type, - env->watchpoint_hit->vaddr); - env->watchpoint_hit = NULL; + (target_ulong)cpu->watchpoint_hit->vaddr); + cpu->watchpoint_hit = NULL; goto send_packet; } tb_flush(env); diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 8af85476fc..31aac691c5 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -120,13 +120,6 @@ typedef struct CPUBreakpoint { QTAILQ_ENTRY(CPUBreakpoint) entry; } CPUBreakpoint; -typedef struct CPUWatchpoint { - target_ulong vaddr; - target_ulong len_mask; - int flags; /* BP_* */ - QTAILQ_ENTRY(CPUWatchpoint) entry; -} CPUWatchpoint; - #define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ /* soft mmu support */ \ @@ -135,8 +128,5 @@ typedef struct CPUWatchpoint { /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ - \ - QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ - CPUWatchpoint *watchpoint_hit; \ #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4d1ea35ca4..c7420e070b 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -151,6 +151,13 @@ typedef struct icount_decr_u16 { } icount_decr_u16; #endif +typedef struct CPUWatchpoint { + vaddr vaddr; + vaddr len_mask; + int flags; /* BP_* */ + QTAILQ_ENTRY(CPUWatchpoint) entry; +} CPUWatchpoint; + struct KVMState; struct kvm_run; @@ -231,6 +238,9 @@ struct CPUState { int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; + CPUWatchpoint *watchpoint_hit; + void *opaque; /* In order to avoid passing too many arguments to the MMIO helpers, diff --git a/linux-user/main.c b/linux-user/main.c index 6e62b8babd..5a06192ec4 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3435,6 +3435,7 @@ void init_task_state(TaskState *ts) CPUArchState *cpu_copy(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); CPUArchState *new_env = cpu_init(cpu_model); #if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; @@ -3450,12 +3451,12 @@ CPUArchState *cpu_copy(CPUArchState *env) Note: Once we support ptrace with hw-debug register access, make sure BP_CPU break/watchpoints are handled correctly on clone. */ QTAILQ_INIT(&env->breakpoints); - QTAILQ_INIT(&env->watchpoints); + QTAILQ_INIT(&cpu->watchpoints); #if defined(TARGET_HAS_ICE) QTAILQ_FOREACH(bp, &env->breakpoints, entry) { cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); } - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, wp->flags, NULL); } diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 62641af77e..906018757d 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -876,7 +876,7 @@ typedef struct CPUX86State { target_ulong dr[8]; /* debug registers */ union { CPUBreakpoint *cpu_breakpoint[4]; - CPUWatchpoint *cpu_watchpoint[4]; + struct CPUWatchpoint *cpu_watchpoint[4]; }; /* break/watchpoints for dr[0..3] */ uint32_t smbase; int old_exception; /* exception in flight */ diff --git a/target-i386/helper.c b/target-i386/helper.c index 6d9bd71a3a..bd8da20946 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1088,11 +1088,12 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update) void breakpoint_handler(CPUX86State *env) { + CPUState *cs = CPU(x86_env_get_cpu(env)); CPUBreakpoint *bp; - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { - env->watchpoint_hit = NULL; + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; if (check_hw_breakpoints(env, false)) { raise_exception(env, EXCP01_DB); } else { diff --git a/target-i386/kvm.c b/target-i386/kvm.c index e555040a97..7a295f6f20 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -2277,13 +2277,13 @@ static int kvm_handle_debug(X86CPU *cpu, break; case 0x1: ret = EXCP_DEBUG; - env->watchpoint_hit = &hw_watchpoint; + cs->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_WRITE; break; case 0x3: ret = EXCP_DEBUG; - env->watchpoint_hit = &hw_watchpoint; + cs->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_ACCESS; break; @@ -2291,11 +2291,11 @@ static int kvm_handle_debug(X86CPU *cpu, } } } - } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) { + } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { ret = EXCP_DEBUG; } if (ret == 0) { - cpu_synchronize_state(CPU(cpu)); + cpu_synchronize_state(cs); assert(env->exception_injected == -1); /* pass to guest */ diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index b94d9b007e..d50726bce7 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -167,7 +167,7 @@ struct CPULM32State { uint32_t wp[4]; /* watchpoints */ CPUBreakpoint * cpu_breakpoint[4]; - CPUWatchpoint * cpu_watchpoint[4]; + struct CPUWatchpoint *cpu_watchpoint[4]; CPU_COMMON diff --git a/target-lm32/helper.c b/target-lm32/helper.c index e5536c0ecb..67ba278e27 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -118,11 +118,12 @@ static bool check_watchpoints(CPULM32State *env) void lm32_debug_excp_handler(CPULM32State *env) { + CPUState *cs = CPU(lm32_env_get_cpu(env)); CPUBreakpoint *bp; - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { - env->watchpoint_hit = NULL; + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; if (check_watchpoints(env)) { raise_exception(env, EXCP_WATCHPOINT); } else { diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 4bae693c6d..e210bacdff 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -359,7 +359,7 @@ typedef struct CPUXtensaState { int exception_taken; /* Watchpoints for DBREAK registers */ - CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; + struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; CPU_COMMON } CPUXtensaState; diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 259878837f..8a9cb0a825 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -81,11 +81,13 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env) void xtensa_breakpoint_handler(CPUXtensaState *env) { - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { uint32_t cause; - env->watchpoint_hit = NULL; + cs->watchpoint_hit = NULL; cause = check_hw_breakpoints(env); if (cause) { debug_exception_env(env, cause); -- cgit v1.2.3-55-g7522 From f0c3c505a8ec1a948006b3a16a35864a2270a84b Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 21:22:53 +0200 Subject: cpu: Move breakpoints field from CPU_COMMON to CPUState Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber --- exec.c | 21 +++++++++++++-------- include/exec/cpu-defs.h | 10 ---------- include/qom/cpu.h | 9 +++++++++ linux-user/main.c | 4 ++-- target-alpha/translate.c | 4 ++-- target-arm/cpu.c | 2 +- target-arm/translate-a64.c | 4 ++-- target-arm/translate.c | 4 ++-- target-cris/cpu.c | 2 +- target-cris/cpu.h | 4 ++-- target-cris/translate.c | 5 +++-- target-i386/cpu.c | 2 +- target-i386/cpu.h | 3 ++- target-i386/helper.c | 3 ++- target-i386/translate.c | 4 ++-- target-lm32/cpu.c | 2 +- target-lm32/cpu.h | 3 ++- target-lm32/helper.c | 2 +- target-lm32/translate.c | 5 +++-- target-m68k/cpu.c | 2 +- target-m68k/cpu.h | 1 + target-m68k/translate.c | 4 ++-- target-microblaze/cpu.c | 2 +- target-microblaze/translate.c | 5 +++-- target-mips/cpu.c | 2 +- target-mips/cpu.h | 1 + target-mips/translate.c | 4 ++-- target-moxie/cpu.c | 2 +- target-moxie/translate.c | 4 ++-- target-openrisc/cpu.c | 6 +++++- target-openrisc/cpu.h | 1 + target-openrisc/translate.c | 5 +++-- target-ppc/translate.c | 4 ++-- target-s390x/cpu.c | 4 ++-- target-s390x/translate.c | 4 ++-- target-sh4/cpu.c | 2 +- target-sh4/cpu.h | 1 + target-sh4/translate.c | 4 ++-- target-sparc/cpu.c | 2 +- target-sparc/cpu.h | 1 + target-sparc/translate.c | 4 ++-- target-unicore32/translate.c | 4 ++-- target-xtensa/translate.c | 5 +++-- 43 files changed, 94 insertions(+), 73 deletions(-) (limited to 'include/exec/cpu-defs.h') diff --git a/exec.c b/exec.c index ee5eff7734..6d9e13a0a6 100644 --- a/exec.c +++ b/exec.c @@ -484,7 +484,7 @@ void cpu_exec_init(CPUArchState *env) } cpu->cpu_index = cpu_index; cpu->numa_node = 0; - QTAILQ_INIT(&env->breakpoints); + QTAILQ_INIT(&cpu->breakpoints); QTAILQ_INIT(&cpu->watchpoints); #ifndef CONFIG_USER_ONLY cpu->as = &address_space_memory; @@ -621,6 +621,7 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, CPUBreakpoint **breakpoint) { #if defined(TARGET_HAS_ICE) + CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; bp = g_malloc(sizeof(*bp)); @@ -630,12 +631,12 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, /* keep all GDB-injected breakpoints in front */ if (flags & BP_GDB) { - QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); + QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); } else { - QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); + QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); } - breakpoint_invalidate(ENV_GET_CPU(env), pc); + breakpoint_invalidate(cpu, pc); if (breakpoint) { *breakpoint = bp; @@ -650,9 +651,10 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) { #if defined(TARGET_HAS_ICE) + CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc == pc && bp->flags == flags) { cpu_breakpoint_remove_by_ref(env, bp); return 0; @@ -668,9 +670,11 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) { #if defined(TARGET_HAS_ICE) - QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); + CPUState *cpu = ENV_GET_CPU(env); - breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc); + QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); + + breakpoint_invalidate(cpu, breakpoint->pc); g_free(breakpoint); #endif @@ -680,9 +684,10 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) void cpu_breakpoint_remove_all(CPUArchState *env, int mask) { #if defined(TARGET_HAS_ICE) + CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp, *next; - QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { + QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { if (bp->flags & mask) cpu_breakpoint_remove_by_ref(env, bp); } diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 31aac691c5..2dd6206d4a 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -114,19 +114,9 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); #endif -typedef struct CPUBreakpoint { - target_ulong pc; - int flags; /* BP_* */ - QTAILQ_ENTRY(CPUBreakpoint) entry; -} CPUBreakpoint; - #define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ /* soft mmu support */ \ CPU_COMMON_TLB \ - \ - /* from this point: preserved by CPU reset */ \ - /* ice debug support */ \ - QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index c7420e070b..3bbda08eac 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -151,6 +151,12 @@ typedef struct icount_decr_u16 { } icount_decr_u16; #endif +typedef struct CPUBreakpoint { + vaddr pc; + int flags; /* BP_* */ + QTAILQ_ENTRY(CPUBreakpoint) entry; +} CPUBreakpoint; + typedef struct CPUWatchpoint { vaddr vaddr; vaddr len_mask; @@ -238,6 +244,9 @@ struct CPUState { int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + /* ice debug support */ + QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; + QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; CPUWatchpoint *watchpoint_hit; diff --git a/linux-user/main.c b/linux-user/main.c index 5a06192ec4..dbc04b7d0f 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3450,10 +3450,10 @@ CPUArchState *cpu_copy(CPUArchState *env) /* Clone all break/watchpoints. Note: Once we support ptrace with hw-debug register access, make sure BP_CPU break/watchpoints are handled correctly on clone. */ - QTAILQ_INIT(&env->breakpoints); + QTAILQ_INIT(&cpu->breakpoints); QTAILQ_INIT(&cpu->watchpoints); #if defined(TARGET_HAS_ICE) - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 4c94bed704..a9ef1a7507 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3463,8 +3463,8 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.pc) { gen_excp(&ctx, EXCP_DEBUG, 0); break; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index be17d72537..ecd0b7ecde 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -82,7 +82,7 @@ static void arm_cpu_reset(CPUState *s) acc->parent_reset(s); - memset(env, 0, offsetof(CPUARMState, breakpoints)); + memset(env, 0, offsetof(CPUARMState, features)); g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 37e05e81f7..2fd9113628 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -9061,8 +9061,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_clear_temp_count(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception_insn(dc, 0, EXCP_DEBUG); /* Advance PC so that clearing the breakpoint will diff --git a/target-arm/translate.c b/target-arm/translate.c index df259debcc..2f02c183a7 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -10733,8 +10733,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, } #endif - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception_insn(dc, 0, EXCP_DEBUG); /* Advance PC so that clearing the breakpoint will diff --git a/target-cris/cpu.c b/target-cris/cpu.c index ff27e7f773..95b6a8889b 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -49,7 +49,7 @@ static void cris_cpu_reset(CPUState *s) ccc->parent_reset(s); vr = env->pregs[PR_VR]; - memset(env, 0, offsetof(CPUCRISState, breakpoints)); + memset(env, 0, offsetof(CPUCRISState, load_info)); env->pregs[PR_VR] = vr; tlb_flush(env, 1); diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 6cc0616523..b88c147518 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -171,8 +171,8 @@ typedef struct CPUCRISState { CPU_COMMON - /* Members after CPU_COMMON are preserved across resets. */ - void *load_info; + /* Members from load_info on are preserved across resets. */ + void *load_info; } CPUCRISState; #include "cpu-qom.h" diff --git a/target-cris/translate.c b/target-cris/translate.c index f990d591c7..7e70940c9b 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3089,10 +3089,11 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) static void check_breakpoint(CPUCRISState *env, DisasContext *dc) { + CPUState *cs = CPU(cris_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { cris_evaluate_flags(dc); tcg_gen_movi_tl(env_pc, dc->pc); diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 63ba2194cb..fab0f55735 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2410,7 +2410,7 @@ static void x86_cpu_reset(CPUState *s) xcc->parent_reset(s); - memset(env, 0, offsetof(CPUX86State, breakpoints)); + memset(env, 0, offsetof(CPUX86State, pat)); tlb_flush(env, 1); diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 906018757d..4d1374c6cc 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -875,7 +875,7 @@ typedef struct CPUX86State { target_ulong exception_next_eip; target_ulong dr[8]; /* debug registers */ union { - CPUBreakpoint *cpu_breakpoint[4]; + struct CPUBreakpoint *cpu_breakpoint[4]; struct CPUWatchpoint *cpu_watchpoint[4]; }; /* break/watchpoints for dr[0..3] */ uint32_t smbase; @@ -887,6 +887,7 @@ typedef struct CPUX86State { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint64_t pat; /* processor features (e.g. for CPUID insn) */ diff --git a/target-i386/helper.c b/target-i386/helper.c index bd8da20946..59736d7a4f 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1101,7 +1101,7 @@ void breakpoint_handler(CPUX86State *env) } } } else { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == env->eip) { if (bp->flags & BP_CPU) { check_hw_breakpoints(env, true); @@ -1109,6 +1109,7 @@ void breakpoint_handler(CPUX86State *env) } break; } + } } } diff --git a/target-i386/translate.c b/target-i386/translate.c index 707ebd5ca0..02625e31c2 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7965,8 +7965,8 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, gen_tb_start(); for(;;) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == pc_ptr && !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { gen_debug(dc, pc_ptr - dc->cs_base); diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index daec499502..d0c66bc0f5 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -125,7 +125,7 @@ static void lm32_cpu_reset(CPUState *s) lcc->parent_reset(s); /* reset cpu state */ - memset(env, 0, offsetof(CPULM32State, breakpoints)); + memset(env, 0, offsetof(CPULM32State, eba)); lm32_cpu_init_cfg_reg(cpu); tlb_flush(env, 1); diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index d50726bce7..24bde78502 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -166,11 +166,12 @@ struct CPULM32State { uint32_t bp[4]; /* breakpoints */ uint32_t wp[4]; /* watchpoints */ - CPUBreakpoint * cpu_breakpoint[4]; + struct CPUBreakpoint *cpu_breakpoint[4]; struct CPUWatchpoint *cpu_watchpoint[4]; CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint32_t eba; /* exception base address */ uint32_t deba; /* debug exception base address */ diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 67ba278e27..eadc7277a7 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -131,7 +131,7 @@ void lm32_debug_excp_handler(CPULM32State *env) } } } else { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == env->pc) { if (bp->flags & BP_CPU) { raise_exception(env, EXCP_BREAKPOINT); diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 80bffc7b27..c8abd1f27e 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1037,10 +1037,11 @@ static inline void decode(DisasContext *dc, uint32_t ir) static void check_breakpoint(CPULM32State *env, DisasContext *dc) { + CPUState *cs = CPU(lm32_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_tl(cpu_pc, dc->pc); t_gen_raise_exception(dc, EXCP_DEBUG); diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 46601dcd5d..a88da20b46 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -49,7 +49,7 @@ static void m68k_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUM68KState, breakpoints)); + memset(env, 0, offsetof(CPUM68KState, features)); #if !defined(CONFIG_USER_ONLY) env->sr = 0x2700; #endif diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index dd1794feac..6e4001d523 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -110,6 +110,7 @@ typedef struct CPUM68KState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint32_t features; } CPUM68KState; diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 4f06443532..a0e2f19e15 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3003,8 +3003,8 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, do { pc_offset = dc->pc - pc_start; gen_throws_exception = NULL; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception(dc, dc->pc, EXCP_DEBUG); dc->is_jmp = DISAS_JUMP; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 86ec25811e..3177fe6d12 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -63,7 +63,7 @@ static void mb_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMBState, breakpoints)); + memset(env, 0, sizeof(CPUMBState)); env->res_addr = RES_ADDR_NONE; tlb_flush(env, 1); diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 270138c6d2..fbd6951d1a 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1660,10 +1660,11 @@ static inline void decode(DisasContext *dc, uint32_t ir) static void check_breakpoint(CPUMBState *env, DisasContext *dc) { + CPUState *cs = CPU(mb_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { t_gen_raise_exception(dc, EXCP_DEBUG); dc->is_jmp = DISAS_UPDATE; diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 8c304ac832..cf4d856d6b 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -83,7 +83,7 @@ static void mips_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMIPSState, breakpoints)); + memset(env, 0, offsetof(CPUMIPSState, mvp)); tlb_flush(env, 1); cpu_state_reset(env); diff --git a/target-mips/cpu.h b/target-mips/cpu.h index a1d85efea1..3ba3229e66 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -482,6 +482,7 @@ struct CPUMIPSState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; diff --git a/target-mips/translate.c b/target-mips/translate.c index d1c25d2b22..71dccaea55 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15613,8 +15613,8 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); gen_tb_start(); while (ctx.bstate == BS_NONE) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.pc) { save_cpu_state(&ctx, 1); ctx.bstate = BS_BRANCH; diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 03d8eb13d7..14d1a24438 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -42,7 +42,7 @@ static void moxie_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMoxieState, breakpoints)); + memset(env, 0, sizeof(CPUMoxieState)); env->pc = 0x1000; tlb_flush(env, 1); diff --git a/target-moxie/translate.c b/target-moxie/translate.c index a93196f47b..63f889fd7f 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -845,8 +845,8 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (ctx.pc == bp->pc) { tcg_gen_movi_i32(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index b601de009c..a00369bef5 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -41,7 +41,11 @@ static void openrisc_cpu_reset(CPUState *s) occ->parent_reset(s); - memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); +#ifndef CONFIG_USER_ONLY + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb)); +#else + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq)); +#endif tlb_flush(&cpu->env, 1); /*tb_flush(&cpu->env); FIXME: Do we need it? */ diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 660bb4f1e7..4512f459bf 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -304,6 +304,7 @@ typedef struct CPUOpenRISCState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ #ifndef CONFIG_USER_ONLY CPUOpenRISCTLBContext * tlb; diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 776cb6eece..852b5e6107 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1619,10 +1619,11 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc) { + CPUState *cs = CPU(cpu); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&cpu->env.breakpoints))) { - QTAILQ_FOREACH(bp, &cpu->env.breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_tl(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 91c33dcd1d..e3fcb03c26 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11377,8 +11377,8 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, /* Set env in case of segfault during code fetch */ while (ctx.exception == POWERPC_EXCP_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.nip) { gen_debug_exception(ctxp); break; diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 993d924e52..ae78ebc5f7 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -109,7 +109,7 @@ static void s390_cpu_initial_reset(CPUState *s) s390_cpu_reset(s); /* initial reset does not touch regs,fregs and aregs */ - memset(&env->fpc, 0, offsetof(CPUS390XState, breakpoints) - + memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) - offsetof(CPUS390XState, fpc)); /* architectured initial values for CR 0 and 14 */ @@ -139,7 +139,7 @@ static void s390_cpu_full_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUS390XState, breakpoints)); + memset(env, 0, offsetof(CPUS390XState, cpu_num)); /* architectured initial values for CR 0 and 14 */ env->cregs[0] = CR0_RESET; diff --git a/target-s390x/translate.c b/target-s390x/translate.c index bc99a378a7..81b7e330ab 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -4795,8 +4795,8 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu, } status = NO_EXIT; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc.pc) { status = EXIT_PC_STALE; do_debug = true; diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 88960c8512..4e0e2179cc 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -53,7 +53,7 @@ static void superh_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUSH4State, breakpoints)); + memset(env, 0, offsetof(CPUSH4State, id)); tlb_flush(env, 1); env->pc = 0xA0000000; diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index a85571087d..a2e9e2c031 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -175,6 +175,7 @@ typedef struct CPUSH4State { CPU_COMMON + /* Fields from here on are preserved over CPU reset. */ int id; /* CPU model */ /* The features that we should emulate. See sh_features above. */ diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 661fc6c887..2360609a0a 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1889,8 +1889,8 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, max_insns = CF_COUNT_MASK; gen_tb_start(); while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (ctx.pc == bp->pc) { /* We have hit a breakpoint - make sure PC is up-to-date */ tcg_gen_movi_i32(cpu_pc, ctx.pc); diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 3e6e7a754e..8465a0b18a 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -33,7 +33,7 @@ static void sparc_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUSPARCState, breakpoints)); + memset(env, 0, offsetof(CPUSPARCState, version)); tlb_flush(env, 1); env->cwp = 0; #ifndef TARGET_SPARC64 diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 893caa0576..f72451d53e 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -423,6 +423,7 @@ struct CPUSPARCState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ target_ulong version; uint32_t nwindows; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 46d7859e97..2de1c4a58d 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5270,8 +5270,8 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, max_insns = CF_COUNT_MASK; gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { if (dc->pc != pc_start) save_state(dc); diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 4572890ffa..5032bbe2a0 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1922,8 +1922,8 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_set_pc_im(dc->pc); gen_exception(EXCP_DEBUG); diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 9f5895e021..764cee96f3 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2948,10 +2948,11 @@ invalid_opcode: static void check_breakpoint(CPUXtensaState *env, DisasContext *dc) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_i32(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); -- cgit v1.2.3-55-g7522