From c5a49c63fa26e8825ad101dfe86339ae4c216539 Mon Sep 17 00:00:00 2001 From: Emilio G. Cota Date: Tue, 18 Jul 2017 20:46:52 -0400 Subject: tcg: convert tb->cflags reads to tb_cflags(tb) Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \ accel/tcg/translator.c | cut -f1 -d':' | sort | uniq) perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/exec/gen-icount.h') diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 9b3cb14dfa..48b566c1c9 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -13,7 +13,7 @@ static inline void gen_tb_start(TranslationBlock *tb) TCGv_i32 count, imm; exitreq_label = gen_new_label(); - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { count = tcg_temp_local_new_i32(); } else { count = tcg_temp_new_i32(); @@ -22,7 +22,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_ld_i32(count, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { imm = tcg_temp_new_i32(); /* We emit a movi with a dummy immediate argument. Keep the insn index * of the movi so that we later (when we know the actual insn count) @@ -36,7 +36,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low)); } @@ -46,7 +46,7 @@ static inline void gen_tb_start(TranslationBlock *tb) static inline void gen_tb_end(TranslationBlock *tb, int num_insns) { - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { /* Update the num_insn immediate parameter now that we know * the actual insn count. */ tcg_set_insn_param(icount_start_insn_idx, 1, num_insns); -- cgit v1.2.3-55-g7522 From b1311c4acf503dc9c1a310cc40b64f05b08833dc Mon Sep 17 00:00:00 2001 From: Emilio G. Cota Date: Wed, 12 Jul 2017 17:15:52 -0400 Subject: tcg: define tcg_init_ctx and make tcg_ctx a pointer Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 109 +++++++++++++++++++++--------------------- bsd-user/main.c | 2 +- include/exec/gen-icount.h | 10 ++-- linux-user/main.c | 2 +- target/alpha/translate.c | 2 +- target/arm/translate.c | 2 +- target/cris/translate.c | 2 +- target/cris/translate_v10.c | 2 +- target/hppa/translate.c | 2 +- target/i386/translate.c | 2 +- target/lm32/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/translate.c | 2 +- target/moxie/translate.c | 2 +- target/nios2/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 2 +- target/s390x/translate.c | 2 +- target/sh4/translate.c | 2 +- target/sparc/translate.c | 2 +- target/tilegx/translate.c | 2 +- target/tricore/translate.c | 2 +- target/unicore32/translate.c | 2 +- target/xtensa/translate.c | 2 +- tcg/tcg-op.c | 46 +++++++++--------- tcg/tcg.c | 22 +++++---- tcg/tcg.h | 21 ++++---- 29 files changed, 130 insertions(+), 126 deletions(-) (limited to 'include/exec/gen-icount.h') diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 25f0cabfed..4172ffda82 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -153,7 +153,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags()); if (tb == NULL) { - return tcg_ctx.code_gen_epilogue; + return tcg_ctx->code_gen_epilogue; } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b238b724a8..7cd9ad5f9c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -153,7 +153,8 @@ static int v_l2_levels; static void *l1_map[V_L1_MAX_SIZE]; /* code generation context */ -TCGContext tcg_ctx; +TCGContext tcg_init_ctx; +TCGContext *tcg_ctx; TBContext tb_ctx; bool parallel_cpus; @@ -209,7 +210,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr); void cpu_gen_init(void) { - tcg_context_init(&tcg_ctx); + tcg_context_init(&tcg_init_ctx); } /* Encode VAL as a signed leb128 sequence at P. @@ -267,7 +268,7 @@ static target_long decode_sleb128(uint8_t **pp) static int encode_search(TranslationBlock *tb, uint8_t *block) { - uint8_t *highwater = tcg_ctx.code_gen_highwater; + uint8_t *highwater = tcg_ctx->code_gen_highwater; uint8_t *p = block; int i, j, n; @@ -278,12 +279,12 @@ static int encode_search(TranslationBlock *tb, uint8_t *block) if (i == 0) { prev = (j == 0 ? tb->pc : 0); } else { - prev = tcg_ctx.gen_insn_data[i - 1][j]; + prev = tcg_ctx->gen_insn_data[i - 1][j]; } - p = encode_sleb128(p, tcg_ctx.gen_insn_data[i][j] - prev); + p = encode_sleb128(p, tcg_ctx->gen_insn_data[i][j] - prev); } - prev = (i == 0 ? 0 : tcg_ctx.gen_insn_end_off[i - 1]); - p = encode_sleb128(p, tcg_ctx.gen_insn_end_off[i] - prev); + prev = (i == 0 ? 0 : tcg_ctx->gen_insn_end_off[i - 1]); + p = encode_sleb128(p, tcg_ctx->gen_insn_end_off[i] - prev); /* Test for (pending) buffer overflow. The assumption is that any one row beginning below the high water mark cannot overrun @@ -343,8 +344,8 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, restore_state_to_opc(env, tb, data); #ifdef CONFIG_PROFILER - tcg_ctx.restore_time += profile_getclock() - ti; - tcg_ctx.restore_count++; + tcg_ctx->restore_time += profile_getclock() - ti; + tcg_ctx->restore_count++; #endif return 0; } @@ -590,7 +591,7 @@ static inline void *split_cross_256mb(void *buf1, size_t size1) buf1 = buf2; } - tcg_ctx.code_gen_buffer_size = size1; + tcg_ctx->code_gen_buffer_size = size1; return buf1; } #endif @@ -653,16 +654,16 @@ static inline void *alloc_code_gen_buffer(void) size = full_size - qemu_real_host_page_size; /* Honor a command-line option limiting the size of the buffer. */ - if (size > tcg_ctx.code_gen_buffer_size) { - size = (((uintptr_t)buf + tcg_ctx.code_gen_buffer_size) + if (size > tcg_ctx->code_gen_buffer_size) { + size = (((uintptr_t)buf + tcg_ctx->code_gen_buffer_size) & qemu_real_host_page_mask) - (uintptr_t)buf; } - tcg_ctx.code_gen_buffer_size = size; + tcg_ctx->code_gen_buffer_size = size; #ifdef __mips__ if (cross_256mb(buf, size)) { buf = split_cross_256mb(buf, size); - size = tcg_ctx.code_gen_buffer_size; + size = tcg_ctx->code_gen_buffer_size; } #endif @@ -675,7 +676,7 @@ static inline void *alloc_code_gen_buffer(void) #elif defined(_WIN32) static inline void *alloc_code_gen_buffer(void) { - size_t size = tcg_ctx.code_gen_buffer_size; + size_t size = tcg_ctx->code_gen_buffer_size; void *buf1, *buf2; /* Perform the allocation in two steps, so that the guard page @@ -694,7 +695,7 @@ static inline void *alloc_code_gen_buffer(void) { int flags = MAP_PRIVATE | MAP_ANONYMOUS; uintptr_t start = 0; - size_t size = tcg_ctx.code_gen_buffer_size; + size_t size = tcg_ctx->code_gen_buffer_size; void *buf; /* Constrain the position of the buffer based on the host cpu. @@ -711,7 +712,7 @@ static inline void *alloc_code_gen_buffer(void) flags |= MAP_32BIT; /* Cannot expect to map more than 800MB in low memory. */ if (size > 800u * 1024 * 1024) { - tcg_ctx.code_gen_buffer_size = size = 800u * 1024 * 1024; + tcg_ctx->code_gen_buffer_size = size = 800u * 1024 * 1024; } # elif defined(__sparc__) start = 0x40000000ul; @@ -751,7 +752,7 @@ static inline void *alloc_code_gen_buffer(void) default: /* Split the original buffer. Free the smaller half. */ buf2 = split_cross_256mb(buf, size); - size2 = tcg_ctx.code_gen_buffer_size; + size2 = tcg_ctx->code_gen_buffer_size; if (buf == buf2) { munmap(buf + size2 + qemu_real_host_page_size, size - size2); } else { @@ -819,9 +820,9 @@ static gint tb_tc_cmp(gconstpointer ap, gconstpointer bp) static inline void code_gen_alloc(size_t tb_size) { - tcg_ctx.code_gen_buffer_size = size_code_gen_buffer(tb_size); - tcg_ctx.code_gen_buffer = alloc_code_gen_buffer(); - if (tcg_ctx.code_gen_buffer == NULL) { + tcg_ctx->code_gen_buffer_size = size_code_gen_buffer(tb_size); + tcg_ctx->code_gen_buffer = alloc_code_gen_buffer(); + if (tcg_ctx->code_gen_buffer == NULL) { fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } @@ -849,7 +850,7 @@ void tcg_exec_init(unsigned long tb_size) #if defined(CONFIG_SOFTMMU) /* There's no guest base to take into account, so go ahead and initialize the prologue now. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); #endif } @@ -865,7 +866,7 @@ static TranslationBlock *tb_alloc(target_ulong pc) assert_tb_locked(); - tb = tcg_tb_alloc(&tcg_ctx); + tb = tcg_tb_alloc(tcg_ctx); if (unlikely(tb == NULL)) { return NULL; } @@ -949,11 +950,11 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count) g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); printf("qemu: flush code_size=%td nb_tbs=%zu avg_tb_size=%zu\n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, + tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : 0); } - if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) - > tcg_ctx.code_gen_buffer_size) { + if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer) + > tcg_ctx->code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); } @@ -968,7 +969,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count) qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); - tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer; + tcg_ctx->code_gen_ptr = tcg_ctx->code_gen_buffer; /* XXX: flush processor icache at this point if cache flush is expensive */ atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); @@ -1316,44 +1317,44 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cpu_loop_exit(cpu); } - gen_code_buf = tcg_ctx.code_gen_ptr; + gen_code_buf = tcg_ctx->code_gen_ptr; tb->tc.ptr = gen_code_buf; tb->pc = pc; tb->cs_base = cs_base; tb->flags = flags; tb->cflags = cflags; tb->trace_vcpu_dstate = *cpu->trace_dstate; - tcg_ctx.tb_cflags = cflags; + tcg_ctx->tb_cflags = cflags; #ifdef CONFIG_PROFILER - tcg_ctx.tb_count1++; /* includes aborted translations because of + tcg_ctx->tb_count1++; /* includes aborted translations because of exceptions */ ti = profile_getclock(); #endif - tcg_func_start(&tcg_ctx); + tcg_func_start(tcg_ctx); - tcg_ctx.cpu = ENV_GET_CPU(env); + tcg_ctx->cpu = ENV_GET_CPU(env); gen_intermediate_code(cpu, tb); - tcg_ctx.cpu = NULL; + tcg_ctx->cpu = NULL; trace_translate_block(tb, tb->pc, tb->tc.ptr); /* generate machine code */ tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID; tb->jmp_reset_offset[1] = TB_JMP_RESET_OFFSET_INVALID; - tcg_ctx.tb_jmp_reset_offset = tb->jmp_reset_offset; + tcg_ctx->tb_jmp_reset_offset = tb->jmp_reset_offset; if (TCG_TARGET_HAS_direct_jump) { - tcg_ctx.tb_jmp_insn_offset = tb->jmp_target_arg; - tcg_ctx.tb_jmp_target_addr = NULL; + tcg_ctx->tb_jmp_insn_offset = tb->jmp_target_arg; + tcg_ctx->tb_jmp_target_addr = NULL; } else { - tcg_ctx.tb_jmp_insn_offset = NULL; - tcg_ctx.tb_jmp_target_addr = tb->jmp_target_arg; + tcg_ctx->tb_jmp_insn_offset = NULL; + tcg_ctx->tb_jmp_target_addr = tb->jmp_target_arg; } #ifdef CONFIG_PROFILER - tcg_ctx.tb_count++; - tcg_ctx.interm_time += profile_getclock() - ti; + tcg_ctx->tb_count++; + tcg_ctx->interm_time += profile_getclock() - ti; ti = profile_getclock(); #endif @@ -1362,7 +1363,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, the tcg optimization currently hidden inside tcg_gen_code. All that should be required is to flush the TBs, allocate a new TB, re-initialize it per above, and re-do the actual code generation. */ - gen_code_size = tcg_gen_code(&tcg_ctx, tb); + gen_code_size = tcg_gen_code(tcg_ctx, tb); if (unlikely(gen_code_size < 0)) { goto buffer_overflow; } @@ -1373,10 +1374,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->tc.size = gen_code_size; #ifdef CONFIG_PROFILER - tcg_ctx.code_time += profile_getclock() - ti; - tcg_ctx.code_in_len += tb->size; - tcg_ctx.code_out_len += gen_code_size; - tcg_ctx.search_out_len += search_size; + tcg_ctx->code_time += profile_getclock() - ti; + tcg_ctx->code_in_len += tb->size; + tcg_ctx->code_out_len += gen_code_size; + tcg_ctx->search_out_len += search_size; #endif #ifdef DEBUG_DISAS @@ -1384,8 +1385,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_in_addr_range(tb->pc)) { qemu_log_lock(); qemu_log("OUT: [size=%d]\n", gen_code_size); - if (tcg_ctx.data_gen_ptr) { - size_t code_size = tcg_ctx.data_gen_ptr - tb->tc.ptr; + if (tcg_ctx->data_gen_ptr) { + size_t code_size = tcg_ctx->data_gen_ptr - tb->tc.ptr; size_t data_size = gen_code_size - code_size; size_t i; @@ -1394,12 +1395,12 @@ TranslationBlock *tb_gen_code(CPUState *cpu, for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { if (sizeof(tcg_target_ulong) == 8) { qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", - (uintptr_t)tcg_ctx.data_gen_ptr + i, - *(uint64_t *)(tcg_ctx.data_gen_ptr + i)); + (uintptr_t)tcg_ctx->data_gen_ptr + i, + *(uint64_t *)(tcg_ctx->data_gen_ptr + i)); } else { qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", - (uintptr_t)tcg_ctx.data_gen_ptr + i, - *(uint32_t *)(tcg_ctx.data_gen_ptr + i)); + (uintptr_t)tcg_ctx->data_gen_ptr + i, + *(uint32_t *)(tcg_ctx->data_gen_ptr + i)); } } } else { @@ -1411,7 +1412,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } #endif - tcg_ctx.code_gen_ptr = (void *) + tcg_ctx->code_gen_ptr = (void *) ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, CODE_GEN_ALIGN); @@ -1940,8 +1941,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) * For avg host size we use the precise numbers from tb_tree_stats though. */ cpu_fprintf(f, "gen code size %td/%zd\n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, - tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); + tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, + tcg_ctx->code_gen_highwater - tcg_ctx->code_gen_buffer); cpu_fprintf(f, "TB count %zu\n", nb_tbs); cpu_fprintf(f, "TB avg target size %zu max=%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, diff --git a/bsd-user/main.c b/bsd-user/main.c index 836daac15c..392c0ed5fb 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -977,7 +977,7 @@ int main(int argc, char **argv) /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); /* build Task State */ memset(ts, 0, sizeof(TaskState)); diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 48b566c1c9..c58b0b2585 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -19,7 +19,7 @@ static inline void gen_tb_start(TranslationBlock *tb) count = tcg_temp_new_i32(); } - tcg_gen_ld_i32(count, tcg_ctx.tcg_env, + tcg_gen_ld_i32(count, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); if (tb_cflags(tb) & CF_USE_ICOUNT) { @@ -37,7 +37,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); if (tb_cflags(tb) & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, tcg_ctx.tcg_env, + tcg_gen_st16_i32(count, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low)); } @@ -56,13 +56,13 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns) tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); /* Terminate the linked list. */ - tcg_ctx.gen_op_buf[tcg_ctx.gen_op_buf[0].prev].next = 0; + tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].next = 0; } static inline void gen_io_start(void) { TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } @@ -70,7 +70,7 @@ static inline void gen_io_start(void) static inline void gen_io_end(void) { TCGv_i32 tmp = tcg_const_i32(0); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } diff --git a/linux-user/main.c b/linux-user/main.c index 0a2a0d75b3..8814906409 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4476,7 +4476,7 @@ int main(int argc, char **argv, char **envp) /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); #if defined(TARGET_I386) env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 53b8c036e2..f6247bf38d 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -127,7 +127,7 @@ void alpha_translate_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; for (i = 0; i < 31; i++) { cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env, diff --git a/target/arm/translate.c b/target/arm/translate.c index 397cc7afea..7873c03ae8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -82,7 +82,7 @@ void arm_translate_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new_i32(cpu_env, diff --git a/target/cris/translate.c b/target/cris/translate.c index 6774acc7af..6687b838d5 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3369,7 +3369,7 @@ void cris_initialize_tcg(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; cc_x = tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src = tcg_global_mem_new(cpu_env, diff --git a/target/cris/translate_v10.c b/target/cris/translate_v10.c index 4a0b485d8e..5d489203f4 100644 --- a/target/cris/translate_v10.c +++ b/target/cris/translate_v10.c @@ -1273,7 +1273,7 @@ void cris_initialize_crisv10_tcg(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; cc_x = tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src = tcg_global_mem_new(cpu_env, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 08b2c73291..9059812d4e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -127,7 +127,7 @@ void hppa_translate_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; TCGV_UNUSED(cpu_gr[0]); for (i = 1; i < 32; i++) { diff --git a/target/i386/translate.c b/target/i386/translate.c index 70ba0b2d5a..649004393d 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8368,7 +8368,7 @@ void tcg_x86_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; cpu_cc_op = tcg_global_mem_new_i32(cpu_env, offsetof(CPUX86State, cc_op), "cc_op"); cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst), diff --git a/target/lm32/translate.c b/target/lm32/translate.c index d4a2e00165..6707967a2c 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1209,7 +1209,7 @@ void lm32_translate_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d751faed7c..f6e902f2b6 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -70,7 +70,7 @@ void m68k_tcg_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; #define DEFO32(name, offset) \ QREG_##name = tcg_global_mem_new_i32(cpu_env, \ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c70a2d6644..22f8d6230b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1856,7 +1856,7 @@ void mb_tcg_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; env_debug = tcg_global_mem_new(cpu_env, offsetof(CPUMBState, debug), diff --git a/target/mips/translate.c b/target/mips/translate.c index aadffbec39..7dfa94ab26 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20455,7 +20455,7 @@ void mips_tcg_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; TCGV_UNUSED(cpu_gpr[0]); for (i = 1; i < 32; i++) diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 3f1e609028..59c70b5cef 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -102,7 +102,7 @@ void moxie_translate_init(void) }; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; cpu_pc = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMoxieState, pc), "$pc"); for (i = 0; i < 16; i++) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index d33e365892..b91fd206fb 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -948,7 +948,7 @@ void nios2_tcg_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; for (i = 0; i < NUM_CORE_REGS; i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 666d050650..b031f2db97 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -81,7 +81,7 @@ void openrisc_translate_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; cpu_sr = tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, sr), "sr"); cpu_dflag = tcg_global_mem_new_i32(cpu_env, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ac5b8ea9a5..0ad84a75e4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -86,7 +86,7 @@ void ppc_translate_init(void) size_t cpu_reg_names_size; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; p = cpu_reg_names; cpu_reg_names_size = sizeof(cpu_reg_names); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 241b708502..2bf6f48089 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -113,7 +113,7 @@ void s390x_translate_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; psw_addr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, psw.addr), "psw_addr"); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index f918bae978..c13be851ba 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -100,7 +100,7 @@ void sh4_translate_init(void) }; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; for (i = 0; i < 24; i++) { cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9dc41869a4..afef77976b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5912,7 +5912,7 @@ void sparc_tcg_init(void) unsigned int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; cpu_regwptr = tcg_global_mem_new_ptr(cpu_env, offsetof(CPUSPARCState, regwptr), diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index 5cd84f6b25..a744c38bb7 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2446,7 +2446,7 @@ void tilegx_tcg_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc"); for (i = 0; i < TILEGX_R_COUNT; i++) { cpu_regs[i] = tcg_global_mem_new_i64(cpu_env, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 042c0e69bc..590cbbee8b 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8882,7 +8882,7 @@ void tricore_tcg_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; /* reg init */ for (i = 0 ; i < 16 ; i++) { cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index d717de0335..070653e2d1 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -75,7 +75,7 @@ void uc32_translate_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; for (i = 0; i < 32; i++) { cpu_R[i] = tcg_global_mem_new_i32(cpu_env, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f62319eddd..ab96b77d88 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -222,7 +222,7 @@ void xtensa_translate_init(void) int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; + tcg_ctx->tcg_env = cpu_env; cpu_pc = tcg_global_mem_new_i32(cpu_env, offsetof(CPUXtensaState, pc), "pc"); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8c7668de60..ba603281d3 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -48,7 +48,7 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); static inline TCGOp *tcg_emit_op(TCGOpcode opc) { - TCGContext *ctx = &tcg_ctx; + TCGContext *ctx = tcg_ctx; int oi = ctx->gen_next_op_idx; int ni = oi + 1; int pi = oi - 1; @@ -121,7 +121,7 @@ void tcg_gen_op6(TCGOpcode opc, TCGArg a1, TCGArg a2, TCGArg a3, void tcg_gen_mb(TCGBar mb_type) { - if (tcg_ctx.tb_cflags & CF_PARALLEL) { + if (tcg_ctx->tb_cflags & CF_PARALLEL) { tcg_gen_op1(INDEX_op_mb, mb_type); } } @@ -2552,8 +2552,8 @@ void tcg_gen_goto_tb(unsigned idx) tcg_debug_assert(idx <= 1); #ifdef CONFIG_DEBUG_TCG /* Verify that we havn't seen this numbered exit before. */ - tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0); - tcg_ctx.goto_tb_issue_mask |= 1 << idx; + tcg_debug_assert((tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0); + tcg_ctx->goto_tb_issue_mask |= 1 << idx; #endif tcg_gen_op1i(INDEX_op_goto_tb, idx); } @@ -2562,7 +2562,7 @@ void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { TCGv_ptr ptr = tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); + gen_helper_lookup_tb_ptr(ptr, tcg_ctx->tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); tcg_temp_free_ptr(ptr); } else { @@ -2648,7 +2648,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop = tcg_canonicalize_memop(memop, 0, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); } @@ -2657,7 +2657,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 0, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } @@ -2676,7 +2676,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) } memop = tcg_canonicalize_memop(memop, 1, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); } @@ -2690,7 +2690,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) } memop = tcg_canonicalize_memop(memop, 1, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); } @@ -2780,7 +2780,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, { memop = tcg_canonicalize_memop(memop, 0, 0); - if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) { + if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { TCGv_i32 t1 = tcg_temp_new_i32(); TCGv_i32 t2 = tcg_temp_new_i32(); @@ -2806,11 +2806,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); #endif if (memop & MO_SIGN) { @@ -2824,7 +2824,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, { memop = tcg_canonicalize_memop(memop, 1, 0); - if (!(tcg_ctx.tb_cflags & CF_PARALLEL)) { + if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); @@ -2851,14 +2851,14 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop, idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(tcg_ctx->tcg_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following. */ tcg_gen_movi_i64(retv, 0); @@ -2914,11 +2914,11 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, tcg_ctx->tcg_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, tcg_ctx->tcg_env, addr, val); #endif if (memop & MO_SIGN) { @@ -2959,14 +2959,14 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, tcg_ctx->tcg_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, tcg_ctx->tcg_env, addr, val); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(tcg_ctx->tcg_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following. */ tcg_gen_movi_i64(ret, 0); @@ -3001,7 +3001,7 @@ static void * const table_##NAME[16] = { \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ { \ - if (tcg_ctx.tb_cflags & CF_PARALLEL) { \ + if (tcg_ctx->tb_cflags & CF_PARALLEL) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3011,7 +3011,7 @@ void tcg_gen_atomic_##NAME##_i32 \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ { \ - if (tcg_ctx.tb_cflags & CF_PARALLEL) { \ + if (tcg_ctx->tb_cflags & CF_PARALLEL) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ diff --git a/tcg/tcg.c b/tcg/tcg.c index 3a73912827..62f418ac8a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -243,7 +243,7 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr) TCGLabel *gen_new_label(void) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); *l = (TCGLabel){ @@ -382,6 +382,8 @@ void tcg_context_init(TCGContext *s) for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i]; } + + tcg_ctx = s; } /* @@ -522,7 +524,7 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; TCGTemp *t; if (tcg_regset_test_reg(s->reserved_regs, reg)) { @@ -534,7 +536,7 @@ TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name) TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; TCGTemp *t; if (tcg_regset_test_reg(s->reserved_regs, reg)) { @@ -547,7 +549,7 @@ TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name) TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, intptr_t offset, const char *name) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; TCGTemp *base_ts = tcgv_ptr_temp(base); TCGTemp *ts = tcg_global_alloc(s); int indirect_reg = 0, bigendian = 0; @@ -602,7 +604,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, static TCGTemp *tcg_temp_new_internal(TCGType type, int temp_local) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; TCGTemp *ts; int idx, k; @@ -659,7 +661,7 @@ TCGv_i64 tcg_temp_new_internal_i64(int temp_local) static void tcg_temp_free_internal(TCGTemp *ts) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; int k, idx; #if defined(CONFIG_DEBUG_TCG) @@ -723,13 +725,13 @@ TCGv_i64 tcg_const_local_i64(int64_t val) #if defined(CONFIG_DEBUG_TCG) void tcg_clear_temp_count(void) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; s->temps_in_use = 0; } int tcg_check_temp_count(void) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; if (s->temps_in_use) { /* Clear the count so that we don't give another * warning immediately next time around. @@ -969,7 +971,7 @@ bool tcg_op_supported(TCGOpcode op) and endian swap in tcg_reg_alloc_call(). */ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; int i, real_args, nb_rets, pi; unsigned sizemask, flags; TCGHelperInfo *info; @@ -2908,7 +2910,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifdef CONFIG_PROFILER void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; int64_t tb_count = s->tb_count; int64_t tb_div_count = tb_count ? tb_count : 1; int64_t tot = s->interm_time + s->code_time; diff --git a/tcg/tcg.h b/tcg/tcg.h index 76324c9ad6..17fd146557 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -688,12 +688,13 @@ struct TCGContext { target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; }; -extern TCGContext tcg_ctx; +extern TCGContext tcg_init_ctx; +extern TCGContext *tcg_ctx; static inline size_t temp_idx(TCGTemp *ts) { - ptrdiff_t n = ts - tcg_ctx.temps; - tcg_debug_assert(n >= 0 && n < tcg_ctx.nb_temps); + ptrdiff_t n = ts - tcg_ctx->temps; + tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); return n; } @@ -713,7 +714,7 @@ static inline TCGTemp *arg_temp(TCGArg a) static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) { uintptr_t o = (uintptr_t)v; - TCGTemp *t = (void *)&tcg_ctx + o; + TCGTemp *t = (void *)tcg_ctx + o; tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); return t; } @@ -746,7 +747,7 @@ static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) { (void)temp_idx(t); /* trigger embedded assert */ - return (TCGv_i32)((void *)t - (void *)&tcg_ctx); + return (TCGv_i32)((void *)t - (void *)tcg_ctx); } static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) @@ -773,13 +774,13 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { - tcg_ctx.gen_op_buf[op_idx].args[arg] = v; + tcg_ctx->gen_op_buf[op_idx].args[arg] = v; } /* The number of opcodes emitted so far. */ static inline int tcg_op_buf_count(void) { - return tcg_ctx.gen_next_op_idx; + return tcg_ctx->gen_next_op_idx; } /* Test for whether to terminate the TB for using too many opcodes. */ @@ -798,7 +799,7 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s); /* Called with tb_lock held. */ static inline void *tcg_malloc(int size) { - TCGContext *s = &tcg_ctx; + TCGContext *s = tcg_ctx; uint8_t *ptr, *ptr_end; /* ??? This is a weak placeholder for minimum malloc alignment. */ @@ -807,7 +808,7 @@ static inline void *tcg_malloc(int size) ptr = s->pool_cur; ptr_end = ptr + size; if (unlikely(ptr_end > s->pool_end)) { - return tcg_malloc_internal(&tcg_ctx, size); + return tcg_malloc_internal(tcg_ctx, size); } else { s->pool_cur = ptr_end; return ptr; @@ -1147,7 +1148,7 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); #else # define tcg_qemu_tb_exec(env, tb_ptr) \ - ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr) + ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr) #endif void tcg_register_jit(void *buf, size_t buf_size); -- cgit v1.2.3-55-g7522 From 26689780f838f6be13c3878b973ad4a83c0e8071 Mon Sep 17 00:00:00 2001 From: Emilio G. Cota Date: Tue, 4 Jul 2017 13:54:21 -0400 Subject: gen-icount: fold exitreq_label into TCGContext Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 7 +++---- tcg/tcg.h | 2 ++ 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'include/exec/gen-icount.h') diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index c58b0b2585..fe80176462 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -6,13 +6,12 @@ /* Helpers for instruction counting code generation. */ static int icount_start_insn_idx; -static TCGLabel *exitreq_label; static inline void gen_tb_start(TranslationBlock *tb) { TCGv_i32 count, imm; - exitreq_label = gen_new_label(); + tcg_ctx->exitreq_label = gen_new_label(); if (tb_cflags(tb) & CF_USE_ICOUNT) { count = tcg_temp_local_new_i32(); } else { @@ -34,7 +33,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_temp_free_i32(imm); } - tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); + tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_ctx->tcg_env, @@ -52,7 +51,7 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns) tcg_set_insn_param(icount_start_insn_idx, 1, num_insns); } - gen_set_label(exitreq_label); + gen_set_label(tcg_ctx->exitreq_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); /* Terminate the linked list. */ diff --git a/tcg/tcg.h b/tcg/tcg.h index 17fd146557..cca85b4d85 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -675,6 +675,8 @@ struct TCGContext { struct TCGLabelPoolData *pool_labels; #endif + TCGLabel *exitreq_label; + TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ -- cgit v1.2.3-55-g7522 From 1c2adb958fc07e5b3e81ed21b801c04a15f41f4f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 10 Oct 2017 14:34:37 -0700 Subject: tcg: Initialize cpu_env generically This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created by targets. Reviewed-by: Emilio G. Cota Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 10 ++++------ target/alpha/translate.c | 4 ---- target/arm/translate.c | 4 ---- target/arm/translate.h | 1 - target/cris/translate.c | 3 --- target/cris/translate_v10.c | 2 -- target/hppa/translate.c | 4 ---- target/i386/translate.c | 3 --- target/lm32/translate.c | 4 ---- target/m68k/translate.c | 5 ----- target/microblaze/translate.c | 4 ---- target/mips/translate.c | 4 ---- target/moxie/translate.c | 3 --- target/nios2/translate.c | 4 ---- target/openrisc/translate.c | 3 --- target/ppc/translate.c | 4 ---- target/s390x/translate.c | 6 ------ target/sh4/translate.c | 4 ---- target/sparc/translate.c | 4 ---- target/tilegx/translate.c | 3 --- target/tricore/translate.c | 4 ---- target/unicore32/translate.c | 4 ---- target/xtensa/translate.c | 3 --- tcg/tcg-op.c | 30 +++++++++++++++--------------- tcg/tcg.c | 32 ++++++++------------------------ tcg/tcg.h | 9 +-------- 26 files changed, 28 insertions(+), 133 deletions(-) (limited to 'include/exec/gen-icount.h') diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index fe80176462..049bba86e9 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -18,7 +18,7 @@ static inline void gen_tb_start(TranslationBlock *tb) count = tcg_temp_new_i32(); } - tcg_gen_ld_i32(count, tcg_ctx->tcg_env, + tcg_gen_ld_i32(count, cpu_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); if (tb_cflags(tb) & CF_USE_ICOUNT) { @@ -36,7 +36,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); if (tb_cflags(tb) & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, tcg_ctx->tcg_env, + tcg_gen_st16_i32(count, cpu_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low)); } @@ -61,16 +61,14 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns) static inline void gen_io_start(void) { TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, - -ENV_OFFSET + offsetof(CPUState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } static inline void gen_io_end(void) { TCGv_i32 tmp = tcg_const_i32(0); - tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, - -ENV_OFFSET + offsetof(CPUState, can_do_io)); + tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } diff --git a/target/alpha/translate.c b/target/alpha/translate.c index f6247bf38d..cfd63d5c1f 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -78,7 +78,6 @@ struct DisasContext { #define DISAS_PC_STALE DISAS_TARGET_2 /* global register indexes */ -static TCGv_env cpu_env; static TCGv cpu_std_ir[31]; static TCGv cpu_fir[31]; static TCGv cpu_pc; @@ -126,9 +125,6 @@ void alpha_translate_init(void) int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - for (i = 0; i < 31; i++) { cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUAlphaState, ir[i]), diff --git a/target/arm/translate.c b/target/arm/translate.c index 7873c03ae8..a252429e68 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -58,7 +58,6 @@ #define IS_USER(s) (s->user) #endif -TCGv_env cpu_env; /* We reuse the same 64-bit temporaries for efficiency. */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; static TCGv_i32 cpu_R[16]; @@ -81,9 +80,6 @@ void arm_translate_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, regs[i]), diff --git a/target/arm/translate.h b/target/arm/translate.h index 3c96aec956..410ba79c0d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -80,7 +80,6 @@ typedef struct DisasCompare { } DisasCompare; /* Share the TCG temporaries common between 32 and 64 bit modes. */ -extern TCGv_env cpu_env; extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_val; diff --git a/target/cris/translate.c b/target/cris/translate.c index 6687b838d5..aa95f6701a 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -66,7 +66,6 @@ #define CC_MASK_NZVC 0xf #define CC_MASK_RNZV 0x10e -static TCGv_env cpu_env; static TCGv cpu_R[16]; static TCGv cpu_PR[16]; static TCGv cc_x; @@ -3368,8 +3367,6 @@ void cris_initialize_tcg(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; cc_x = tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src = tcg_global_mem_new(cpu_env, diff --git a/target/cris/translate_v10.c b/target/cris/translate_v10.c index 5d489203f4..fce78825cc 100644 --- a/target/cris/translate_v10.c +++ b/target/cris/translate_v10.c @@ -1272,8 +1272,6 @@ void cris_initialize_crisv10_tcg(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; cc_x = tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src = tcg_global_mem_new(cpu_env, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9059812d4e..dbd4cd8615 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -83,7 +83,6 @@ typedef struct DisasInsn { } DisasInsn; /* global register indexes */ -static TCGv_env cpu_env; static TCGv cpu_gr[32]; static TCGv cpu_iaoq_f; static TCGv cpu_iaoq_b; @@ -126,9 +125,6 @@ void hppa_translate_init(void) int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - TCGV_UNUSED(cpu_gr[0]); for (i = 1; i < 32; i++) { cpu_gr[i] = tcg_global_mem_new(cpu_env, diff --git a/target/i386/translate.c b/target/i386/translate.c index 649004393d..7df9233ded 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -72,7 +72,6 @@ //#define MACRO_TEST 1 /* global register indexes */ -static TCGv_env cpu_env; static TCGv cpu_A0; static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT; static TCGv_i32 cpu_cc_op; @@ -8367,8 +8366,6 @@ void tcg_x86_init(void) }; int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; cpu_cc_op = tcg_global_mem_new_i32(cpu_env, offsetof(CPUX86State, cc_op), "cc_op"); cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst), diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 6707967a2c..02ad3edad3 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -53,7 +53,6 @@ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ -static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; static TCGv cpu_ie; @@ -1208,9 +1207,6 @@ void lm32_translate_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, regs[i]), diff --git a/target/m68k/translate.c b/target/m68k/translate.c index f6e902f2b6..e7eaf03e55 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -44,8 +44,6 @@ static TCGv_i32 cpu_halted; static TCGv_i32 cpu_exception_index; -static TCGv_env cpu_env; - static char cpu_reg_names[2 * 8 * 3 + 5 * 4]; static TCGv cpu_dregs[8]; static TCGv cpu_aregs[8]; @@ -69,9 +67,6 @@ void m68k_tcg_init(void) char *p; int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - #define DEFO32(name, offset) \ QREG_##name = tcg_global_mem_new_i32(cpu_env, \ offsetof(CPUM68KState, offset), #name); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 22f8d6230b..e51821d6bd 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -53,7 +53,6 @@ #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ static TCGv env_debug; -static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_SR[18]; static TCGv env_imm; @@ -1855,9 +1854,6 @@ void mb_tcg_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - env_debug = tcg_global_mem_new(cpu_env, offsetof(CPUMBState, debug), "debug0"); diff --git a/target/mips/translate.c b/target/mips/translate.c index 7dfa94ab26..82622c550e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1376,7 +1376,6 @@ enum { }; /* global register indices */ -static TCGv_env cpu_env; static TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget, bcond; @@ -20454,9 +20453,6 @@ void mips_tcg_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - TCGV_UNUSED(cpu_gpr[0]); for (i = 1; i < 32; i++) cpu_gpr[i] = tcg_global_mem_new(cpu_env, diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 59c70b5cef..28b405f0e4 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -56,7 +56,6 @@ enum { static TCGv cpu_pc; static TCGv cpu_gregs[16]; -static TCGv_env cpu_env; static TCGv cc_a, cc_b; #include "exec/gen-icount.h" @@ -101,8 +100,6 @@ void moxie_translate_init(void) "$r10", "$r11", "$r12", "$r13" }; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; cpu_pc = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMoxieState, pc), "$pc"); for (i = 0; i < 16; i++) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index b91fd206fb..b5aaf56e86 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -789,7 +789,6 @@ static const char * const regnames[] = { "rpc" }; -static TCGv_ptr cpu_env; static TCGv cpu_R[NUM_CORE_REGS]; #include "exec/gen-icount.h" @@ -947,9 +946,6 @@ void nios2_tcg_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - for (i = 0; i < NUM_CORE_REGS; i++) { cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index b031f2db97..c9cbd2319f 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -53,7 +53,6 @@ typedef struct DisasContext { bool singlestep_enabled; } DisasContext; -static TCGv_env cpu_env; static TCGv cpu_sr; static TCGv cpu_R[32]; static TCGv cpu_R0; @@ -80,8 +79,6 @@ void openrisc_translate_init(void) }; int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; cpu_sr = tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, sr), "sr"); cpu_dflag = tcg_global_mem_new_i32(cpu_env, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0ad84a75e4..e7e4983cbf 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -51,7 +51,6 @@ /* Code translation helpers */ /* global register indexes */ -static TCGv_env cpu_env; static char cpu_reg_names[10*3 + 22*4 /* GPR */ + 10*4 + 22*5 /* SPE GPRh */ + 10*4 + 22*5 /* FPR */ @@ -85,9 +84,6 @@ void ppc_translate_init(void) char* p; size_t cpu_reg_names_size; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - p = cpu_reg_names; cpu_reg_names_size = sizeof(cpu_reg_names); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 2bf6f48089..55db8f3446 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -37,10 +37,6 @@ #include "qemu/log.h" #include "qemu/host-utils.h" #include "exec/cpu_ldst.h" - -/* global register indexes */ -static TCGv_env cpu_env; - #include "exec/gen-icount.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -112,8 +108,6 @@ void s390x_translate_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; psw_addr = tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, psw.addr), "psw_addr"); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index c13be851ba..c98f8d31e3 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -65,7 +65,6 @@ enum { }; /* global register indexes */ -static TCGv_env cpu_env; static TCGv cpu_gregs[32]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; @@ -99,9 +98,6 @@ void sh4_translate_init(void) "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", }; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - for (i = 0; i < 24; i++) { cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUSH4State, gregs[i]), diff --git a/target/sparc/translate.c b/target/sparc/translate.c index afef77976b..d5e866fe0d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -41,7 +41,6 @@ according to jump_pc[T2] */ /* global register indexes */ -static TCGv_env cpu_env; static TCGv_ptr cpu_regwptr; static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; static TCGv_i32 cpu_cc_op; @@ -5911,9 +5910,6 @@ void sparc_tcg_init(void) unsigned int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - cpu_regwptr = tcg_global_mem_new_ptr(cpu_env, offsetof(CPUSPARCState, regwptr), "regwptr"); diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index a744c38bb7..d55549dabc 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -33,7 +33,6 @@ #define FMT64X "%016" PRIx64 -static TCGv_env cpu_env; static TCGv cpu_pc; static TCGv cpu_regs[TILEGX_R_COUNT]; @@ -2445,8 +2444,6 @@ void tilegx_tcg_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc"); for (i = 0; i < TILEGX_R_COUNT; i++) { cpu_regs[i] = tcg_global_mem_new_i64(cpu_env, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 590cbbee8b..18102e54cb 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -47,8 +47,6 @@ static TCGv cpu_PSW_V; static TCGv cpu_PSW_SV; static TCGv cpu_PSW_AV; static TCGv cpu_PSW_SAV; -/* CPU env */ -static TCGv_env cpu_env; #include "exec/gen-icount.h" @@ -8881,8 +8879,6 @@ void tricore_tcg_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; /* reg init */ for (i = 0 ; i < 16 ; i++) { cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 070653e2d1..de2a7ceee7 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -54,7 +54,6 @@ typedef struct DisasContext { conditional executions state has been updated. */ #define DISAS_SYSCALL DISAS_TARGET_3 -static TCGv_env cpu_env; static TCGv_i32 cpu_R[32]; /* FIXME: These should be removed. */ @@ -74,9 +73,6 @@ void uc32_translate_init(void) { int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; - for (i = 0; i < 32; i++) { cpu_R[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUUniCore32State, regs[i]), regnames[i]); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index ab96b77d88..32c4159949 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -77,7 +77,6 @@ typedef struct DisasContext { unsigned cpenable; } DisasContext; -static TCGv_env cpu_env; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; @@ -221,8 +220,6 @@ void xtensa_translate_init(void) }; int i; - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx->tcg_env = cpu_env; cpu_pc = tcg_global_mem_new_i32(cpu_env, offsetof(CPUXtensaState, pc), "pc"); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ba603281d3..3cad30b1f2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2562,7 +2562,7 @@ void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { TCGv_ptr ptr = tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx->tcg_env); + gen_helper_lookup_tb_ptr(ptr, cpu_env); tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); tcg_temp_free_ptr(ptr); } else { @@ -2648,7 +2648,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop = tcg_canonicalize_memop(memop, 0, 0); - trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); } @@ -2657,7 +2657,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 0, 1); - trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } @@ -2676,7 +2676,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) } memop = tcg_canonicalize_memop(memop, 1, 0); - trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); } @@ -2690,7 +2690,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) } memop = tcg_canonicalize_memop(memop, 1, 1); - trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); } @@ -2806,11 +2806,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); + gen(retv, cpu_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); + gen(retv, cpu_env, addr, cmpv, newv); #endif if (memop & MO_SIGN) { @@ -2851,14 +2851,14 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop, idx)); - gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); + gen(retv, cpu_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); + gen(retv, cpu_env, addr, cmpv, newv); #endif #else - gen_helper_exit_atomic(tcg_ctx->tcg_env); + gen_helper_exit_atomic(cpu_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following. */ tcg_gen_movi_i64(retv, 0); @@ -2914,11 +2914,11 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(ret, tcg_ctx->tcg_env, addr, val, oi); + gen(ret, cpu_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx->tcg_env, addr, val); + gen(ret, cpu_env, addr, val); #endif if (memop & MO_SIGN) { @@ -2959,14 +2959,14 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx)); - gen(ret, tcg_ctx->tcg_env, addr, val, oi); + gen(ret, cpu_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx->tcg_env, addr, val); + gen(ret, cpu_env, addr, val); #endif #else - gen_helper_exit_atomic(tcg_ctx->tcg_env); + gen_helper_exit_atomic(cpu_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following. */ tcg_gen_movi_i64(ret, 0); diff --git a/tcg/tcg.c b/tcg/tcg.c index 5574317736..683ff4abb7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -121,6 +121,7 @@ static bool tcg_out_ldst_finalize(TCGContext *s); static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; +TCGv_env cpu_env = 0; /* * We divide code_gen_buffer into equally-sized "regions" that TCG threads @@ -657,6 +658,8 @@ static GHashTable *helper_table; static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; static void process_op_defs(TCGContext *s); +static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, + TCGReg reg, const char *name); void tcg_context_init(TCGContext *s) { @@ -664,6 +667,7 @@ void tcg_context_init(TCGContext *s) TCGOpDef *def; TCGArgConstraint *args_ct; int *sorted_args; + TCGTemp *ts; memset(s, 0, sizeof(*s)); s->nb_globals = 0; @@ -729,6 +733,10 @@ void tcg_context_init(TCGContext *s) #else tcg_ctxs = g_new(TCGContext *, max_cpus); #endif + + tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); + ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); + cpu_env = temp_tcgv_ptr(ts); } /* @@ -871,30 +879,6 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); } -TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name) -{ - TCGContext *s = tcg_ctx; - TCGTemp *t; - - if (tcg_regset_test_reg(s->reserved_regs, reg)) { - tcg_abort(); - } - t = tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name); - return temp_tcgv_i32(t); -} - -TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name) -{ - TCGContext *s = tcg_ctx; - TCGTemp *t; - - if (tcg_regset_test_reg(s->reserved_regs, reg)) { - tcg_abort(); - } - t = tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name); - return temp_tcgv_i64(t); -} - TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, intptr_t offset, const char *name) { diff --git a/tcg/tcg.h b/tcg/tcg.h index 3d022e448b..cb7b329876 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -669,7 +669,6 @@ struct TCGContext { /* Track which vCPU triggers events */ CPUState *cpu; /* *_trans */ - TCGv_env tcg_env; /* *_exec */ /* These structures are private to tcg-target.inc.c. */ #ifdef TCG_TARGET_NEED_LDST_LABELS @@ -696,6 +695,7 @@ struct TCGContext { extern TCGContext tcg_init_ctx; extern __thread TCGContext *tcg_ctx; +extern TCGv_env cpu_env; static inline size_t temp_idx(TCGTemp *ts) { @@ -839,9 +839,6 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); -TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); -TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); - TCGv_i32 tcg_temp_new_internal_i32(int temp_local); TCGv_i64 tcg_temp_new_internal_i64(int temp_local); @@ -960,8 +957,6 @@ static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i32 n) { return (TCGv_ptr)n; } static inline TCGv_i32 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i32)n; } #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V))) -#define tcg_global_reg_new_ptr(R, N) \ - TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N))) #define tcg_global_mem_new_ptr(R, O, N) \ TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N))) #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32()) @@ -971,8 +966,6 @@ static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i64 n) { return (TCGv_ptr)n; } static inline TCGv_i64 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i64)n; } #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V))) -#define tcg_global_reg_new_ptr(R, N) \ - TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N))) #define tcg_global_mem_new_ptr(R, O, N) \ TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N))) #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64()) -- cgit v1.2.3-55-g7522