From cc05c43ad942165ecc6ffd39e41991bee43af044 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:23 +0100 Subject: memory: Define API for MemoryRegionOps to take attrs and return status Define an API so that devices can register MemoryRegionOps whose read and write callback functions are passed an arbitrary pointer to some transaction attributes and can return a success-or-failure status code. This will allow us to model devices which: * behave differently for ARM Secure/NonSecure memory accesses * behave differently for privileged/unprivileged accesses * may return a transaction failure (causing a guest exception) for erroneous accesses This patch defines the new API and plumbs the attributes parameter through to the memory.c public level functions io_mem_read() and io_mem_write(), where it is currently dummied out. The success/failure response indication is also propagated out to io_mem_read() and io_mem_write(), which retain the old-style boolean true-for-error return. Signed-off-by: Peter Maydell Acked-by: Paolo Bonzini Reviewed-by: Alex Bennée --- include/exec/memory.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include/exec/memory.h') diff --git a/include/exec/memory.h b/include/exec/memory.h index 06ffa1d185..703d9e5f8f 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -28,6 +28,7 @@ #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif +#include "exec/memattrs.h" #include "qemu/queue.h" #include "qemu/int128.h" #include "qemu/notify.h" @@ -68,6 +69,16 @@ struct IOMMUTLBEntry { IOMMUAccessFlags perm; }; +/* New-style MMIO accessors can indicate that the transaction failed. + * A zero (MEMTX_OK) response means success; anything else is a failure + * of some kind. The memory subsystem will bitwise-OR together results + * if it is synthesizing an operation from multiple smaller accesses. + */ +#define MEMTX_OK 0 +#define MEMTX_ERROR (1U << 0) /* device returned an error */ +#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ +typedef uint32_t MemTxResult; + /* * Memory region callbacks */ @@ -84,6 +95,17 @@ struct MemoryRegionOps { uint64_t data, unsigned size); + MemTxResult (*read_with_attrs)(void *opaque, + hwaddr addr, + uint64_t *data, + unsigned size, + MemTxAttrs attrs); + MemTxResult (*write_with_attrs)(void *opaque, + hwaddr addr, + uint64_t data, + unsigned size, + MemTxAttrs attrs); + enum device_endian endianness; /* Guest-visible constraints: */ struct { -- cgit v1.2.3-55-g7522 From 3b6434953934e6d4a776ed426d8c6d6badee176f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:23 +0100 Subject: memory: Replace io_mem_read/write with memory_region_dispatch_read/write Rather than retaining io_mem_read/write as simple wrappers around the memory_region_dispatch_read/write functions, make the latter public and change all the callers to use them, since we need to touch all the callsites anyway to add MemTxAttrs and MemTxResult support. Delete io_mem_read and io_mem_write entirely. (All the callers currently pass MEMTXATTRS_UNSPECIFIED and convert the return value back to bool or ignore it.) Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée --- exec.c | 47 +++++++++++++++++++++++++++++++---------------- hw/s390x/s390-pci-inst.c | 10 +++++++--- hw/vfio/pci.c | 18 ++++++++++++------ include/exec/exec-all.h | 4 ---- include/exec/memory.h | 31 +++++++++++++++++++++++++++++++ memory.c | 33 ++++++++++----------------------- softmmu_template.h | 6 ++++-- 7 files changed, 95 insertions(+), 54 deletions(-) (limited to 'include/exec/memory.h') diff --git a/exec.c b/exec.c index 874ecfc2c6..34dafd2e36 100644 --- a/exec.c +++ b/exec.c @@ -2312,7 +2312,8 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, uint64_t val; hwaddr addr1; MemoryRegion *mr; - bool error = false; + MemTxResult result = MEMTX_OK; + MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; while (len > 0) { l = len; @@ -2327,22 +2328,26 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, case 8: /* 64 bit write access */ val = ldq_p(buf); - error |= io_mem_write(mr, addr1, val, 8); + result |= memory_region_dispatch_write(mr, addr1, val, 8, + attrs); break; case 4: /* 32 bit write access */ val = ldl_p(buf); - error |= io_mem_write(mr, addr1, val, 4); + result |= memory_region_dispatch_write(mr, addr1, val, 4, + attrs); break; case 2: /* 16 bit write access */ val = lduw_p(buf); - error |= io_mem_write(mr, addr1, val, 2); + result |= memory_region_dispatch_write(mr, addr1, val, 2, + attrs); break; case 1: /* 8 bit write access */ val = ldub_p(buf); - error |= io_mem_write(mr, addr1, val, 1); + result |= memory_region_dispatch_write(mr, addr1, val, 1, + attrs); break; default: abort(); @@ -2361,22 +2366,26 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, switch (l) { case 8: /* 64 bit read access */ - error |= io_mem_read(mr, addr1, &val, 8); + result |= memory_region_dispatch_read(mr, addr1, &val, 8, + attrs); stq_p(buf, val); break; case 4: /* 32 bit read access */ - error |= io_mem_read(mr, addr1, &val, 4); + result |= memory_region_dispatch_read(mr, addr1, &val, 4, + attrs); stl_p(buf, val); break; case 2: /* 16 bit read access */ - error |= io_mem_read(mr, addr1, &val, 2); + result |= memory_region_dispatch_read(mr, addr1, &val, 2, + attrs); stw_p(buf, val); break; case 1: /* 8 bit read access */ - error |= io_mem_read(mr, addr1, &val, 1); + result |= memory_region_dispatch_read(mr, addr1, &val, 1, + attrs); stb_p(buf, val); break; default: @@ -2393,7 +2402,7 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, addr += l; } - return error; + return result; } bool address_space_write(AddressSpace *as, hwaddr addr, @@ -2669,7 +2678,8 @@ static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr, mr = address_space_translate(as, addr, &addr1, &l, false); if (l < 4 || !memory_access_is_direct(mr, false)) { /* I/O case */ - io_mem_read(mr, addr1, &val, 4); + memory_region_dispatch_read(mr, addr1, &val, 4, + MEMTXATTRS_UNSPECIFIED); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap32(val); @@ -2728,7 +2738,8 @@ static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr, false); if (l < 8 || !memory_access_is_direct(mr, false)) { /* I/O case */ - io_mem_read(mr, addr1, &val, 8); + memory_region_dispatch_read(mr, addr1, &val, 8, + MEMTXATTRS_UNSPECIFIED); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap64(val); @@ -2795,7 +2806,8 @@ static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr, false); if (l < 2 || !memory_access_is_direct(mr, false)) { /* I/O case */ - io_mem_read(mr, addr1, &val, 2); + memory_region_dispatch_read(mr, addr1, &val, 2, + MEMTXATTRS_UNSPECIFIED); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap16(val); @@ -2853,7 +2865,8 @@ void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) mr = address_space_translate(as, addr, &addr1, &l, true); if (l < 4 || !memory_access_is_direct(mr, true)) { - io_mem_write(mr, addr1, val, 4); + memory_region_dispatch_write(mr, addr1, val, 4, + MEMTXATTRS_UNSPECIFIED); } else { addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; ptr = qemu_get_ram_ptr(addr1); @@ -2892,7 +2905,8 @@ static inline void stl_phys_internal(AddressSpace *as, val = bswap32(val); } #endif - io_mem_write(mr, addr1, val, 4); + memory_region_dispatch_write(mr, addr1, val, 4, + MEMTXATTRS_UNSPECIFIED); } else { /* RAM case */ addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; @@ -2955,7 +2969,8 @@ static inline void stw_phys_internal(AddressSpace *as, val = bswap16(val); } #endif - io_mem_write(mr, addr1, val, 2); + memory_region_dispatch_write(mr, addr1, val, 2, + MEMTXATTRS_UNSPECIFIED); } else { /* RAM case */ addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 08d8aa6b4b..8f7288fadf 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -331,7 +331,8 @@ int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2) return 0; } MemoryRegion *mr = pbdev->pdev->io_regions[pcias].memory; - io_mem_read(mr, offset, &data, len); + memory_region_dispatch_read(mr, offset, &data, len, + MEMTXATTRS_UNSPECIFIED); } else if (pcias == 15) { if ((4 - (offset & 0x3)) < len) { program_interrupt(env, PGM_OPERAND, 4); @@ -456,7 +457,8 @@ int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2) mr = pbdev->pdev->io_regions[pcias].memory; } - io_mem_write(mr, offset, data, len); + memory_region_dispatch_write(mr, offset, data, len, + MEMTXATTRS_UNSPECIFIED); } else if (pcias == 15) { if ((4 - (offset & 0x3)) < len) { program_interrupt(env, PGM_OPERAND, 4); @@ -606,7 +608,9 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr) } for (i = 0; i < len / 8; i++) { - io_mem_write(mr, env->regs[r3] + i * 8, ldq_p(buffer + i * 8), 8); + memory_region_dispatch_write(mr, env->regs[r3] + i * 8, + ldq_p(buffer + i * 8), 8, + MEMTXATTRS_UNSPECIFIED); } setcc(cpu, ZPCI_PCI_LS_OK); diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 6b80539c1f..cd15b20990 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1531,9 +1531,12 @@ static uint64_t vfio_rtl8168_window_quirk_read(void *opaque, return 0; } - io_mem_read(&vdev->pdev.msix_table_mmio, - (hwaddr)(quirk->data.address_match & 0xfff), - &val, size); + memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, + (hwaddr)(quirk->data.address_match + & 0xfff), + &val, + size, + MEMTXATTRS_UNSPECIFIED); return val; } } @@ -1561,9 +1564,12 @@ static void vfio_rtl8168_window_quirk_write(void *opaque, hwaddr addr, memory_region_name(&quirk->mem), vdev->vbasedev.name); - io_mem_write(&vdev->pdev.msix_table_mmio, - (hwaddr)(quirk->data.address_match & 0xfff), - data, size); + memory_region_dispatch_write(&vdev->pdev.msix_table_mmio, + (hwaddr)(quirk->data.address_match + & 0xfff), + data, + size, + MEMTXATTRS_UNSPECIFIED); } quirk->data.flags = 1; diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 8eb0db3910..ff1bc3e4c1 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -341,10 +341,6 @@ void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)); struct MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index); -bool io_mem_read(struct MemoryRegion *mr, hwaddr addr, - uint64_t *pvalue, unsigned size); -bool io_mem_write(struct MemoryRegion *mr, hwaddr addr, - uint64_t value, unsigned size); void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr); diff --git a/include/exec/memory.h b/include/exec/memory.h index 703d9e5f8f..970a3a9b1e 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1052,6 +1052,37 @@ void memory_global_dirty_log_stop(void); void mtree_info(fprintf_function mon_printf, void *f); +/** + * memory_region_dispatch_read: perform a read directly to the specified + * MemoryRegion. + * + * @mr: #MemoryRegion to access + * @addr: address within that region + * @pval: pointer to uint64_t which the data is written to + * @size: size of the access in bytes + * @attrs: memory transaction attributes to use for the access + */ +MemTxResult memory_region_dispatch_read(MemoryRegion *mr, + hwaddr addr, + uint64_t *pval, + unsigned size, + MemTxAttrs attrs); +/** + * memory_region_dispatch_write: perform a write directly to the specified + * MemoryRegion. + * + * @mr: #MemoryRegion to access + * @addr: address within that region + * @data: data to write + * @size: size of the access in bytes + * @attrs: memory transaction attributes to use for the access + */ +MemTxResult memory_region_dispatch_write(MemoryRegion *mr, + hwaddr addr, + uint64_t data, + unsigned size, + MemTxAttrs attrs); + /** * address_space_init: initializes an address space * diff --git a/memory.c b/memory.c index 9bb5674bb9..a403c86b22 100644 --- a/memory.c +++ b/memory.c @@ -1131,11 +1131,11 @@ static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr, } } -static MemTxResult memory_region_dispatch_read(MemoryRegion *mr, - hwaddr addr, - uint64_t *pval, - unsigned size, - MemTxAttrs attrs) +MemTxResult memory_region_dispatch_read(MemoryRegion *mr, + hwaddr addr, + uint64_t *pval, + unsigned size, + MemTxAttrs attrs) { MemTxResult r; @@ -1149,11 +1149,11 @@ static MemTxResult memory_region_dispatch_read(MemoryRegion *mr, return r; } -static MemTxResult memory_region_dispatch_write(MemoryRegion *mr, - hwaddr addr, - uint64_t data, - unsigned size, - MemTxAttrs attrs) +MemTxResult memory_region_dispatch_write(MemoryRegion *mr, + hwaddr addr, + uint64_t data, + unsigned size, + MemTxAttrs attrs) { if (!memory_region_access_valid(mr, addr, size, true)) { unassigned_mem_write(mr, addr, data, size); @@ -2063,19 +2063,6 @@ void address_space_destroy(AddressSpace *as) call_rcu(as, do_address_space_destroy, rcu); } -bool io_mem_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, unsigned size) -{ - return memory_region_dispatch_read(mr, addr, pval, size, - MEMTXATTRS_UNSPECIFIED); -} - -bool io_mem_write(MemoryRegion *mr, hwaddr addr, - uint64_t val, unsigned size) -{ - return memory_region_dispatch_write(mr, addr, val, size, - MEMTXATTRS_UNSPECIFIED); -} - typedef struct MemoryRegionList MemoryRegionList; struct MemoryRegionList { diff --git a/softmmu_template.h b/softmmu_template.h index 0e3dd35fe1..9c1d53e2e4 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -158,7 +158,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, } cpu->mem_io_vaddr = addr; - io_mem_read(mr, physaddr, &val, 1 << SHIFT); + memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT, + MEMTXATTRS_UNSPECIFIED); return val; } #endif @@ -378,7 +379,8 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, cpu->mem_io_vaddr = addr; cpu->mem_io_pc = retaddr; - io_mem_write(mr, physaddr, val, 1 << SHIFT); + memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT, + MEMTXATTRS_UNSPECIFIED); } void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, -- cgit v1.2.3-55-g7522 From 5c9eb0286c819c1836220a32f2e1a7b5004ac79a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:24 +0100 Subject: exec.c: Make address_space_rw take transaction attributes Make address_space_rw take transaction attributes, rather than always using the 'unspecified' attributes. Signed-off-by: Peter Maydell Reviewed-by: Paolo Bonzini Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée --- dma-helpers.c | 3 ++- exec.c | 51 ++++++++++++++++++++++++++---------------------- hw/mips/mips_jazz.c | 6 ++++-- hw/pci-host/prep.c | 6 ++++-- include/exec/memory.h | 31 ++++++++++++++++++----------- include/sysemu/dma.h | 3 ++- ioport.c | 16 +++++++++------ kvm-all.c | 3 ++- scripts/coverity-model.c | 8 +++++--- 9 files changed, 77 insertions(+), 50 deletions(-) (limited to 'include/exec/memory.h') diff --git a/dma-helpers.c b/dma-helpers.c index 6918572e18..33b1983b25 100644 --- a/dma-helpers.c +++ b/dma-helpers.c @@ -28,7 +28,8 @@ int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len) memset(fillbuf, c, FILLBUF_SIZE); while (len > 0) { l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE; - error |= address_space_rw(as, addr, fillbuf, l, true); + error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, + fillbuf, l, true); len -= l; addr += l; } diff --git a/exec.c b/exec.c index bba6f26e5c..9811a9cbc0 100644 --- a/exec.c +++ b/exec.c @@ -1946,13 +1946,16 @@ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, { subpage_t *subpage = opaque; uint8_t buf[8]; + MemTxResult res; #if defined(DEBUG_SUBPAGE) printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, subpage, len, addr); #endif - if (address_space_read(subpage->as, addr + subpage->base, buf, len)) { - return MEMTX_DECODE_ERROR; + res = address_space_read(subpage->as, addr + subpage->base, + attrs, buf, len); + if (res) { + return res; } switch (len) { case 1: @@ -1999,10 +2002,8 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr, default: abort(); } - if (address_space_write(subpage->as, addr + subpage->base, buf, len)) { - return MEMTX_DECODE_ERROR; - } - return MEMTX_OK; + return address_space_write(subpage->as, addr + subpage->base, + attrs, buf, len); } static bool subpage_accepts(void *opaque, hwaddr addr, @@ -2313,8 +2314,8 @@ static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) return l; } -bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, - int len, bool is_write) +MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + uint8_t *buf, int len, bool is_write) { hwaddr l; uint8_t *ptr; @@ -2322,7 +2323,6 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, hwaddr addr1; MemoryRegion *mr; MemTxResult result = MEMTX_OK; - MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; while (len > 0) { l = len; @@ -2414,22 +2414,24 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, return result; } -bool address_space_write(AddressSpace *as, hwaddr addr, - const uint8_t *buf, int len) +MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + const uint8_t *buf, int len) { - return address_space_rw(as, addr, (uint8_t *)buf, len, true); + return address_space_rw(as, addr, attrs, (uint8_t *)buf, len, true); } -bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len) +MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + uint8_t *buf, int len) { - return address_space_rw(as, addr, buf, len, false); + return address_space_rw(as, addr, attrs, buf, len, false); } void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, int len, int is_write) { - address_space_rw(&address_space_memory, addr, buf, len, is_write); + address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, + buf, len, is_write); } enum write_rom_type { @@ -2600,7 +2602,8 @@ void *address_space_map(AddressSpace *as, memory_region_ref(mr); bounce.mr = mr; if (!is_write) { - address_space_read(as, addr, bounce.buffer, l); + address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED, + bounce.buffer, l); } *plen = l; @@ -2653,7 +2656,8 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, return; } if (is_write) { - address_space_write(as, bounce.addr, bounce.buffer, access_len); + address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, + bounce.buffer, access_len); } qemu_vfree(bounce.buffer); bounce.buffer = NULL; @@ -2797,7 +2801,7 @@ uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr) uint32_t ldub_phys(AddressSpace *as, hwaddr addr) { uint8_t val; - address_space_rw(as, addr, &val, 1, 0); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &val, 1, 0); return val; } @@ -2954,7 +2958,7 @@ void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val) { uint8_t v = val; - address_space_rw(as, addr, &v, 1, 1); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &v, 1, 1); } /* warning: addr must be aligned */ @@ -3018,19 +3022,19 @@ void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val) { val = tswap64(val); - address_space_rw(as, addr, (void *) &val, 8, 1); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); } void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val) { val = cpu_to_le64(val); - address_space_rw(as, addr, (void *) &val, 8, 1); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); } void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val) { val = cpu_to_be64(val); - address_space_rw(as, addr, (void *) &val, 8, 1); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); } /* virtual memory access for debug (includes writing to ROM) */ @@ -3054,7 +3058,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, if (is_write) { cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l); } else { - address_space_rw(cpu->as, phys_addr, buf, l, 0); + address_space_rw(cpu->as, phys_addr, MEMTXATTRS_UNSPECIFIED, + buf, l, 0); } len -= l; buf += l; diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 07f3c270d4..2c153e092f 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -61,7 +61,8 @@ static void main_cpu_reset(void *opaque) static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) { uint8_t val; - address_space_read(&address_space_memory, 0x90000071, &val, 1); + address_space_read(&address_space_memory, 0x90000071, + MEMTXATTRS_UNSPECIFIED, &val, 1); return val; } @@ -69,7 +70,8 @@ static void rtc_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { uint8_t buf = val & 0xff; - address_space_write(&address_space_memory, 0x90000071, &buf, 1); + address_space_write(&address_space_memory, 0x90000071, + MEMTXATTRS_UNSPECIFIED, &buf, 1); } static const MemoryRegionOps rtc_ops = { diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 6cea6ffebb..c63f45d217 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -140,7 +140,8 @@ static uint64_t raven_io_read(void *opaque, hwaddr addr, uint8_t buf[4]; addr = raven_io_address(s, addr); - address_space_read(&s->pci_io_as, addr + 0x80000000, buf, size); + address_space_read(&s->pci_io_as, addr + 0x80000000, + MEMTXATTRS_UNSPECIFIED, buf, size); if (size == 1) { return buf[0]; @@ -171,7 +172,8 @@ static void raven_io_write(void *opaque, hwaddr addr, g_assert_not_reached(); } - address_space_write(&s->pci_io_as, addr + 0x80000000, buf, size); + address_space_write(&s->pci_io_as, addr + 0x80000000, + MEMTXATTRS_UNSPECIFIED, buf, size); } static const MemoryRegionOps raven_io_ops = { diff --git a/include/exec/memory.h b/include/exec/memory.h index 970a3a9b1e..cafd590b92 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1108,41 +1108,50 @@ void address_space_destroy(AddressSpace *as); /** * address_space_rw: read from or write to an address space. * - * Return true if the operation hit any unassigned memory or encountered an - * IOMMU fault. + * Return a MemTxResult indicating whether the operation succeeded + * or failed (eg unassigned memory, device rejected the transaction, + * IOMMU fault). * * @as: #AddressSpace to be accessed * @addr: address within that address space + * @attrs: memory transaction attributes * @buf: buffer with the data transferred * @is_write: indicates the transfer direction */ -bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, - int len, bool is_write); +MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, uint8_t *buf, + int len, bool is_write); /** * address_space_write: write to address space. * - * Return true if the operation hit any unassigned memory or encountered an - * IOMMU fault. + * Return a MemTxResult indicating whether the operation succeeded + * or failed (eg unassigned memory, device rejected the transaction, + * IOMMU fault). * * @as: #AddressSpace to be accessed * @addr: address within that address space + * @attrs: memory transaction attributes * @buf: buffer with the data transferred */ -bool address_space_write(AddressSpace *as, hwaddr addr, - const uint8_t *buf, int len); +MemTxResult address_space_write(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, + const uint8_t *buf, int len); /** * address_space_read: read from an address space. * - * Return true if the operation hit any unassigned memory or encountered an - * IOMMU fault. + * Return a MemTxResult indicating whether the operation succeeded + * or failed (eg unassigned memory, device rejected the transaction, + * IOMMU fault). * * @as: #AddressSpace to be accessed * @addr: address within that address space + * @attrs: memory transaction attributes * @buf: buffer with the data transferred */ -bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len); +MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + uint8_t *buf, int len); /* address_space_translate: translate an address range into an address space * into a MemoryRegion and an address range into that section diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index 3f2f4c89e3..efa8b9993a 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -88,7 +88,8 @@ static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr, void *buf, dma_addr_t len, DMADirection dir) { - return address_space_rw(as, addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE); + return (bool)address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, + buf, len, dir == DMA_DIRECTION_FROM_DEVICE); } static inline int dma_memory_read_relaxed(AddressSpace *as, dma_addr_t addr, diff --git a/ioport.c b/ioport.c index 783a3ae675..b345bd9abe 100644 --- a/ioport.c +++ b/ioport.c @@ -64,7 +64,8 @@ void cpu_outb(pio_addr_t addr, uint8_t val) { LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); trace_cpu_out(addr, val); - address_space_write(&address_space_io, addr, &val, 1); + address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + &val, 1); } void cpu_outw(pio_addr_t addr, uint16_t val) @@ -74,7 +75,8 @@ void cpu_outw(pio_addr_t addr, uint16_t val) LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); trace_cpu_out(addr, val); stw_p(buf, val); - address_space_write(&address_space_io, addr, buf, 2); + address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + buf, 2); } void cpu_outl(pio_addr_t addr, uint32_t val) @@ -84,14 +86,16 @@ void cpu_outl(pio_addr_t addr, uint32_t val) LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); trace_cpu_out(addr, val); stl_p(buf, val); - address_space_write(&address_space_io, addr, buf, 4); + address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + buf, 4); } uint8_t cpu_inb(pio_addr_t addr) { uint8_t val; - address_space_read(&address_space_io, addr, &val, 1); + address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + &val, 1); trace_cpu_in(addr, val); LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); return val; @@ -102,7 +106,7 @@ uint16_t cpu_inw(pio_addr_t addr) uint8_t buf[2]; uint16_t val; - address_space_read(&address_space_io, addr, buf, 2); + address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, buf, 2); val = lduw_p(buf); trace_cpu_in(addr, val); LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); @@ -114,7 +118,7 @@ uint32_t cpu_inl(pio_addr_t addr) uint8_t buf[4]; uint32_t val; - address_space_read(&address_space_io, addr, buf, 4); + address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, buf, 4); val = ldl_p(buf); trace_cpu_in(addr, val); LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); diff --git a/kvm-all.c b/kvm-all.c index dd44f8c753..4ec153df93 100644 --- a/kvm-all.c +++ b/kvm-all.c @@ -1667,7 +1667,8 @@ static void kvm_handle_io(uint16_t port, void *data, int direction, int size, uint8_t *ptr = data; for (i = 0; i < count; i++) { - address_space_rw(&address_space_io, port, ptr, size, + address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED, + ptr, size, direction == KVM_EXIT_IO_OUT); ptr += size; } diff --git a/scripts/coverity-model.c b/scripts/coverity-model.c index cdda2591d9..224d2d1873 100644 --- a/scripts/coverity-model.c +++ b/scripts/coverity-model.c @@ -46,6 +46,8 @@ typedef struct va_list_str *va_list; typedef struct AddressSpace AddressSpace; typedef uint64_t hwaddr; +typedef uint32_t MemTxResult; +typedef uint64_t MemTxAttrs; static void __write(uint8_t *buf, ssize_t len) { @@ -65,10 +67,10 @@ static void __read(uint8_t *buf, ssize_t len) int last = buf[len-1]; } -bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, - int len, bool is_write) +MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + uint8_t *buf, int len, bool is_write) { - bool result; + MemTxResult result; // TODO: investigate impact of treating reads as producing // tainted data, with __coverity_tainted_data_argument__(buf). -- cgit v1.2.3-55-g7522 From 500131154d677930fce35ec3a6f0b5a26bcd2973 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:24 +0100 Subject: exec.c: Add new address_space_ld*/st* functions Add new address_space_ld*/st* functions which allow transaction attributes and error reporting for basic load and stores. These are named to be in line with the address_space_read/write/rw buffer operations. The existing ld/st*_phys functions are now wrappers around the new functions. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée --- exec.c | 297 +++++++++++++++++++++++++++++++++++++++++--------- include/exec/memory.h | 67 ++++++++++++ 2 files changed, 314 insertions(+), 50 deletions(-) (limited to 'include/exec/memory.h') diff --git a/exec.c b/exec.c index 9811a9cbc0..399543ef98 100644 --- a/exec.c +++ b/exec.c @@ -2679,20 +2679,22 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len, } /* warning: addr must be aligned */ -static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr, - enum device_endian endian) +static inline uint32_t address_space_ldl_internal(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; uint64_t val; MemoryRegion *mr; hwaddr l = 4; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, false); if (l < 4 || !memory_access_is_direct(mr, false)) { /* I/O case */ - memory_region_dispatch_read(mr, addr1, &val, 4, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap32(val); @@ -2718,41 +2720,68 @@ static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr, val = ldl_p(ptr); break; } + r = MEMTX_OK; + } + if (result) { + *result = r; } return val; } +uint32_t address_space_ldl(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldl_internal(as, addr, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +uint32_t address_space_ldl_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldl_internal(as, addr, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +uint32_t address_space_ldl_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldl_internal(as, addr, attrs, result, + DEVICE_BIG_ENDIAN); +} + uint32_t ldl_phys(AddressSpace *as, hwaddr addr) { - return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN); + return address_space_ldl(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr) { - return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN); + return address_space_ldl_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr) { - return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN); + return address_space_ldl_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } /* warning: addr must be aligned */ -static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr, - enum device_endian endian) +static inline uint64_t address_space_ldq_internal(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; uint64_t val; MemoryRegion *mr; hwaddr l = 8; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, false); if (l < 8 || !memory_access_is_direct(mr, false)) { /* I/O case */ - memory_region_dispatch_read(mr, addr1, &val, 8, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap64(val); @@ -2778,49 +2807,88 @@ static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr, val = ldq_p(ptr); break; } + r = MEMTX_OK; + } + if (result) { + *result = r; } return val; } +uint64_t address_space_ldq(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldq_internal(as, addr, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +uint64_t address_space_ldq_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldq_internal(as, addr, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +uint64_t address_space_ldq_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldq_internal(as, addr, attrs, result, + DEVICE_BIG_ENDIAN); +} + uint64_t ldq_phys(AddressSpace *as, hwaddr addr) { - return ldq_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN); + return address_space_ldq(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr) { - return ldq_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN); + return address_space_ldq_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr) { - return ldq_phys_internal(as, addr, DEVICE_BIG_ENDIAN); + return address_space_ldq_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } /* XXX: optimize */ -uint32_t ldub_phys(AddressSpace *as, hwaddr addr) +uint32_t address_space_ldub(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) { uint8_t val; - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &val, 1, 0); + MemTxResult r; + + r = address_space_rw(as, addr, attrs, &val, 1, 0); + if (result) { + *result = r; + } return val; } +uint32_t ldub_phys(AddressSpace *as, hwaddr addr) +{ + return address_space_ldub(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); +} + /* warning: addr must be aligned */ -static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr, - enum device_endian endian) +static inline uint32_t address_space_lduw_internal(AddressSpace *as, + hwaddr addr, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; uint64_t val; MemoryRegion *mr; hwaddr l = 2; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, false); if (l < 2 || !memory_access_is_direct(mr, false)) { /* I/O case */ - memory_region_dispatch_read(mr, addr1, &val, 2, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap16(val); @@ -2846,40 +2914,66 @@ static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr, val = lduw_p(ptr); break; } + r = MEMTX_OK; + } + if (result) { + *result = r; } return val; } +uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_lduw_internal(as, addr, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +uint32_t address_space_lduw_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_lduw_internal(as, addr, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +uint32_t address_space_lduw_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_lduw_internal(as, addr, attrs, result, + DEVICE_BIG_ENDIAN); +} + uint32_t lduw_phys(AddressSpace *as, hwaddr addr) { - return lduw_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN); + return address_space_lduw(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr) { - return lduw_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN); + return address_space_lduw_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr) { - return lduw_phys_internal(as, addr, DEVICE_BIG_ENDIAN); + return address_space_lduw_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } /* warning: addr must be aligned. The ram page is not masked as dirty and the code inside is not invalidated. It is useful if the dirty bits are used to track modified PTEs */ -void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) +void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) { uint8_t *ptr; MemoryRegion *mr; hwaddr l = 4; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, true); if (l < 4 || !memory_access_is_direct(mr, true)) { - memory_region_dispatch_write(mr, addr1, val, 4, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); } else { addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; ptr = qemu_get_ram_ptr(addr1); @@ -2893,18 +2987,30 @@ void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) cpu_physical_memory_set_dirty_range_nocode(addr1, 4); } } + r = MEMTX_OK; + } + if (result) { + *result = r; } } +void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) +{ + address_space_stl_notdirty(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); +} + /* warning: addr must be aligned */ -static inline void stl_phys_internal(AddressSpace *as, - hwaddr addr, uint32_t val, - enum device_endian endian) +static inline void address_space_stl_internal(AddressSpace *as, + hwaddr addr, uint32_t val, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; MemoryRegion *mr; hwaddr l = 4; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, true); @@ -2918,8 +3024,7 @@ static inline void stl_phys_internal(AddressSpace *as, val = bswap32(val); } #endif - memory_region_dispatch_write(mr, addr1, val, 4, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); } else { /* RAM case */ addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; @@ -2936,40 +3041,79 @@ static inline void stl_phys_internal(AddressSpace *as, break; } invalidate_and_set_dirty(addr1, 4); + r = MEMTX_OK; + } + if (result) { + *result = r; } } +void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stl_internal(as, addr, val, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +void address_space_stl_le(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stl_internal(as, addr, val, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +void address_space_stl_be(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stl_internal(as, addr, val, attrs, result, + DEVICE_BIG_ENDIAN); +} + void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stl_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN); + address_space_stl(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stl_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN); + address_space_stl_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stl_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN); + address_space_stl_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } /* XXX: optimize */ -void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val) +void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) { uint8_t v = val; - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &v, 1, 1); + MemTxResult r; + + r = address_space_rw(as, addr, attrs, &v, 1, 1); + if (result) { + *result = r; + } +} + +void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val) +{ + address_space_stb(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } /* warning: addr must be aligned */ -static inline void stw_phys_internal(AddressSpace *as, - hwaddr addr, uint32_t val, - enum device_endian endian) +static inline void address_space_stw_internal(AddressSpace *as, + hwaddr addr, uint32_t val, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; MemoryRegion *mr; hwaddr l = 2; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, true); if (l < 2 || !memory_access_is_direct(mr, true)) { @@ -2982,8 +3126,7 @@ static inline void stw_phys_internal(AddressSpace *as, val = bswap16(val); } #endif - memory_region_dispatch_write(mr, addr1, val, 2, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_write(mr, addr1, val, 2, attrs); } else { /* RAM case */ addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; @@ -3000,41 +3143,95 @@ static inline void stw_phys_internal(AddressSpace *as, break; } invalidate_and_set_dirty(addr1, 2); + r = MEMTX_OK; + } + if (result) { + *result = r; } } +void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stw_internal(as, addr, val, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +void address_space_stw_le(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stw_internal(as, addr, val, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +void address_space_stw_be(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stw_internal(as, addr, val, attrs, result, + DEVICE_BIG_ENDIAN); +} + void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN); + address_space_stw(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN); + address_space_stw_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN); + address_space_stw_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } /* XXX: optimize */ -void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val) +void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result) { + MemTxResult r; val = tswap64(val); - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); + r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); + if (result) { + *result = r; + } } -void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val) +void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result) { + MemTxResult r; val = cpu_to_le64(val); - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); + r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); + if (result) { + *result = r; + } +} +void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + MemTxResult r; + val = cpu_to_be64(val); + r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); + if (result) { + *result = r; + } +} + +void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val) +{ + address_space_stq(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); +} + +void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val) +{ + address_space_stq_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val) { - val = cpu_to_be64(val); - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); + address_space_stq_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } /* virtual memory access for debug (includes writing to ROM) */ diff --git a/include/exec/memory.h b/include/exec/memory.h index cafd590b92..2f386cecb7 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1153,6 +1153,73 @@ MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, uint8_t *buf, int len); +/** + * address_space_ld*: load from an address space + * address_space_st*: store to an address space + * + * These functions perform a load or store of the byte, word, + * longword or quad to the specified address within the AddressSpace. + * The _le suffixed functions treat the data as little endian; + * _be indicates big endian; no suffix indicates "same endianness + * as guest CPU". + * + * The "guest CPU endianness" accessors are deprecated for use outside + * target-* code; devices should be CPU-agnostic and use either the LE + * or the BE accessors. + * + * @as #AddressSpace to be accessed + * @addr: address within that address space + * @val: data value, for stores + * @attrs: memory transaction attributes + * @result: location to write the success/failure of the transaction; + * if NULL, this information is discarded + */ +uint32_t address_space_ldub(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_lduw_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_lduw_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_ldl_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_ldl_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint64_t address_space_ldq_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint64_t address_space_ldq_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stw_le(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stw_be(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stl_le(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stl_be(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result); + +#ifdef NEED_CPU_H +uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_ldl(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint64_t address_space_ldq(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result); +#endif + /* address_space_translate: translate an address range into an address space * into a MemoryRegion and an address range into that section * -- cgit v1.2.3-55-g7522