From cc05c43ad942165ecc6ffd39e41991bee43af044 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:23 +0100 Subject: memory: Define API for MemoryRegionOps to take attrs and return status Define an API so that devices can register MemoryRegionOps whose read and write callback functions are passed an arbitrary pointer to some transaction attributes and can return a success-or-failure status code. This will allow us to model devices which: * behave differently for ARM Secure/NonSecure memory accesses * behave differently for privileged/unprivileged accesses * may return a transaction failure (causing a guest exception) for erroneous accesses This patch defines the new API and plumbs the attributes parameter through to the memory.c public level functions io_mem_read() and io_mem_write(), where it is currently dummied out. The success/failure response indication is also propagated out to io_mem_read() and io_mem_write(), which retain the old-style boolean true-for-error return. Signed-off-by: Peter Maydell Acked-by: Paolo Bonzini Reviewed-by: Alex Bennée --- include/exec/memattrs.h | 41 +++++++++++++++++++++++++++++++++++++++++ include/exec/memory.h | 22 ++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 include/exec/memattrs.h (limited to 'include/exec') diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h new file mode 100644 index 0000000000..1cb3fc0815 --- /dev/null +++ b/include/exec/memattrs.h @@ -0,0 +1,41 @@ +/* + * Memory transaction attributes + * + * Copyright (c) 2015 Linaro Limited. + * + * Authors: + * Peter Maydell + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef MEMATTRS_H +#define MEMATTRS_H + +/* Every memory transaction has associated with it a set of + * attributes. Some of these are generic (such as the ID of + * the bus master); some are specific to a particular kind of + * bus (such as the ARM Secure/NonSecure bit). We define them + * all as non-overlapping bitfields in a single struct to avoid + * confusion if different parts of QEMU used the same bit for + * different semantics. + */ +typedef struct MemTxAttrs { + /* Bus masters which don't specify any attributes will get this + * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can + * distinguish "all attributes deliberately clear" from + * "didn't specify" if necessary. + */ + unsigned int unspecified:1; +} MemTxAttrs; + +/* Bus masters which don't specify any attributes will get this, + * which has all attribute bits clear except the topmost one + * (so that we can distinguish "all attributes deliberately clear" + * from "didn't specify" if necessary). + */ +#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 }) + +#endif diff --git a/include/exec/memory.h b/include/exec/memory.h index 06ffa1d185..703d9e5f8f 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -28,6 +28,7 @@ #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif +#include "exec/memattrs.h" #include "qemu/queue.h" #include "qemu/int128.h" #include "qemu/notify.h" @@ -68,6 +69,16 @@ struct IOMMUTLBEntry { IOMMUAccessFlags perm; }; +/* New-style MMIO accessors can indicate that the transaction failed. + * A zero (MEMTX_OK) response means success; anything else is a failure + * of some kind. The memory subsystem will bitwise-OR together results + * if it is synthesizing an operation from multiple smaller accesses. + */ +#define MEMTX_OK 0 +#define MEMTX_ERROR (1U << 0) /* device returned an error */ +#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ +typedef uint32_t MemTxResult; + /* * Memory region callbacks */ @@ -84,6 +95,17 @@ struct MemoryRegionOps { uint64_t data, unsigned size); + MemTxResult (*read_with_attrs)(void *opaque, + hwaddr addr, + uint64_t *data, + unsigned size, + MemTxAttrs attrs); + MemTxResult (*write_with_attrs)(void *opaque, + hwaddr addr, + uint64_t data, + unsigned size, + MemTxAttrs attrs); + enum device_endian endianness; /* Guest-visible constraints: */ struct { -- cgit v1.2.3-55-g7522 From 3b6434953934e6d4a776ed426d8c6d6badee176f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:23 +0100 Subject: memory: Replace io_mem_read/write with memory_region_dispatch_read/write Rather than retaining io_mem_read/write as simple wrappers around the memory_region_dispatch_read/write functions, make the latter public and change all the callers to use them, since we need to touch all the callsites anyway to add MemTxAttrs and MemTxResult support. Delete io_mem_read and io_mem_write entirely. (All the callers currently pass MEMTXATTRS_UNSPECIFIED and convert the return value back to bool or ignore it.) Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée --- exec.c | 47 +++++++++++++++++++++++++++++++---------------- hw/s390x/s390-pci-inst.c | 10 +++++++--- hw/vfio/pci.c | 18 ++++++++++++------ include/exec/exec-all.h | 4 ---- include/exec/memory.h | 31 +++++++++++++++++++++++++++++++ memory.c | 33 ++++++++++----------------------- softmmu_template.h | 6 ++++-- 7 files changed, 95 insertions(+), 54 deletions(-) (limited to 'include/exec') diff --git a/exec.c b/exec.c index 874ecfc2c6..34dafd2e36 100644 --- a/exec.c +++ b/exec.c @@ -2312,7 +2312,8 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, uint64_t val; hwaddr addr1; MemoryRegion *mr; - bool error = false; + MemTxResult result = MEMTX_OK; + MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; while (len > 0) { l = len; @@ -2327,22 +2328,26 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, case 8: /* 64 bit write access */ val = ldq_p(buf); - error |= io_mem_write(mr, addr1, val, 8); + result |= memory_region_dispatch_write(mr, addr1, val, 8, + attrs); break; case 4: /* 32 bit write access */ val = ldl_p(buf); - error |= io_mem_write(mr, addr1, val, 4); + result |= memory_region_dispatch_write(mr, addr1, val, 4, + attrs); break; case 2: /* 16 bit write access */ val = lduw_p(buf); - error |= io_mem_write(mr, addr1, val, 2); + result |= memory_region_dispatch_write(mr, addr1, val, 2, + attrs); break; case 1: /* 8 bit write access */ val = ldub_p(buf); - error |= io_mem_write(mr, addr1, val, 1); + result |= memory_region_dispatch_write(mr, addr1, val, 1, + attrs); break; default: abort(); @@ -2361,22 +2366,26 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, switch (l) { case 8: /* 64 bit read access */ - error |= io_mem_read(mr, addr1, &val, 8); + result |= memory_region_dispatch_read(mr, addr1, &val, 8, + attrs); stq_p(buf, val); break; case 4: /* 32 bit read access */ - error |= io_mem_read(mr, addr1, &val, 4); + result |= memory_region_dispatch_read(mr, addr1, &val, 4, + attrs); stl_p(buf, val); break; case 2: /* 16 bit read access */ - error |= io_mem_read(mr, addr1, &val, 2); + result |= memory_region_dispatch_read(mr, addr1, &val, 2, + attrs); stw_p(buf, val); break; case 1: /* 8 bit read access */ - error |= io_mem_read(mr, addr1, &val, 1); + result |= memory_region_dispatch_read(mr, addr1, &val, 1, + attrs); stb_p(buf, val); break; default: @@ -2393,7 +2402,7 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, addr += l; } - return error; + return result; } bool address_space_write(AddressSpace *as, hwaddr addr, @@ -2669,7 +2678,8 @@ static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr, mr = address_space_translate(as, addr, &addr1, &l, false); if (l < 4 || !memory_access_is_direct(mr, false)) { /* I/O case */ - io_mem_read(mr, addr1, &val, 4); + memory_region_dispatch_read(mr, addr1, &val, 4, + MEMTXATTRS_UNSPECIFIED); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap32(val); @@ -2728,7 +2738,8 @@ static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr, false); if (l < 8 || !memory_access_is_direct(mr, false)) { /* I/O case */ - io_mem_read(mr, addr1, &val, 8); + memory_region_dispatch_read(mr, addr1, &val, 8, + MEMTXATTRS_UNSPECIFIED); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap64(val); @@ -2795,7 +2806,8 @@ static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr, false); if (l < 2 || !memory_access_is_direct(mr, false)) { /* I/O case */ - io_mem_read(mr, addr1, &val, 2); + memory_region_dispatch_read(mr, addr1, &val, 2, + MEMTXATTRS_UNSPECIFIED); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap16(val); @@ -2853,7 +2865,8 @@ void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) mr = address_space_translate(as, addr, &addr1, &l, true); if (l < 4 || !memory_access_is_direct(mr, true)) { - io_mem_write(mr, addr1, val, 4); + memory_region_dispatch_write(mr, addr1, val, 4, + MEMTXATTRS_UNSPECIFIED); } else { addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; ptr = qemu_get_ram_ptr(addr1); @@ -2892,7 +2905,8 @@ static inline void stl_phys_internal(AddressSpace *as, val = bswap32(val); } #endif - io_mem_write(mr, addr1, val, 4); + memory_region_dispatch_write(mr, addr1, val, 4, + MEMTXATTRS_UNSPECIFIED); } else { /* RAM case */ addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; @@ -2955,7 +2969,8 @@ static inline void stw_phys_internal(AddressSpace *as, val = bswap16(val); } #endif - io_mem_write(mr, addr1, val, 2); + memory_region_dispatch_write(mr, addr1, val, 2, + MEMTXATTRS_UNSPECIFIED); } else { /* RAM case */ addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 08d8aa6b4b..8f7288fadf 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -331,7 +331,8 @@ int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2) return 0; } MemoryRegion *mr = pbdev->pdev->io_regions[pcias].memory; - io_mem_read(mr, offset, &data, len); + memory_region_dispatch_read(mr, offset, &data, len, + MEMTXATTRS_UNSPECIFIED); } else if (pcias == 15) { if ((4 - (offset & 0x3)) < len) { program_interrupt(env, PGM_OPERAND, 4); @@ -456,7 +457,8 @@ int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2) mr = pbdev->pdev->io_regions[pcias].memory; } - io_mem_write(mr, offset, data, len); + memory_region_dispatch_write(mr, offset, data, len, + MEMTXATTRS_UNSPECIFIED); } else if (pcias == 15) { if ((4 - (offset & 0x3)) < len) { program_interrupt(env, PGM_OPERAND, 4); @@ -606,7 +608,9 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr) } for (i = 0; i < len / 8; i++) { - io_mem_write(mr, env->regs[r3] + i * 8, ldq_p(buffer + i * 8), 8); + memory_region_dispatch_write(mr, env->regs[r3] + i * 8, + ldq_p(buffer + i * 8), 8, + MEMTXATTRS_UNSPECIFIED); } setcc(cpu, ZPCI_PCI_LS_OK); diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 6b80539c1f..cd15b20990 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1531,9 +1531,12 @@ static uint64_t vfio_rtl8168_window_quirk_read(void *opaque, return 0; } - io_mem_read(&vdev->pdev.msix_table_mmio, - (hwaddr)(quirk->data.address_match & 0xfff), - &val, size); + memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, + (hwaddr)(quirk->data.address_match + & 0xfff), + &val, + size, + MEMTXATTRS_UNSPECIFIED); return val; } } @@ -1561,9 +1564,12 @@ static void vfio_rtl8168_window_quirk_write(void *opaque, hwaddr addr, memory_region_name(&quirk->mem), vdev->vbasedev.name); - io_mem_write(&vdev->pdev.msix_table_mmio, - (hwaddr)(quirk->data.address_match & 0xfff), - data, size); + memory_region_dispatch_write(&vdev->pdev.msix_table_mmio, + (hwaddr)(quirk->data.address_match + & 0xfff), + data, + size, + MEMTXATTRS_UNSPECIFIED); } quirk->data.flags = 1; diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 8eb0db3910..ff1bc3e4c1 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -341,10 +341,6 @@ void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)); struct MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index); -bool io_mem_read(struct MemoryRegion *mr, hwaddr addr, - uint64_t *pvalue, unsigned size); -bool io_mem_write(struct MemoryRegion *mr, hwaddr addr, - uint64_t value, unsigned size); void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr); diff --git a/include/exec/memory.h b/include/exec/memory.h index 703d9e5f8f..970a3a9b1e 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1052,6 +1052,37 @@ void memory_global_dirty_log_stop(void); void mtree_info(fprintf_function mon_printf, void *f); +/** + * memory_region_dispatch_read: perform a read directly to the specified + * MemoryRegion. + * + * @mr: #MemoryRegion to access + * @addr: address within that region + * @pval: pointer to uint64_t which the data is written to + * @size: size of the access in bytes + * @attrs: memory transaction attributes to use for the access + */ +MemTxResult memory_region_dispatch_read(MemoryRegion *mr, + hwaddr addr, + uint64_t *pval, + unsigned size, + MemTxAttrs attrs); +/** + * memory_region_dispatch_write: perform a write directly to the specified + * MemoryRegion. + * + * @mr: #MemoryRegion to access + * @addr: address within that region + * @data: data to write + * @size: size of the access in bytes + * @attrs: memory transaction attributes to use for the access + */ +MemTxResult memory_region_dispatch_write(MemoryRegion *mr, + hwaddr addr, + uint64_t data, + unsigned size, + MemTxAttrs attrs); + /** * address_space_init: initializes an address space * diff --git a/memory.c b/memory.c index 9bb5674bb9..a403c86b22 100644 --- a/memory.c +++ b/memory.c @@ -1131,11 +1131,11 @@ static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr, } } -static MemTxResult memory_region_dispatch_read(MemoryRegion *mr, - hwaddr addr, - uint64_t *pval, - unsigned size, - MemTxAttrs attrs) +MemTxResult memory_region_dispatch_read(MemoryRegion *mr, + hwaddr addr, + uint64_t *pval, + unsigned size, + MemTxAttrs attrs) { MemTxResult r; @@ -1149,11 +1149,11 @@ static MemTxResult memory_region_dispatch_read(MemoryRegion *mr, return r; } -static MemTxResult memory_region_dispatch_write(MemoryRegion *mr, - hwaddr addr, - uint64_t data, - unsigned size, - MemTxAttrs attrs) +MemTxResult memory_region_dispatch_write(MemoryRegion *mr, + hwaddr addr, + uint64_t data, + unsigned size, + MemTxAttrs attrs) { if (!memory_region_access_valid(mr, addr, size, true)) { unassigned_mem_write(mr, addr, data, size); @@ -2063,19 +2063,6 @@ void address_space_destroy(AddressSpace *as) call_rcu(as, do_address_space_destroy, rcu); } -bool io_mem_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, unsigned size) -{ - return memory_region_dispatch_read(mr, addr, pval, size, - MEMTXATTRS_UNSPECIFIED); -} - -bool io_mem_write(MemoryRegion *mr, hwaddr addr, - uint64_t val, unsigned size) -{ - return memory_region_dispatch_write(mr, addr, val, size, - MEMTXATTRS_UNSPECIFIED); -} - typedef struct MemoryRegionList MemoryRegionList; struct MemoryRegionList { diff --git a/softmmu_template.h b/softmmu_template.h index 0e3dd35fe1..9c1d53e2e4 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -158,7 +158,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, } cpu->mem_io_vaddr = addr; - io_mem_read(mr, physaddr, &val, 1 << SHIFT); + memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT, + MEMTXATTRS_UNSPECIFIED); return val; } #endif @@ -378,7 +379,8 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, cpu->mem_io_vaddr = addr; cpu->mem_io_pc = retaddr; - io_mem_write(mr, physaddr, val, 1 << SHIFT); + memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT, + MEMTXATTRS_UNSPECIFIED); } void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, -- cgit v1.2.3-55-g7522 From e469b22ffda40188954fafaf6e3308f58d50f8f8 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:23 +0100 Subject: Make CPU iotlb a structure rather than a plain hwaddr Make the CPU iotlb a structure rather than a plain hwaddr; this will allow us to add transaction attributes to it. Signed-off-by: Peter Maydell Reviewed-by: Paolo Bonzini Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée --- cputlb.c | 4 ++-- include/exec/cpu-defs.h | 13 +++++++++++-- softmmu_template.h | 32 +++++++++++++++++--------------- 3 files changed, 30 insertions(+), 19 deletions(-) (limited to 'include/exec') diff --git a/cputlb.c b/cputlb.c index 38f2151166..5e1cb8f9d2 100644 --- a/cputlb.c +++ b/cputlb.c @@ -301,7 +301,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index]; /* refill the tlb */ - env->iotlb[mmu_idx][index] = iotlb - vaddr; + env->iotlb[mmu_idx][index].addr = iotlb - vaddr; te->addend = addend - vaddr; if (prot & PAGE_READ) { te->addr_read = address; @@ -349,7 +349,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) (addr & TARGET_PAGE_MASK))) { cpu_ldub_code(env1, addr); } - pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK; + pd = env1->iotlb[mmu_idx][page_index].addr & ~TARGET_PAGE_MASK; mr = iotlb_to_region(cpu, pd); if (memory_region_is_unassigned(mr)) { CPUClass *cc = CPU_GET_CLASS(cpu); diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 0ca6f0b953..7f88185c7f 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -102,12 +102,21 @@ typedef struct CPUTLBEntry { QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); +/* The IOTLB is not accessed directly inline by generated TCG code, + * so the CPUIOTLBEntry layout is not as critical as that of the + * CPUTLBEntry. (This is also why we don't want to combine the two + * structs into one.) + */ +typedef struct CPUIOTLBEntry { + hwaddr addr; +} CPUIOTLBEntry; + #define CPU_COMMON_TLB \ /* The meaning of the MMU modes is defined in the target code. */ \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ - hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ - hwaddr iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ + CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ + CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ target_ulong tlb_flush_addr; \ target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ diff --git a/softmmu_template.h b/softmmu_template.h index 9c1d53e2e4..0e30986e5b 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -123,7 +123,7 @@ * victim tlb. try to refill from the victim tlb before walking the \ * page table. */ \ int vidx; \ - hwaddr tmpiotlb; \ + CPUIOTLBEntry tmpiotlb; \ CPUTLBEntry tmptlb; \ for (vidx = CPU_VTLB_SIZE-1; vidx >= 0; --vidx) { \ if (env->tlb_v_table[mmu_idx][vidx].ty == (addr & TARGET_PAGE_MASK)) {\ @@ -143,12 +143,13 @@ #ifndef SOFTMMU_CODE_ACCESS static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, - hwaddr physaddr, + CPUIOTLBEntry *iotlbentry, target_ulong addr, uintptr_t retaddr) { uint64_t val; CPUState *cpu = ENV_GET_CPU(env); + hwaddr physaddr = iotlbentry->addr; MemoryRegion *mr = iotlb_to_region(cpu, physaddr); physaddr = (physaddr & TARGET_PAGE_MASK) + addr; @@ -196,15 +197,15 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - hwaddr ioaddr; + CPUIOTLBEntry *iotlbentry; if ((addr & (DATA_SIZE - 1)) != 0) { goto do_unaligned_access; } - ioaddr = env->iotlb[mmu_idx][index]; + iotlbentry = &env->iotlb[mmu_idx][index]; /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. */ - res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr); + res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr); res = TGT_LE(res); return res; } @@ -284,15 +285,15 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - hwaddr ioaddr; + CPUIOTLBEntry *iotlbentry; if ((addr & (DATA_SIZE - 1)) != 0) { goto do_unaligned_access; } - ioaddr = env->iotlb[mmu_idx][index]; + iotlbentry = &env->iotlb[mmu_idx][index]; /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. */ - res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr); + res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr); res = TGT_BE(res); return res; } @@ -364,12 +365,13 @@ WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr, #endif static inline void glue(io_write, SUFFIX)(CPUArchState *env, - hwaddr physaddr, + CPUIOTLBEntry *iotlbentry, DATA_TYPE val, target_ulong addr, uintptr_t retaddr) { CPUState *cpu = ENV_GET_CPU(env); + hwaddr physaddr = iotlbentry->addr; MemoryRegion *mr = iotlb_to_region(cpu, physaddr); physaddr = (physaddr & TARGET_PAGE_MASK) + addr; @@ -410,16 +412,16 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - hwaddr ioaddr; + CPUIOTLBEntry *iotlbentry; if ((addr & (DATA_SIZE - 1)) != 0) { goto do_unaligned_access; } - ioaddr = env->iotlb[mmu_idx][index]; + iotlbentry = &env->iotlb[mmu_idx][index]; /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. */ val = TGT_LE(val); - glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr); + glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr); return; } @@ -491,16 +493,16 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - hwaddr ioaddr; + CPUIOTLBEntry *iotlbentry; if ((addr & (DATA_SIZE - 1)) != 0) { goto do_unaligned_access; } - ioaddr = env->iotlb[mmu_idx][index]; + iotlbentry = &env->iotlb[mmu_idx][index]; /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. */ val = TGT_BE(val); - glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr); + glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr); return; } -- cgit v1.2.3-55-g7522 From fadc1cbe85c6b032d5842ec0d19d209f50fcb375 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:24 +0100 Subject: Add MemTxAttrs to the IOTLB Add a MemTxAttrs field to the IOTLB, and allow target-specific code to set it via a new tlb_set_page_with_attrs() function; pass the attributes through to the device when making IO accesses. Signed-off-by: Peter Maydell Reviewed-by: Paolo Bonzini Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée --- cputlb.c | 18 +++++++++++++++--- include/exec/cpu-defs.h | 2 ++ include/exec/exec-all.h | 3 +++ softmmu_template.h | 4 ++-- 4 files changed, 22 insertions(+), 5 deletions(-) (limited to 'include/exec') diff --git a/cputlb.c b/cputlb.c index 5e1cb8f9d2..7606548200 100644 --- a/cputlb.c +++ b/cputlb.c @@ -249,9 +249,9 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, * Called from TCG-generated code, which is under an RCU read-side * critical section. */ -void tlb_set_page(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, int prot, - int mmu_idx, target_ulong size) +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, int prot, + int mmu_idx, target_ulong size) { CPUArchState *env = cpu->env_ptr; MemoryRegionSection *section; @@ -302,6 +302,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, /* refill the tlb */ env->iotlb[mmu_idx][index].addr = iotlb - vaddr; + env->iotlb[mmu_idx][index].attrs = attrs; te->addend = addend - vaddr; if (prot & PAGE_READ) { te->addr_read = address; @@ -331,6 +332,17 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, } } +/* Add a new TLB entry, but without specifying the memory + * transaction attributes to be used. + */ +void tlb_set_page(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, int prot, + int mmu_idx, target_ulong size) +{ + tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED, + prot, mmu_idx, size); +} + /* NOTE: this function can trigger an exception */ /* NOTE2: the returned address is not exactly the physical address: it * is actually a ram_addr_t (in system mode; the user mode emulation diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 7f88185c7f..3f56546066 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -30,6 +30,7 @@ #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif +#include "exec/memattrs.h" #ifndef TARGET_LONG_BITS #error TARGET_LONG_BITS must be defined before including this header @@ -109,6 +110,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); */ typedef struct CPUIOTLBEntry { hwaddr addr; + MemTxAttrs attrs; } CPUIOTLBEntry; #define CPU_COMMON_TLB \ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ff1bc3e4c1..b58cd47ced 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -105,6 +105,9 @@ void tlb_flush(CPUState *cpu, int flush_global); void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, target_ulong size); void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); #else static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) diff --git a/softmmu_template.h b/softmmu_template.h index 0e30986e5b..16b08523e9 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -160,7 +160,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, cpu->mem_io_vaddr = addr; memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT, - MEMTXATTRS_UNSPECIFIED); + iotlbentry->attrs); return val; } #endif @@ -382,7 +382,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env, cpu->mem_io_vaddr = addr; cpu->mem_io_pc = retaddr; memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT, - MEMTXATTRS_UNSPECIFIED); + iotlbentry->attrs); } void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, -- cgit v1.2.3-55-g7522 From 5c9eb0286c819c1836220a32f2e1a7b5004ac79a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:24 +0100 Subject: exec.c: Make address_space_rw take transaction attributes Make address_space_rw take transaction attributes, rather than always using the 'unspecified' attributes. Signed-off-by: Peter Maydell Reviewed-by: Paolo Bonzini Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée --- dma-helpers.c | 3 ++- exec.c | 51 ++++++++++++++++++++++++++---------------------- hw/mips/mips_jazz.c | 6 ++++-- hw/pci-host/prep.c | 6 ++++-- include/exec/memory.h | 31 ++++++++++++++++++----------- include/sysemu/dma.h | 3 ++- ioport.c | 16 +++++++++------ kvm-all.c | 3 ++- scripts/coverity-model.c | 8 +++++--- 9 files changed, 77 insertions(+), 50 deletions(-) (limited to 'include/exec') diff --git a/dma-helpers.c b/dma-helpers.c index 6918572e18..33b1983b25 100644 --- a/dma-helpers.c +++ b/dma-helpers.c @@ -28,7 +28,8 @@ int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len) memset(fillbuf, c, FILLBUF_SIZE); while (len > 0) { l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE; - error |= address_space_rw(as, addr, fillbuf, l, true); + error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, + fillbuf, l, true); len -= l; addr += l; } diff --git a/exec.c b/exec.c index bba6f26e5c..9811a9cbc0 100644 --- a/exec.c +++ b/exec.c @@ -1946,13 +1946,16 @@ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, { subpage_t *subpage = opaque; uint8_t buf[8]; + MemTxResult res; #if defined(DEBUG_SUBPAGE) printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, subpage, len, addr); #endif - if (address_space_read(subpage->as, addr + subpage->base, buf, len)) { - return MEMTX_DECODE_ERROR; + res = address_space_read(subpage->as, addr + subpage->base, + attrs, buf, len); + if (res) { + return res; } switch (len) { case 1: @@ -1999,10 +2002,8 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr, default: abort(); } - if (address_space_write(subpage->as, addr + subpage->base, buf, len)) { - return MEMTX_DECODE_ERROR; - } - return MEMTX_OK; + return address_space_write(subpage->as, addr + subpage->base, + attrs, buf, len); } static bool subpage_accepts(void *opaque, hwaddr addr, @@ -2313,8 +2314,8 @@ static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) return l; } -bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, - int len, bool is_write) +MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + uint8_t *buf, int len, bool is_write) { hwaddr l; uint8_t *ptr; @@ -2322,7 +2323,6 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, hwaddr addr1; MemoryRegion *mr; MemTxResult result = MEMTX_OK; - MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; while (len > 0) { l = len; @@ -2414,22 +2414,24 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, return result; } -bool address_space_write(AddressSpace *as, hwaddr addr, - const uint8_t *buf, int len) +MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + const uint8_t *buf, int len) { - return address_space_rw(as, addr, (uint8_t *)buf, len, true); + return address_space_rw(as, addr, attrs, (uint8_t *)buf, len, true); } -bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len) +MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + uint8_t *buf, int len) { - return address_space_rw(as, addr, buf, len, false); + return address_space_rw(as, addr, attrs, buf, len, false); } void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, int len, int is_write) { - address_space_rw(&address_space_memory, addr, buf, len, is_write); + address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, + buf, len, is_write); } enum write_rom_type { @@ -2600,7 +2602,8 @@ void *address_space_map(AddressSpace *as, memory_region_ref(mr); bounce.mr = mr; if (!is_write) { - address_space_read(as, addr, bounce.buffer, l); + address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED, + bounce.buffer, l); } *plen = l; @@ -2653,7 +2656,8 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, return; } if (is_write) { - address_space_write(as, bounce.addr, bounce.buffer, access_len); + address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, + bounce.buffer, access_len); } qemu_vfree(bounce.buffer); bounce.buffer = NULL; @@ -2797,7 +2801,7 @@ uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr) uint32_t ldub_phys(AddressSpace *as, hwaddr addr) { uint8_t val; - address_space_rw(as, addr, &val, 1, 0); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &val, 1, 0); return val; } @@ -2954,7 +2958,7 @@ void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val) { uint8_t v = val; - address_space_rw(as, addr, &v, 1, 1); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &v, 1, 1); } /* warning: addr must be aligned */ @@ -3018,19 +3022,19 @@ void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val) { val = tswap64(val); - address_space_rw(as, addr, (void *) &val, 8, 1); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); } void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val) { val = cpu_to_le64(val); - address_space_rw(as, addr, (void *) &val, 8, 1); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); } void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val) { val = cpu_to_be64(val); - address_space_rw(as, addr, (void *) &val, 8, 1); + address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); } /* virtual memory access for debug (includes writing to ROM) */ @@ -3054,7 +3058,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, if (is_write) { cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l); } else { - address_space_rw(cpu->as, phys_addr, buf, l, 0); + address_space_rw(cpu->as, phys_addr, MEMTXATTRS_UNSPECIFIED, + buf, l, 0); } len -= l; buf += l; diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 07f3c270d4..2c153e092f 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -61,7 +61,8 @@ static void main_cpu_reset(void *opaque) static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size) { uint8_t val; - address_space_read(&address_space_memory, 0x90000071, &val, 1); + address_space_read(&address_space_memory, 0x90000071, + MEMTXATTRS_UNSPECIFIED, &val, 1); return val; } @@ -69,7 +70,8 @@ static void rtc_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { uint8_t buf = val & 0xff; - address_space_write(&address_space_memory, 0x90000071, &buf, 1); + address_space_write(&address_space_memory, 0x90000071, + MEMTXATTRS_UNSPECIFIED, &buf, 1); } static const MemoryRegionOps rtc_ops = { diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 6cea6ffebb..c63f45d217 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -140,7 +140,8 @@ static uint64_t raven_io_read(void *opaque, hwaddr addr, uint8_t buf[4]; addr = raven_io_address(s, addr); - address_space_read(&s->pci_io_as, addr + 0x80000000, buf, size); + address_space_read(&s->pci_io_as, addr + 0x80000000, + MEMTXATTRS_UNSPECIFIED, buf, size); if (size == 1) { return buf[0]; @@ -171,7 +172,8 @@ static void raven_io_write(void *opaque, hwaddr addr, g_assert_not_reached(); } - address_space_write(&s->pci_io_as, addr + 0x80000000, buf, size); + address_space_write(&s->pci_io_as, addr + 0x80000000, + MEMTXATTRS_UNSPECIFIED, buf, size); } static const MemoryRegionOps raven_io_ops = { diff --git a/include/exec/memory.h b/include/exec/memory.h index 970a3a9b1e..cafd590b92 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1108,41 +1108,50 @@ void address_space_destroy(AddressSpace *as); /** * address_space_rw: read from or write to an address space. * - * Return true if the operation hit any unassigned memory or encountered an - * IOMMU fault. + * Return a MemTxResult indicating whether the operation succeeded + * or failed (eg unassigned memory, device rejected the transaction, + * IOMMU fault). * * @as: #AddressSpace to be accessed * @addr: address within that address space + * @attrs: memory transaction attributes * @buf: buffer with the data transferred * @is_write: indicates the transfer direction */ -bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, - int len, bool is_write); +MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, uint8_t *buf, + int len, bool is_write); /** * address_space_write: write to address space. * - * Return true if the operation hit any unassigned memory or encountered an - * IOMMU fault. + * Return a MemTxResult indicating whether the operation succeeded + * or failed (eg unassigned memory, device rejected the transaction, + * IOMMU fault). * * @as: #AddressSpace to be accessed * @addr: address within that address space + * @attrs: memory transaction attributes * @buf: buffer with the data transferred */ -bool address_space_write(AddressSpace *as, hwaddr addr, - const uint8_t *buf, int len); +MemTxResult address_space_write(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, + const uint8_t *buf, int len); /** * address_space_read: read from an address space. * - * Return true if the operation hit any unassigned memory or encountered an - * IOMMU fault. + * Return a MemTxResult indicating whether the operation succeeded + * or failed (eg unassigned memory, device rejected the transaction, + * IOMMU fault). * * @as: #AddressSpace to be accessed * @addr: address within that address space + * @attrs: memory transaction attributes * @buf: buffer with the data transferred */ -bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len); +MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + uint8_t *buf, int len); /* address_space_translate: translate an address range into an address space * into a MemoryRegion and an address range into that section diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index 3f2f4c89e3..efa8b9993a 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -88,7 +88,8 @@ static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr, void *buf, dma_addr_t len, DMADirection dir) { - return address_space_rw(as, addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE); + return (bool)address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, + buf, len, dir == DMA_DIRECTION_FROM_DEVICE); } static inline int dma_memory_read_relaxed(AddressSpace *as, dma_addr_t addr, diff --git a/ioport.c b/ioport.c index 783a3ae675..b345bd9abe 100644 --- a/ioport.c +++ b/ioport.c @@ -64,7 +64,8 @@ void cpu_outb(pio_addr_t addr, uint8_t val) { LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); trace_cpu_out(addr, val); - address_space_write(&address_space_io, addr, &val, 1); + address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + &val, 1); } void cpu_outw(pio_addr_t addr, uint16_t val) @@ -74,7 +75,8 @@ void cpu_outw(pio_addr_t addr, uint16_t val) LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); trace_cpu_out(addr, val); stw_p(buf, val); - address_space_write(&address_space_io, addr, buf, 2); + address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + buf, 2); } void cpu_outl(pio_addr_t addr, uint32_t val) @@ -84,14 +86,16 @@ void cpu_outl(pio_addr_t addr, uint32_t val) LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); trace_cpu_out(addr, val); stl_p(buf, val); - address_space_write(&address_space_io, addr, buf, 4); + address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + buf, 4); } uint8_t cpu_inb(pio_addr_t addr) { uint8_t val; - address_space_read(&address_space_io, addr, &val, 1); + address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, + &val, 1); trace_cpu_in(addr, val); LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); return val; @@ -102,7 +106,7 @@ uint16_t cpu_inw(pio_addr_t addr) uint8_t buf[2]; uint16_t val; - address_space_read(&address_space_io, addr, buf, 2); + address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, buf, 2); val = lduw_p(buf); trace_cpu_in(addr, val); LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); @@ -114,7 +118,7 @@ uint32_t cpu_inl(pio_addr_t addr) uint8_t buf[4]; uint32_t val; - address_space_read(&address_space_io, addr, buf, 4); + address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, buf, 4); val = ldl_p(buf); trace_cpu_in(addr, val); LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); diff --git a/kvm-all.c b/kvm-all.c index dd44f8c753..4ec153df93 100644 --- a/kvm-all.c +++ b/kvm-all.c @@ -1667,7 +1667,8 @@ static void kvm_handle_io(uint16_t port, void *data, int direction, int size, uint8_t *ptr = data; for (i = 0; i < count; i++) { - address_space_rw(&address_space_io, port, ptr, size, + address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED, + ptr, size, direction == KVM_EXIT_IO_OUT); ptr += size; } diff --git a/scripts/coverity-model.c b/scripts/coverity-model.c index cdda2591d9..224d2d1873 100644 --- a/scripts/coverity-model.c +++ b/scripts/coverity-model.c @@ -46,6 +46,8 @@ typedef struct va_list_str *va_list; typedef struct AddressSpace AddressSpace; typedef uint64_t hwaddr; +typedef uint32_t MemTxResult; +typedef uint64_t MemTxAttrs; static void __write(uint8_t *buf, ssize_t len) { @@ -65,10 +67,10 @@ static void __read(uint8_t *buf, ssize_t len) int last = buf[len-1]; } -bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf, - int len, bool is_write) +MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, + uint8_t *buf, int len, bool is_write) { - bool result; + MemTxResult result; // TODO: investigate impact of treating reads as producing // tainted data, with __coverity_tainted_data_argument__(buf). -- cgit v1.2.3-55-g7522 From 500131154d677930fce35ec3a6f0b5a26bcd2973 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:24 +0100 Subject: exec.c: Add new address_space_ld*/st* functions Add new address_space_ld*/st* functions which allow transaction attributes and error reporting for basic load and stores. These are named to be in line with the address_space_read/write/rw buffer operations. The existing ld/st*_phys functions are now wrappers around the new functions. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée --- exec.c | 297 +++++++++++++++++++++++++++++++++++++++++--------- include/exec/memory.h | 67 ++++++++++++ 2 files changed, 314 insertions(+), 50 deletions(-) (limited to 'include/exec') diff --git a/exec.c b/exec.c index 9811a9cbc0..399543ef98 100644 --- a/exec.c +++ b/exec.c @@ -2679,20 +2679,22 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len, } /* warning: addr must be aligned */ -static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr, - enum device_endian endian) +static inline uint32_t address_space_ldl_internal(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; uint64_t val; MemoryRegion *mr; hwaddr l = 4; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, false); if (l < 4 || !memory_access_is_direct(mr, false)) { /* I/O case */ - memory_region_dispatch_read(mr, addr1, &val, 4, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap32(val); @@ -2718,41 +2720,68 @@ static inline uint32_t ldl_phys_internal(AddressSpace *as, hwaddr addr, val = ldl_p(ptr); break; } + r = MEMTX_OK; + } + if (result) { + *result = r; } return val; } +uint32_t address_space_ldl(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldl_internal(as, addr, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +uint32_t address_space_ldl_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldl_internal(as, addr, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +uint32_t address_space_ldl_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldl_internal(as, addr, attrs, result, + DEVICE_BIG_ENDIAN); +} + uint32_t ldl_phys(AddressSpace *as, hwaddr addr) { - return ldl_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN); + return address_space_ldl(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr) { - return ldl_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN); + return address_space_ldl_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr) { - return ldl_phys_internal(as, addr, DEVICE_BIG_ENDIAN); + return address_space_ldl_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } /* warning: addr must be aligned */ -static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr, - enum device_endian endian) +static inline uint64_t address_space_ldq_internal(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; uint64_t val; MemoryRegion *mr; hwaddr l = 8; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, false); if (l < 8 || !memory_access_is_direct(mr, false)) { /* I/O case */ - memory_region_dispatch_read(mr, addr1, &val, 8, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap64(val); @@ -2778,49 +2807,88 @@ static inline uint64_t ldq_phys_internal(AddressSpace *as, hwaddr addr, val = ldq_p(ptr); break; } + r = MEMTX_OK; + } + if (result) { + *result = r; } return val; } +uint64_t address_space_ldq(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldq_internal(as, addr, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +uint64_t address_space_ldq_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldq_internal(as, addr, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +uint64_t address_space_ldq_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldq_internal(as, addr, attrs, result, + DEVICE_BIG_ENDIAN); +} + uint64_t ldq_phys(AddressSpace *as, hwaddr addr) { - return ldq_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN); + return address_space_ldq(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr) { - return ldq_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN); + return address_space_ldq_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr) { - return ldq_phys_internal(as, addr, DEVICE_BIG_ENDIAN); + return address_space_ldq_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } /* XXX: optimize */ -uint32_t ldub_phys(AddressSpace *as, hwaddr addr) +uint32_t address_space_ldub(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) { uint8_t val; - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &val, 1, 0); + MemTxResult r; + + r = address_space_rw(as, addr, attrs, &val, 1, 0); + if (result) { + *result = r; + } return val; } +uint32_t ldub_phys(AddressSpace *as, hwaddr addr) +{ + return address_space_ldub(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); +} + /* warning: addr must be aligned */ -static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr, - enum device_endian endian) +static inline uint32_t address_space_lduw_internal(AddressSpace *as, + hwaddr addr, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; uint64_t val; MemoryRegion *mr; hwaddr l = 2; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, false); if (l < 2 || !memory_access_is_direct(mr, false)) { /* I/O case */ - memory_region_dispatch_read(mr, addr1, &val, 2, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap16(val); @@ -2846,40 +2914,66 @@ static inline uint32_t lduw_phys_internal(AddressSpace *as, hwaddr addr, val = lduw_p(ptr); break; } + r = MEMTX_OK; + } + if (result) { + *result = r; } return val; } +uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_lduw_internal(as, addr, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +uint32_t address_space_lduw_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_lduw_internal(as, addr, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +uint32_t address_space_lduw_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_lduw_internal(as, addr, attrs, result, + DEVICE_BIG_ENDIAN); +} + uint32_t lduw_phys(AddressSpace *as, hwaddr addr) { - return lduw_phys_internal(as, addr, DEVICE_NATIVE_ENDIAN); + return address_space_lduw(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr) { - return lduw_phys_internal(as, addr, DEVICE_LITTLE_ENDIAN); + return address_space_lduw_le(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr) { - return lduw_phys_internal(as, addr, DEVICE_BIG_ENDIAN); + return address_space_lduw_be(as, addr, MEMTXATTRS_UNSPECIFIED, NULL); } /* warning: addr must be aligned. The ram page is not masked as dirty and the code inside is not invalidated. It is useful if the dirty bits are used to track modified PTEs */ -void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) +void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) { uint8_t *ptr; MemoryRegion *mr; hwaddr l = 4; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, true); if (l < 4 || !memory_access_is_direct(mr, true)) { - memory_region_dispatch_write(mr, addr1, val, 4, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); } else { addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; ptr = qemu_get_ram_ptr(addr1); @@ -2893,18 +2987,30 @@ void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) cpu_physical_memory_set_dirty_range_nocode(addr1, 4); } } + r = MEMTX_OK; + } + if (result) { + *result = r; } } +void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) +{ + address_space_stl_notdirty(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); +} + /* warning: addr must be aligned */ -static inline void stl_phys_internal(AddressSpace *as, - hwaddr addr, uint32_t val, - enum device_endian endian) +static inline void address_space_stl_internal(AddressSpace *as, + hwaddr addr, uint32_t val, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; MemoryRegion *mr; hwaddr l = 4; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, true); @@ -2918,8 +3024,7 @@ static inline void stl_phys_internal(AddressSpace *as, val = bswap32(val); } #endif - memory_region_dispatch_write(mr, addr1, val, 4, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); } else { /* RAM case */ addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; @@ -2936,40 +3041,79 @@ static inline void stl_phys_internal(AddressSpace *as, break; } invalidate_and_set_dirty(addr1, 4); + r = MEMTX_OK; + } + if (result) { + *result = r; } } +void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stl_internal(as, addr, val, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +void address_space_stl_le(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stl_internal(as, addr, val, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +void address_space_stl_be(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stl_internal(as, addr, val, attrs, result, + DEVICE_BIG_ENDIAN); +} + void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stl_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN); + address_space_stl(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stl_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN); + address_space_stl_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stl_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN); + address_space_stl_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } /* XXX: optimize */ -void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val) +void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) { uint8_t v = val; - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &v, 1, 1); + MemTxResult r; + + r = address_space_rw(as, addr, attrs, &v, 1, 1); + if (result) { + *result = r; + } +} + +void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val) +{ + address_space_stb(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } /* warning: addr must be aligned */ -static inline void stw_phys_internal(AddressSpace *as, - hwaddr addr, uint32_t val, - enum device_endian endian) +static inline void address_space_stw_internal(AddressSpace *as, + hwaddr addr, uint32_t val, + MemTxAttrs attrs, + MemTxResult *result, + enum device_endian endian) { uint8_t *ptr; MemoryRegion *mr; hwaddr l = 2; hwaddr addr1; + MemTxResult r; mr = address_space_translate(as, addr, &addr1, &l, true); if (l < 2 || !memory_access_is_direct(mr, true)) { @@ -2982,8 +3126,7 @@ static inline void stw_phys_internal(AddressSpace *as, val = bswap16(val); } #endif - memory_region_dispatch_write(mr, addr1, val, 2, - MEMTXATTRS_UNSPECIFIED); + r = memory_region_dispatch_write(mr, addr1, val, 2, attrs); } else { /* RAM case */ addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK; @@ -3000,41 +3143,95 @@ static inline void stw_phys_internal(AddressSpace *as, break; } invalidate_and_set_dirty(addr1, 2); + r = MEMTX_OK; + } + if (result) { + *result = r; } } +void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stw_internal(as, addr, val, attrs, result, + DEVICE_NATIVE_ENDIAN); +} + +void address_space_stw_le(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stw_internal(as, addr, val, attrs, result, + DEVICE_LITTLE_ENDIAN); +} + +void address_space_stw_be(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stw_internal(as, addr, val, attrs, result, + DEVICE_BIG_ENDIAN); +} + void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stw_phys_internal(as, addr, val, DEVICE_NATIVE_ENDIAN); + address_space_stw(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stw_phys_internal(as, addr, val, DEVICE_LITTLE_ENDIAN); + address_space_stw_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val) { - stw_phys_internal(as, addr, val, DEVICE_BIG_ENDIAN); + address_space_stw_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } /* XXX: optimize */ -void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val) +void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result) { + MemTxResult r; val = tswap64(val); - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); + r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); + if (result) { + *result = r; + } } -void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val) +void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result) { + MemTxResult r; val = cpu_to_le64(val); - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); + r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); + if (result) { + *result = r; + } +} +void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result) +{ + MemTxResult r; + val = cpu_to_be64(val); + r = address_space_rw(as, addr, attrs, (void *) &val, 8, 1); + if (result) { + *result = r; + } +} + +void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val) +{ + address_space_stq(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); +} + +void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val) +{ + address_space_stq_le(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val) { - val = cpu_to_be64(val); - address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1); + address_space_stq_be(as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } /* virtual memory access for debug (includes writing to ROM) */ diff --git a/include/exec/memory.h b/include/exec/memory.h index cafd590b92..2f386cecb7 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1153,6 +1153,73 @@ MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, uint8_t *buf, int len); +/** + * address_space_ld*: load from an address space + * address_space_st*: store to an address space + * + * These functions perform a load or store of the byte, word, + * longword or quad to the specified address within the AddressSpace. + * The _le suffixed functions treat the data as little endian; + * _be indicates big endian; no suffix indicates "same endianness + * as guest CPU". + * + * The "guest CPU endianness" accessors are deprecated for use outside + * target-* code; devices should be CPU-agnostic and use either the LE + * or the BE accessors. + * + * @as #AddressSpace to be accessed + * @addr: address within that address space + * @val: data value, for stores + * @attrs: memory transaction attributes + * @result: location to write the success/failure of the transaction; + * if NULL, this information is discarded + */ +uint32_t address_space_ldub(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_lduw_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_lduw_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_ldl_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_ldl_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint64_t address_space_ldq_le(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint64_t address_space_ldq_be(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stb(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stw_le(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stw_be(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stl_le(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stl_be(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stq_le(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stq_be(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result); + +#ifdef NEED_CPU_H +uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint32_t address_space_ldl(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +uint64_t address_space_ldq(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val, + MemTxAttrs attrs, MemTxResult *result); +void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val, + MemTxAttrs attrs, MemTxResult *result); +#endif + /* address_space_translate: translate an address range into an address space * into a MemoryRegion and an address range into that section * -- cgit v1.2.3-55-g7522 From 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:25 +0100 Subject: target-arm: Honour NS bits in page tables Honour the NS bit in ARM page tables: * when adding entries to the TLB, include the Secure/NonSecure transaction attribute * set the NS bit in the PAR when doing ATS operations Note that we don't yet correctly use the NSTable bit to cause the page table walk itself to use the right attributes. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée --- include/exec/memattrs.h | 2 ++ target-arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 69 insertions(+), 12 deletions(-) (limited to 'include/exec') diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 1cb3fc0815..68a9c760d5 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -29,6 +29,8 @@ typedef struct MemTxAttrs { * "didn't specify" if necessary. */ unsigned int unspecified:1; + /* ARM/AMBA TrustZone Secure access */ + unsigned int secure:1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, diff --git a/target-arm/helper.c b/target-arm/helper.c index d77c6de40c..a568299cc6 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -14,7 +14,7 @@ #ifndef CONFIG_USER_ONLY static inline int get_phys_addr(CPUARMState *env, target_ulong address, int access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size); /* Definitions for the PMCCNTR and PMCR registers */ @@ -1466,9 +1466,10 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, int prot; int ret; uint64_t par64; + MemTxAttrs attrs = {}; ret = get_phys_addr(env, value, access_type, mmu_idx, - &phys_addr, &prot, &page_size); + &phys_addr, &attrs, &prot, &page_size); if (extended_addresses_enabled(env)) { /* ret is a DFSR/IFSR value for the long descriptor * translation table format, but with WnR always clear. @@ -1477,6 +1478,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 = (1 << 11); /* LPAE bit always set */ if (ret == 0) { par64 |= phys_addr & ~0xfffULL; + if (!attrs.secure) { + par64 |= (1 << 9); /* NS */ + } /* We don't set the ATTR or SH fields in the PAR. */ } else { par64 |= 1; /* F */ @@ -1499,6 +1503,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, } else { par64 = phys_addr & 0xfffff000; } + if (!attrs.secure) { + par64 |= (1 << 9); /* NS */ + } } else { par64 = ((ret & (1 << 10)) >> 5) | ((ret & (1 << 12)) >> 6) | ((ret & 0xf) << 1) | 1; @@ -4858,6 +4865,26 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) } } +/* Return true if this address translation regime is secure */ +static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_S12NSE0: + case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_S1E2: + case ARMMMUIdx_S2NS: + return false; + case ARMMMUIdx_S1E3: + case ARMMMUIdx_S1SE0: + case ARMMMUIdx_S1SE1: + return true; + default: + g_assert_not_reached(); + } +} + /* Return the SCTLR value which controls this address translation regime */ static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -5210,6 +5237,7 @@ do_fault: static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, + MemTxAttrs *attrs, int *prot, target_ulong *page_size) { CPUState *cs = CPU(arm_env_get_cpu(env)); @@ -5224,6 +5252,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, int domain_prot; hwaddr phys_addr; uint32_t dacr; + bool ns; /* Pagetable walk. */ /* Lookup l1 descriptor. */ @@ -5273,10 +5302,12 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, xn = desc & (1 << 4); pxn = desc & 1; code = 13; + ns = extract32(desc, 19, 1); } else { if (arm_feature(env, ARM_FEATURE_PXN)) { pxn = (desc >> 2) & 1; } + ns = extract32(desc, 3, 1); /* Lookup l2 entry. */ table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); desc = ldl_phys(cs->as, table); @@ -5330,6 +5361,13 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, goto do_fault; } } + if (ns) { + /* The NS bit will (as required by the architecture) have no effect if + * the CPU doesn't support TZ or this is a non-secure translation + * regime, because the attribute will already be non-secure. + */ + attrs->secure = false; + } *phys_ptr = phys_addr; return 0; do_fault: @@ -5347,7 +5385,7 @@ typedef enum { static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, int access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, + hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size_ptr) { CPUState *cs = CPU(arm_env_get_cpu(env)); @@ -5552,6 +5590,13 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, goto do_fault; } + if (ns) { + /* The NS bit will (as required by the architecture) have no effect if + * the CPU doesn't support TZ or this is a non-secure translation + * regime, because the attribute will already be non-secure. + */ + txattrs->secure = false; + } *phys_ptr = descaddr; *page_size_ptr = page_size; return 0; @@ -5635,8 +5680,8 @@ static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, * by doing a translation table walk on MMU based systems or using the * MPU state on MPU based systems. * - * Returns 0 if the translation was successful. Otherwise, phys_ptr, - * prot and page_size are not filled in, and the return value provides + * Returns 0 if the translation was successful. Otherwise, phys_ptr, attrs, + * prot and page_size may not be filled in, and the return value provides * information on why the translation aborted, in the format of a * DFSR/IFSR fault register, with the following caveats: * * we honour the short vs long DFSR format differences. @@ -5649,12 +5694,13 @@ static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, * @access_type: 0 for read, 1 for write, 2 for execute * @mmu_idx: MMU index indicating required translation regime * @phys_ptr: set to the physical address corresponding to the virtual address + * @attrs: set to the memory transaction attributes to use * @prot: set to the permissions for the page containing phys_ptr * @page_size: set to the size of the page containing phys_ptr */ static inline int get_phys_addr(CPUARMState *env, target_ulong address, int access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size) { if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { @@ -5667,6 +5713,12 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address, mmu_idx += ARMMMUIdx_S1NSE0; } + /* The page table entries may downgrade secure to non-secure, but + * cannot upgrade an non-secure translation regime's attributes + * to secure. + */ + attrs->secure = regime_is_secure(env, mmu_idx); + /* Fast Context Switch Extension. This doesn't exist at all in v8. * In v7 and earlier it affects all stage 1 translations. */ @@ -5695,10 +5747,10 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address, if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, - prot, page_size); + attrs, prot, page_size); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, - prot, page_size); + attrs, prot, page_size); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, prot, page_size); @@ -5716,14 +5768,16 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int ret; uint32_t syn; bool same_el = (arm_current_el(env) != 0); + MemTxAttrs attrs = {}; - ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr, &prot, - &page_size); + ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr, + &attrs, &prot, &page_size); if (ret == 0) { /* Map a single [sub]page. */ phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; - tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size); + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, + prot, mmu_idx, page_size); return 0; } @@ -5758,9 +5812,10 @@ hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) target_ulong page_size; int prot; int ret; + MemTxAttrs attrs = {}; ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env), &phys_addr, - &prot, &page_size); + &attrs, &prot, &page_size); if (ret != 0) { return -1; -- cgit v1.2.3-55-g7522 From 0995bf8cd91b81ec9c1078e37b808794080dc5c0 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 26 Apr 2015 16:49:25 +0100 Subject: target-arm: Add user-mode transaction attribute Add a transaction attribute indicating that a memory access is being done from user-mode (unprivileged). This corresponds to an equivalent signal in ARM AMBA buses. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée --- include/exec/memattrs.h | 2 ++ target-arm/helper.c | 1 + 2 files changed, 3 insertions(+) (limited to 'include/exec') diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 68a9c760d5..1389b4b01d 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -31,6 +31,8 @@ typedef struct MemTxAttrs { unsigned int unspecified:1; /* ARM/AMBA TrustZone Secure access */ unsigned int secure:1; + /* Memory access is usermode (unprivileged) */ + unsigned int user:1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, diff --git a/target-arm/helper.c b/target-arm/helper.c index a01ff7fccc..50469cdae0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5749,6 +5749,7 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address, * to secure. */ attrs->secure = regime_is_secure(env, mmu_idx); + attrs->user = regime_is_user(env, mmu_idx); /* Fast Context Switch Extension. This doesn't exist at all in v8. * In v7 and earlier it affects all stage 1 translations. -- cgit v1.2.3-55-g7522